From 274c376f31e365d067a5473ee3e5140c16aeb3c4 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 2 Oct 2013 12:40:31 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6346 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32F1xx/adc_lld.c | 1 - os/hal/ports/STM32F1xx/ext_lld_isr.c | 109 ++--- os/hal/ports/STM32F1xx/hal_lld.c | 12 - os/hal/ports/STM32F1xx/hal_lld.h | 56 ++- os/hal/ports/STM32F1xx/hal_lld_f100.h | 377 --------------- os/hal/ports/STM32F1xx/hal_lld_f103.h | 700 --------------------------- os/hal/ports/STM32F1xx/hal_lld_f105_f107.h | 232 --------- os/hal/ports/STM32F1xx/platform.mk | 57 +-- os/hal/ports/STM32F1xx/platform_f105_f107.mk | 56 +-- os/hal/ports/STM32F1xx/stm32_dma.c | 95 ++-- os/hal/ports/STM32F1xx/stm32_dma.h | 8 +- 11 files changed, 200 insertions(+), 1503 deletions(-) (limited to 'os/hal/ports/STM32F1xx') diff --git a/os/hal/ports/STM32F1xx/adc_lld.c b/os/hal/ports/STM32F1xx/adc_lld.c index 9e9bbfb7d..8f7ea5d29 100644 --- a/os/hal/ports/STM32F1xx/adc_lld.c +++ b/os/hal/ports/STM32F1xx/adc_lld.c @@ -22,7 +22,6 @@ * @{ */ -#include "ch.h" #include "hal.h" #if HAL_USE_ADC || defined(__DOXYGEN__) diff --git a/os/hal/ports/STM32F1xx/ext_lld_isr.c b/os/hal/ports/STM32F1xx/ext_lld_isr.c index ee4236c9b..1b6d6eca2 100644 --- a/os/hal/ports/STM32F1xx/ext_lld_isr.c +++ b/os/hal/ports/STM32F1xx/ext_lld_isr.c @@ -22,7 +22,6 @@ * @{ */ -#include "ch.h" #include "hal.h" #if HAL_USE_EXT || defined(__DOXYGEN__) @@ -54,14 +53,14 @@ * * @isr */ -CH_IRQ_HANDLER(EXTI0_IRQHandler) { +OSAL_IRQ_HANDLER(EXTI0_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 0); EXTD1.config->channels[0].cb(&EXTD1, 0); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -69,14 +68,14 @@ CH_IRQ_HANDLER(EXTI0_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(EXTI1_IRQHandler) { +OSAL_IRQ_HANDLER(EXTI1_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 1); EXTD1.config->channels[1].cb(&EXTD1, 1); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -84,14 +83,14 @@ CH_IRQ_HANDLER(EXTI1_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(EXTI2_IRQHandler) { +OSAL_IRQ_HANDLER(EXTI2_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 2); EXTD1.config->channels[2].cb(&EXTD1, 2); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -99,14 +98,14 @@ CH_IRQ_HANDLER(EXTI2_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(EXTI3_IRQHandler) { +OSAL_IRQ_HANDLER(EXTI3_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 3); EXTD1.config->channels[3].cb(&EXTD1, 3); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -114,14 +113,14 @@ CH_IRQ_HANDLER(EXTI3_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(EXTI4_IRQHandler) { +OSAL_IRQ_HANDLER(EXTI4_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 4); EXTD1.config->channels[4].cb(&EXTD1, 4); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -129,10 +128,10 @@ CH_IRQ_HANDLER(EXTI4_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { +OSAL_IRQ_HANDLER(EXTI9_5_IRQHandler) { uint32_t pr; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9)); EXTI->PR = pr; @@ -147,7 +146,7 @@ CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { if (pr & (1 << 9)) EXTD1.config->channels[9].cb(&EXTD1, 9); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -155,10 +154,10 @@ CH_IRQ_HANDLER(EXTI9_5_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { +OSAL_IRQ_HANDLER(EXTI15_10_IRQHandler) { uint32_t pr; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | (1 << 15)); @@ -176,7 +175,7 @@ CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { if (pr & (1 << 15)) EXTD1.config->channels[15].cb(&EXTD1, 15); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -184,14 +183,14 @@ CH_IRQ_HANDLER(EXTI15_10_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(PVD_IRQHandler) { +OSAL_IRQ_HANDLER(PVD_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 16); EXTD1.config->channels[16].cb(&EXTD1, 16); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -199,14 +198,14 @@ CH_IRQ_HANDLER(PVD_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) { +OSAL_IRQ_HANDLER(RTC_Alarm_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 17); EXTD1.config->channels[17].cb(&EXTD1, 17); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #if defined(STM32F10X_CL) @@ -215,14 +214,14 @@ CH_IRQ_HANDLER(RTC_Alarm_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) { +OSAL_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 18); EXTD1.config->channels[18].cb(&EXTD1, 18); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -230,14 +229,14 @@ CH_IRQ_HANDLER(OTG_FS_WKUP_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) { +OSAL_IRQ_HANDLER(ETH_WKUP_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 19); EXTD1.config->channels[19].cb(&EXTD1, 19); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ defined(STM32F10X_HD_VL) @@ -248,14 +247,14 @@ CH_IRQ_HANDLER(ETH_WKUP_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) { +OSAL_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); EXTI->PR = (1 << 18); EXTD1.config->channels[18].cb(&EXTD1, 18); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif @@ -270,37 +269,25 @@ CH_IRQ_HANDLER(USB_FS_WKUP_IRQHandler) { */ void ext_lld_exti_irq_enable(void) { - nvicEnableVector(EXTI0_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY)); - nvicEnableVector(EXTI1_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY)); - nvicEnableVector(EXTI2_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY)); - nvicEnableVector(EXTI3_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY)); - nvicEnableVector(EXTI4_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY)); - nvicEnableVector(EXTI9_5_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY)); - nvicEnableVector(EXTI15_10_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY)); - nvicEnableVector(PVD_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY)); - nvicEnableVector(RTC_Alarm_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY)); + nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY); + nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY); + nvicEnableVector(EXTI2_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY); + nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY); + nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY); + nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY); + nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY); + nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY); + nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY); #if defined(STM32F10X_CL) /* EXTI vectors specific to STM32F1xx Connectivity Line.*/ - nvicEnableVector(OTG_FS_WKUP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); - nvicEnableVector(ETH_WKUP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY)); + nvicEnableVector(OTG_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); + nvicEnableVector(ETH_WKUP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY); #elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ defined(STM32F10X_HD_VL) /* EXTI vectors specific to STM32F1xx Value Line.*/ #else /* EXTI vectors specific to STM32F1xx except Connectivity Line.*/ - nvicEnableVector(USB_FS_WKUP_IRQn, - CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY)); + nvicEnableVector(USB_FS_WKUP_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY); #endif } diff --git a/os/hal/ports/STM32F1xx/hal_lld.c b/os/hal/ports/STM32F1xx/hal_lld.c index eb87a1a84..301f26fb9 100644 --- a/os/hal/ports/STM32F1xx/hal_lld.c +++ b/os/hal/ports/STM32F1xx/hal_lld.c @@ -22,7 +22,6 @@ * @{ */ -#include "ch.h" #include "hal.h" /*===========================================================================*/ @@ -102,17 +101,6 @@ void hal_lld_init(void) { rccResetAPB1(0xFFFFFFFF); rccResetAPB2(0xFFFFFFFF); - /* SysTick initialization using the system clock.*/ - SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; - - /* DWT cycle counter enable.*/ - SCS_DEMCR |= SCS_DEMCR_TRCENA; - DWT_CTRL |= DWT_CTRL_CYCCNTENA; - /* PWR and BD clocks enabled.*/ rccEnablePWRInterface(FALSE); rccEnableBKPInterface(FALSE); diff --git a/os/hal/ports/STM32F1xx/hal_lld.h b/os/hal/ports/STM32F1xx/hal_lld.h index 4c3734da7..7498ea48c 100644 --- a/os/hal/ports/STM32F1xx/hal_lld.h +++ b/os/hal/ports/STM32F1xx/hal_lld.h @@ -41,10 +41,48 @@ #ifndef _HAL_LLD_H_ #define _HAL_LLD_H_ +#include "stm32_registry.h" + /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ +/** + * @name Platform identification + * @{ + */ +#if defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32F1xx" + +#elif defined(STM32F10X_LD_VL) +#define PLATFORM_NAME "STM32F100 Value Line Low Density" + +#elif defined(STM32F10X_MD_VL) +#define PLATFORM_NAME "STM32F100 Value Line Medium Density" + +#elif defined(STM32F10X_HD_VL) +#define PLATFORM_NAME "STM32F100 Value Line High Density" + +#elif defined(STM32F10X_LD) +#define PLATFORM_NAME "STM32F10x Performance Line Low Density" + +#elif defined(STM32F10X_MD) +#define PLATFORM_NAME "STM32F10x Performance Line Medium Density" + +#elif defined(STM32F10X_HD) +#define PLATFORM_NAME "STM32F10x Performance Line High Density" + +#elif defined(STM32F10X_XL) +#define PLATFORM_NAME "STM32F10x Performance Line eXtra Density" + +#elif defined(STM32F10X_CL) +#define PLATFORM_NAME "STM32F10x Connectivity Line" + +#else +#error "unsupported or unrecognized STM32F1xx member" +#endif +/** @} */ + /** * @name Internal clock sources * @{ @@ -134,16 +172,8 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if defined(__DOXYGEN__) -/** - * @name Platform identification - * @{ - */ -#define PLATFORM_NAME "STM32" -/** @} */ - -#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ - defined(STM32F10X_HD_VL) || defined(__DOXYGEN__) +#if defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \ + defined(STM32F10X_HD_VL) || defined(__DOXYGEN__) #include "hal_lld_f100.h" #elif defined(STM32F10X_LD) || defined(STM32F10X_MD) || \ @@ -153,9 +183,6 @@ #elif defined(STM32F10X_CL) || defined(__DOXYGEN__) #include "hal_lld_f105_f107.h" - -#else -#error "unspecified, unsupported or invalid STM32 platform" #endif /*===========================================================================*/ @@ -170,7 +197,8 @@ /* External declarations. */ /*===========================================================================*/ -/* STM32 ISR, DMA and RCC helpers.*/ +/* Various helpers.*/ +#include "nvic.h" #include "stm32_isr.h" #include "stm32_dma.h" #include "stm32_rcc.h" diff --git a/os/hal/ports/STM32F1xx/hal_lld_f100.h b/os/hal/ports/STM32F1xx/hal_lld_f100.h index ce5b591f4..232d479c5 100644 --- a/os/hal/ports/STM32F1xx/hal_lld_f100.h +++ b/os/hal/ports/STM32F1xx/hal_lld_f100.h @@ -36,23 +36,6 @@ /* Driver constants. */ /*===========================================================================*/ -/** - * @name Platform identification - * @{ - */ -#if defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32F100 Value Line" - -#elif defined(STM32F10X_LD_VL) -#define PLATFORM_NAME "STM32F100 Value Line Low Density" - -#elif defined(STM32F10X_MD_VL) -#define PLATFORM_NAME "STM32F100 Value Line Medium Density" -#else -#error "unsupported STM32 Value Line member" -#endif -/** @} */ - /** * @name Absolute Maximum Ratings * @{ @@ -178,366 +161,6 @@ RTC clock. */ /** @} */ -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -#if defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) -/** - * @name STM32F100 LD capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 0 - -/* DAC attributes.*/ -#define STM32_HAS_DAC TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 18 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE FALSE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 FALSE -#define STM32_I2C2_RX_DMA_MSK 0 -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK 0 -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 FALSE -#define STM32_SPI2_RX_DMA_MSK 0 -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK 0 -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 TRUE -#define STM32_HAS_TIM16 TRUE -#define STM32_HAS_TIM17 TRUE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 FALSE -#define STM32_USART3_RX_DMA_MSK 0 -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK 0 -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 FALSE -#define STM32_UART4_RX_DMA_MSK 0 -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK 0 -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 FALSE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ -#endif /* defined(STM32F10X_LD_VL) */ - -#if defined(STM32F10X_MD_VL) || defined(__DOXYGEN__) -/** - * @name STM32F100 MD capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 FALSE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 0 - -/* DAC attributes.*/ -#define STM32_HAS_DAC TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 19 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 TRUE -#define STM32_HAS_TIM16 TRUE -#define STM32_HAS_TIM17 TRUE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 FALSE -#define STM32_UART4_RX_DMA_MSK 0 -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK 0 -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 FALSE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ -#endif /* defined(STM32F10X_MD_VL) */ - -/*===========================================================================*/ -/* Platform specific friendly IRQ names. */ -/*===========================================================================*/ - -/** - * @name IRQ VECTOR names - * @{ - */ -#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ -#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line - detect. */ -#define TAMPER_IRQHandler Vector48 /**< Tamper. */ -#define RTC_IRQHandler Vector4C /**< RTC. */ -#define FLASH_IRQHandler Vector50 /**< Flash. */ -#define RCC_IRQHandler Vector54 /**< RCC. */ -#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ -#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ -#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ -#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ -#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ -#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ -#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ -#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ -#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ -#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ -#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ -#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ -#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ -#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ -#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ -#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ -#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and - Commutation. */ -#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ -#define TIM2_IRQHandler VectorB0 /**< TIM2. */ -#define TIM3_IRQHandler VectorB4 /**< TIM3. */ -#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) -#define TIM4_IRQHandler VectorB8 /**< TIM4. */ -#endif -#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ -#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ -#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) -#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ -#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ -#endif -#define SPI1_IRQHandler VectorCC /**< SPI1. */ -#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) -#define SPI2_IRQHandler VectorD0 /**< SPI2. */ -#endif -#define USART1_IRQHandler VectorD4 /**< USART1. */ -#define USART2_IRQHandler VectorD8 /**< USART2. */ -#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__) -#define USART3_IRQHandler VectorDC /**< USART3. */ -#endif -#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ -#define CEC_IRQHandler VectorE8 /**< CEC. */ -#define TIM12_IRQHandler VectorEC /**< TIM12. */ -#define TIM13_IRQHandler VectorF0 /**< TIM13. */ -#define TIM14_IRQHandler VectorF4 /**< TIM14. */ -/** @} */ - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32F1xx/hal_lld_f103.h b/os/hal/ports/STM32F1xx/hal_lld_f103.h index 813970305..280d9e5fb 100644 --- a/os/hal/ports/STM32F1xx/hal_lld_f103.h +++ b/os/hal/ports/STM32F1xx/hal_lld_f103.h @@ -36,30 +36,6 @@ /* Driver constants. */ /*===========================================================================*/ -/** - * @name Platform identification - * @{ - */ -#if defined(__DOXYGEN__) -#define PLATFORM_NAME "STM32F10x Performance Line" - -#elif defined(STM32F10X_LD) -#define PLATFORM_NAME "STM32F10x Performance Line Low Density" - -#elif defined(STM32F10X_MD) -#define PLATFORM_NAME "STM32F10x Performance Line Medium Density" - -#elif defined(STM32F10X_HD) -#define PLATFORM_NAME "STM32F10x Performance Line High Density" - -#elif defined(STM32F10X_XL) -#define PLATFORM_NAME "STM32F10x Performance Line eXtra Density" - -#else -#error "unsupported STM32 Performance Line member" -#endif -/** @} */ - /** * @name Absolute Maximum Ratings * @{ @@ -188,682 +164,6 @@ RTC clock. */ /** @} */ -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -#if defined(STM32F10X_LD) || defined(__DOXYGEN__) -/** - * @name STM32F103 LD capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 14 - -/* DAC attributes.*/ -#define STM32_HAS_DAC FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 19 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE FALSE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 FALSE -#define STM32_I2C2_RX_DMA_MSK 0 -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK 0 -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 FALSE -#define STM32_SPI2_RX_DMA_MSK 0 -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK 0 -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 FALSE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 FALSE -#define STM32_USART3_RX_DMA_MSK 0 -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK 0 -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 FALSE -#define STM32_UART4_RX_DMA_MSK 0 -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK 0 -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 FALSE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ -#endif /* defined(STM32F10X_LD) */ - -#if defined(STM32F10X_MD) || defined(__DOXYGEN__) -/** - * @name STM32F103 MD capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 14 - -/* DAC attributes.*/ -#define STM32_HAS_DAC FALSE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 FALSE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 19 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTCSEL_HAS_SUBSECONDS TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 FALSE -#define STM32_SPI3_RX_DMA_MSK 0 -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK 0 -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 FALSE -#define STM32_HAS_TIM7 FALSE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 FALSE -#define STM32_UART4_RX_DMA_MSK 0 -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK 0 -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 FALSE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ -#endif /* defined(STM32F10X_MD) */ - -#if defined(STM32F10X_HD) || defined(__DOXYGEN__) -/** - * @name STM32F103 HD capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 TRUE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 14 - -/* DAC attributes.*/ -#define STM32_HAS_DAC TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 19 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTCSEL_HAS_SUBSECONDS TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO TRUE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 TRUE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 TRUE -#define STM32_HAS_TIM9 TRUE -#define STM32_HAS_TIM10 TRUE -#define STM32_HAS_TIM11 TRUE -#define STM32_HAS_TIM12 TRUE -#define STM32_HAS_TIM13 TRUE -#define STM32_HAS_TIM14 TRUE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 TRUE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ -#endif /* defined(STM32F10X_HD) */ - -#if defined(STM32F10X_XL) || defined(__DOXYGEN__) -/** - * @name STM32F103 XL capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 TRUE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 14 - -/* DAC attributes.*/ -#define STM32_HAS_DAC TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE - -/* ETH attributes.*/ -#define STM32_HAS_ETH FALSE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 19 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF TRUE -#define STM32_HAS_GPIOG TRUE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 - -/* RTC attributes.*/ -#define STM32_HAS_RTC TRUE -#define STM32_RTCSEL_HAS_SUBSECONDS TRUE - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO TRUE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 TRUE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 TRUE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 TRUE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB TRUE -#define STM32_HAS_OTG1 FALSE -#define STM32_HAS_OTG2 FALSE -/** @} */ -#endif /* defined(STM32F10X_XL) */ - -/*===========================================================================*/ -/* Platform specific friendly IRQ names. */ -/*===========================================================================*/ - -/** - * @name IRQ VECTOR names - * @{ - */ -#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ -#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line - detect. */ -#define TAMPER_IRQHandler Vector48 /**< Tamper. */ -#define RTC_IRQHandler Vector4C /**< RTC. */ -#define FLASH_IRQHandler Vector50 /**< Flash. */ -#define RCC_IRQHandler Vector54 /**< RCC. */ -#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ -#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ -#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ -#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ -#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ -#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ -#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ -#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ -#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ -#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ -#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ -#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ -#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */ -#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ -#define USB_HP_IRQHandler Vector8C /**< USB High Priority, CAN1 TX.*/ -#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ -#define USB_LP_IRQHandler Vector90 /**< USB Low Priority, CAN1 RX0.*/ -#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ -#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ -#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ -#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ -#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ -#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and - Commutation. */ -#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ -#define TIM2_IRQHandler VectorB0 /**< TIM2. */ -#define TIM3_IRQHandler VectorB4 /**< TIM3. */ -#define TIM4_IRQHandler VectorB8 /**< TIM4. */ -#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ -#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ -#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ -#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */ -#define SPI1_IRQHandler VectorCC /**< SPI1. */ -#define SPI2_IRQHandler VectorD0 /**< SPI2. */ -#define USART1_IRQHandler VectorD4 /**< USART1. */ -#define USART2_IRQHandler VectorD8 /**< USART2. */ -#define USART3_IRQHandler VectorDC /**< USART3. */ -#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */ -#define USB_FS_WKUP_IRQHandler VectorE8 /**< USB Wakeup from suspend. */ -#define TIM8_BRK_IRQHandler VectorEC /**< TIM8 Break. */ -#define TIM8_UP_IRQHandler VectorF0 /**< TIM8 Update. */ -#define TIM8_TRG_COM_IRQHandler VectorF4 /**< TIM8 Trigger and - Commutation. */ -#define TIM8_CC_IRQHandler VectorF8 /**< TIM8 Capture Compare. */ -#define ADC3_IRQHandler VectorFC /**< ADC3. */ -#define FSMC_IRQHandler Vector100 /**< FSMC. */ -#define SDIO_IRQHandler Vector104 /**< SDIO. */ -#define TIM5_IRQHandler Vector108 /**< TIM5. */ -#define SPI3_IRQHandler Vector10C /**< SPI3. */ -#define UART4_IRQHandler Vector110 /**< UART4. */ -#define UART5_IRQHandler Vector114 /**< UART5. */ -#define TIM6_IRQHandler Vector118 /**< TIM6. */ -#define TIM7_IRQHandler Vector11C /**< TIM7. */ -#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ -#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ -#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ -#define DMA2_Ch4_5_IRQHandler Vector12C /**< DMA2 Channel4 & Channel5. */ -/** @} */ - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32F1xx/hal_lld_f105_f107.h b/os/hal/ports/STM32F1xx/hal_lld_f105_f107.h index 115ae8173..0bed30a05 100644 --- a/os/hal/ports/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/ports/STM32F1xx/hal_lld_f105_f107.h @@ -36,13 +36,6 @@ /* Driver constants. */ /*===========================================================================*/ -/** - * @name Platform identification - * @{ - */ -#define PLATFORM_NAME "STM32F10x Connectivity Line" -/** @} */ - /** * @name Absolute Maximum Ratings * @{ @@ -206,231 +199,6 @@ #define STM32_PREDIV1SRC_PLL2 (1 << 16) /**< PREDIV1 source is PLL2. */ /** @} */ -/*===========================================================================*/ -/* Platform capabilities. */ -/*===========================================================================*/ - -/** - * @name STM32F105/F107 CL capabilities - * @{ - */ -/* ADC attributes.*/ -#define STM32_HAS_ADC1 TRUE -#define STM32_HAS_ADC2 TRUE -#define STM32_HAS_ADC3 FALSE -#define STM32_HAS_ADC4 FALSE - -/* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE -#define STM32_HAS_CAN2 TRUE -#define STM32_CAN_MAX_FILTERS 28 - -/* DAC attributes.*/ -#define STM32_HAS_DAC TRUE - -/* DMA attributes.*/ -#define STM32_ADVANCED_DMA FALSE -#define STM32_HAS_DMA1 TRUE -#define STM32_HAS_DMA2 TRUE - -/* ETH attributes.*/ -#define STM32_HAS_ETH TRUE - -/* EXTI attributes.*/ -#define STM32_EXTI_NUM_CHANNELS 20 - -/* GPIO attributes.*/ -#define STM32_HAS_GPIOA TRUE -#define STM32_HAS_GPIOB TRUE -#define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE -#define STM32_HAS_GPIOF FALSE -#define STM32_HAS_GPIOG FALSE -#define STM32_HAS_GPIOH FALSE -#define STM32_HAS_GPIOI FALSE - -/* I2C attributes.*/ -#define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_I2C3 FALSE -#define STM32_I2C3_RX_DMA_MSK 0 -#define STM32_I2C3_RX_DMA_CHN 0x00000000 -#define STM32_I2C3_TX_DMA_MSK 0 -#define STM32_I2C3_TX_DMA_CHN 0x00000000 - -/* SDIO attributes.*/ -#define STM32_HAS_SDIO FALSE - -/* SPI attributes.*/ -#define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 -#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_SPI3 TRUE -#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1) -#define STM32_SPI3_RX_DMA_CHN 0x00000000 -#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2) -#define STM32_SPI3_TX_DMA_CHN 0x00000000 - -/* TIM attributes.*/ -#define STM32_HAS_TIM1 TRUE -#define STM32_HAS_TIM2 TRUE -#define STM32_HAS_TIM3 TRUE -#define STM32_HAS_TIM4 TRUE -#define STM32_HAS_TIM5 TRUE -#define STM32_HAS_TIM6 TRUE -#define STM32_HAS_TIM7 TRUE -#define STM32_HAS_TIM8 FALSE -#define STM32_HAS_TIM9 FALSE -#define STM32_HAS_TIM10 FALSE -#define STM32_HAS_TIM11 FALSE -#define STM32_HAS_TIM12 FALSE -#define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM14 FALSE -#define STM32_HAS_TIM15 FALSE -#define STM32_HAS_TIM16 FALSE -#define STM32_HAS_TIM17 FALSE -#define STM32_HAS_TIM18 FALSE -#define STM32_HAS_TIM19 FALSE - -/* USART attributes.*/ -#define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 -#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3)) -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5)) -#define STM32_UART4_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART5 TRUE -#define STM32_UART5_RX_DMA_MSK 0 -#define STM32_UART5_RX_DMA_CHN 0x00000000 -#define STM32_UART5_TX_DMA_MSK 0 -#define STM32_UART5_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART6 FALSE -#define STM32_USART6_RX_DMA_MSK 0 -#define STM32_USART6_RX_DMA_CHN 0x00000000 -#define STM32_USART6_TX_DMA_MSK 0 -#define STM32_USART6_TX_DMA_CHN 0x00000000 - -/* USB attributes.*/ -#define STM32_HAS_USB FALSE -#define STM32_HAS_OTG1 TRUE -#define STM32_HAS_OTG2 FALSE -/** @} */ - -/*===========================================================================*/ -/* Platform specific friendly IRQ names. */ -/*===========================================================================*/ - -/** - * @name IRQ VECTOR names - * @{ - */ -#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */ -#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line - detect. */ -#define TAMPER_IRQHandler Vector48 /**< Tamper. */ -#define RTC_IRQHandler Vector4C /**< RTC. */ -#define FLASH_IRQHandler Vector50 /**< Flash. */ -#define RCC_IRQHandler Vector54 /**< RCC. */ -#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */ -#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */ -#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */ -#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */ -#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */ -#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */ -#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */ -#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */ -#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */ -#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */ -#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */ -#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */ -#define ADC1_2_IRQHandler Vector88 /**< ADC1 and ADC2. */ -#define CAN1_TX_IRQHandler Vector8C /**< CAN1 TX. */ -#define CAN1_RX0_IRQHandler Vector90 /**< CAN1 RX0. */ -#define CAN1_RX1_IRQHandler Vector94 /**< CAN1 RX1. */ -#define CAN1_SCE_IRQHandler Vector98 /**< CAN1 SCE. */ -#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */ -#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */ -#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */ -#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and - Commutation. */ -#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */ -#define TIM2_IRQHandler VectorB0 /**< TIM2. */ -#define TIM3_IRQHandler VectorB4 /**< TIM3. */ -#define TIM4_IRQHandler VectorB8 /**< TIM4. */ -#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */ -#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */ -#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */ -#define I2C2_ER_IRQHandler VectorC8 /**< I2C1 Error. */ -#define SPI1_IRQHandler VectorCC /**< SPI1. */ -#define SPI2_IRQHandler VectorD0 /**< SPI2. */ -#define USART1_IRQHandler VectorD4 /**< USART1. */ -#define USART2_IRQHandler VectorD8 /**< USART2. */ -#define USART3_IRQHandler VectorDC /**< USART3. */ -#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */ -#define RTC_Alarm_IRQHandler VectorE4 /**< RTC alarm through EXTI - line. */ -#define OTG_FS_WKUP_IRQHandler VectorE8 /**< USB OTG FS Wakeup through - EXTI line. */ -#define TIM5_IRQHandler Vector108 /**< TIM5. */ -#define SPI3_IRQHandler Vector10C /**< SPI3. */ -#define UART4_IRQHandler Vector110 /**< UART4. */ -#define UART5_IRQHandler Vector114 /**< UART5. */ -#define TIM6_IRQHandler Vector118 /**< TIM6. */ -#define TIM7_IRQHandler Vector11C /**< TIM7. */ -#define DMA2_Ch1_IRQHandler Vector120 /**< DMA2 Channel1. */ -#define DMA2_Ch2_IRQHandler Vector124 /**< DMA2 Channel2. */ -#define DMA2_Ch3_IRQHandler Vector128 /**< DMA2 Channel3. */ -#define DMA2_Ch4_IRQHandler Vector12C /**< DMA2 Channel4. */ -#define DMA2_Ch5_IRQHandler Vector130 /**< DMA2 Channel5. */ -#define ETH_IRQHandler Vector134 /**< Ethernet. */ -#define ETH_WKUP_IRQHandler Vector138 /**< Ethernet Wakeup through - EXTI line. */ -#define CAN2_TX_IRQHandler Vector13C /**< CAN2 TX. */ -#define CAN2_RX0_IRQHandler Vector140 /**< CAN2 RX0. */ -#define CAN2_RX1_IRQHandler Vector144 /**< CAN2 RX1. */ -#define CAN2_SCE_IRQHandler Vector148 /**< CAN2 SCE. */ -#define OTG_FS_IRQHandler Vector14C /**< USB OTG FS. */ -/** @} */ - /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32F1xx/platform.mk b/os/hal/ports/STM32F1xx/platform.mk index 3940dedbe..7b3efd83f 100644 --- a/os/hal/ports/STM32F1xx/platform.mk +++ b/os/hal/ports/STM32F1xx/platform.mk @@ -1,31 +1,34 @@ # List of all the STM32F1xx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \ - ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \ - ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c +PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS}/os/hal/ports/STM32F1xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/ports/STM32F1xx/hal_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32F1xx/adc_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32F1xx/ext_lld_isr.c \ + ${CHIBIOS}/os/hal/ports/STM32/can_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/mac_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/sdc_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/GPIOv1/pal_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/I2Cv1/i2c_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/RTCv1/rtc_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/SPIv1/spi_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/TIMv1/gpt_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/TIMv1/icu_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/TIMv1/pwm_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/TIMv1/st_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/USARTv1/serial_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/USARTv1/uart_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/USBv1/usb_lld.c # Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \ - ${CHIBIOS}/os/hal/platforms/STM32 \ - ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/USBv1 +PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ + ${CHIBIOS}/os/hal/ports/STM32F1xx \ + ${CHIBIOS}/os/hal/ports/STM32 \ + ${CHIBIOS}/os/hal/ports/STM32/GPIOv1 \ + ${CHIBIOS}/os/hal/ports/STM32/I2Cv1 \ + ${CHIBIOS}/os/hal/ports/STM32/RTCv1 \ + ${CHIBIOS}/os/hal/ports/STM32/SPIv1 \ + ${CHIBIOS}/os/hal/ports/STM32/TIMv1 \ + ${CHIBIOS}/os/hal/ports/STM32/USARTv1 \ + ${CHIBIOS}/os/hal/ports/STM32/USBv1 diff --git a/os/hal/ports/STM32F1xx/platform_f105_f107.mk b/os/hal/ports/STM32F1xx/platform_f105_f107.mk index 88595f8ad..c0264dd3a 100644 --- a/os/hal/ports/STM32F1xx/platform_f105_f107.mk +++ b/os/hal/ports/STM32F1xx/platform_f105_f107.mk @@ -1,30 +1,32 @@ # List of all the STM32F1xx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \ - ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \ - ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/SPIv1/spi_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/gpt_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/icu_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1/pwm_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \ - ${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c +PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ + ${CHIBIOS}/os/hal/ports/STM32F1xx/stm32_dma.c \ + ${CHIBIOS}/os/hal/ports/STM32F1xx/hal_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32F1xx/adc_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32F1xx/ext_lld_isr.c \ + ${CHIBIOS}/os/hal/ports/STM32/can_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/ext_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/mac_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/sdc_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/GPIOv1/pal_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/I2Cv1/i2c_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/RTCv1/rtc_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/SPIv1/spi_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/TIMv1/gpt_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/TIMv1/icu_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/TIMv1/pwm_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/USARTv1/serial_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/USARTv1/uart_lld.c \ + ${CHIBIOS}/os/hal/ports/STM32/OTGv1/usb_lld.c # Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \ - ${CHIBIOS}/os/hal/platforms/STM32 \ - ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/SPIv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/TIMv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \ - ${CHIBIOS}/os/hal/platforms/STM32/OTGv1 +PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ + ${CHIBIOS}/os/hal/ports/STM32F1xx \ + ${CHIBIOS}/os/hal/ports/STM32 \ + ${CHIBIOS}/os/hal/ports/STM32/GPIOv1 \ + ${CHIBIOS}/os/hal/ports/STM32/I2Cv1 \ + ${CHIBIOS}/os/hal/ports/STM32/RTCv1 \ + ${CHIBIOS}/os/hal/ports/STM32/SPIv1 \ + ${CHIBIOS}/os/hal/ports/STM32/TIMv1 \ + ${CHIBIOS}/os/hal/ports/STM32/USARTv1 \ + ${CHIBIOS}/os/hal/ports/STM32/OTGv1 diff --git a/os/hal/ports/STM32F1xx/stm32_dma.c b/os/hal/ports/STM32F1xx/stm32_dma.c index 5f94f3392..f27e6ed2b 100644 --- a/os/hal/ports/STM32F1xx/stm32_dma.c +++ b/os/hal/ports/STM32F1xx/stm32_dma.c @@ -29,7 +29,6 @@ * @{ */ -#include "ch.h" #include "hal.h" /* The following macro is only defined if some driver requiring DMA services @@ -123,17 +122,17 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; * * @isr */ -CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { +OSAL_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 0; if (dma_isr_redir[0].dma_func) dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -141,17 +140,17 @@ CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { +OSAL_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 4; if (dma_isr_redir[1].dma_func) dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -159,17 +158,17 @@ CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { +OSAL_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 8; if (dma_isr_redir[2].dma_func) dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -177,17 +176,17 @@ CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { +OSAL_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 12; if (dma_isr_redir[3].dma_func) dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -195,17 +194,17 @@ CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { +OSAL_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 16; if (dma_isr_redir[4].dma_func) dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -213,17 +212,17 @@ CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { +OSAL_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 20; if (dma_isr_redir[5].dma_func) dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -231,17 +230,17 @@ CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { +OSAL_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 24; if (dma_isr_redir[6].dma_func) dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #if STM32_HAS_DMA2 || defined(__DOXYGEN__) @@ -250,17 +249,17 @@ CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) { +OSAL_IRQ_HANDLER(DMA2_Ch1_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 0; if (dma_isr_redir[7].dma_func) dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -268,17 +267,17 @@ CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) { +OSAL_IRQ_HANDLER(DMA2_Ch2_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 4; if (dma_isr_redir[8].dma_func) dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -286,17 +285,17 @@ CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) { +OSAL_IRQ_HANDLER(DMA2_Ch3_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 8; if (dma_isr_redir[9].dma_func) dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #if defined(STM32F10X_CL) || defined(__DOXYGEN__) @@ -305,17 +304,17 @@ CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) { +OSAL_IRQ_HANDLER(DMA2_Ch4_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 12; if (dma_isr_redir[10].dma_func) dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -323,17 +322,17 @@ CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) { +OSAL_IRQ_HANDLER(DMA2_Ch5_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 16; if (dma_isr_redir[11].dma_func) dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #else /* !STM32F10X_CL */ /** @@ -343,10 +342,10 @@ CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) { * * @isr */ -CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) { +OSAL_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); /* Check on channel 4.*/ flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; @@ -364,7 +363,7 @@ CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) { dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); } - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* !STM32F10X_CL */ #endif /* STM32_HAS_DMA2 */ @@ -416,12 +415,12 @@ void dmaInit(void) { * * @special */ -bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param) { +bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param) { - chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); + osalDbgCheck(dmastp != NULL); /* Checks if the stream is already taken.*/ if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) @@ -466,11 +465,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, */ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - chDbgCheck(dmastp != NULL, "dmaStreamRelease"); + osalDbgCheck(dmastp != NULL); /* Check if the streams is not taken.*/ - chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, - "dmaStreamRelease(), #1", "not allocated"); + osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "not allocated"); /* Disables the associated IRQ vector.*/ nvicDisableVector(dmastp->vector); diff --git a/os/hal/ports/STM32F1xx/stm32_dma.h b/os/hal/ports/STM32F1xx/stm32_dma.h index 70737fe7c..00f6e344a 100644 --- a/os/hal/ports/STM32F1xx/stm32_dma.h +++ b/os/hal/ports/STM32F1xx/stm32_dma.h @@ -392,10 +392,10 @@ extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS]; extern "C" { #endif void dmaInit(void); - bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, - uint32_t priority, - stm32_dmaisr_t func, - void *param); + bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp, + uint32_t priority, + stm32_dmaisr_t func, + void *param); void dmaStreamRelease(const stm32_dma_stream_t *dmastp); #ifdef __cplusplus } -- cgit v1.2.3