From f24c09b778d1103a345cb94b2d57c3e76fb5a681 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 25 Nov 2018 15:12:23 +0000 Subject: RTC changes for F3. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12440 110e8d01-0319-4d1e-a829-52ad28d1bb01 --- os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c | 29 +++- os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.h | 2 +- os/hal/ports/STM32/STM32F3xx/hal_lld.h | 1 + os/hal/ports/STM32/STM32F3xx/platform.mk | 1 + os/hal/ports/STM32/STM32F3xx/stm32_registry.h | 228 ++++++++++++++++++++++--- os/hal/ports/STM32/STM32L4xx+/stm32_registry.h | 2 +- os/hal/ports/STM32/STM32L4xx/stm32_registry.h | 2 +- 7 files changed, 229 insertions(+), 36 deletions(-) (limited to 'os/hal/ports/STM32') diff --git a/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c b/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c index 2dfc4f62c..66bde797a 100644 --- a/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c +++ b/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.c @@ -384,7 +384,7 @@ OSAL_IRQ_HANDLER(STM32_RTC_TAMP_STAMP_HANDLER) { extiClearGroup1(EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI)); if (RTCD1.callback != NULL) { - uint32_t cr, tampcr; + uint32_t cr, tcr; cr = RTCD1.rtc->CR; if ((cr & RTC_CR_TSIE) != 0U) { @@ -396,25 +396,44 @@ OSAL_IRQ_HANDLER(STM32_RTC_TAMP_STAMP_HANDLER) { } } - tampcr = RTCD1.rtc->TAMPCR; + /* This part is different depending on if the RTC has a TAMPCR or TAFCR + register.*/ +#if defined(RTC_TAFCR_TAMP1E) + tcr = RTCD1.rtc->TAFCR; + if ((tcr & RTC_TAFCR_TAMPIE) != 0U) { +#if defined(RTC_ISR_TAMP1F) + if ((isr & RTC_ISR_TAMP1F) != 0U) { + RTCD1.callback(&RTCD1, RTC_EVENT_TAMP1); + } +#endif +#if defined(RTC_ISR_TAMP2F) + if ((isr & RTC_ISR_TAMP2F) != 0U) { + RTCD1.callback(&RTCD1, RTC_EVENT_TAMP2); + } +#endif + } + +#else /* !defined(RTC_TAFCR_TAMP1E) */ + tcr = RTCD1.rtc->TAMPCR; #if defined(RTC_ISR_TAMP1F) - if (((tampcr & RTC_TAMPCR_TAMP1IE) != 0U) && + if (((tcr & RTC_TAMPCR_TAMP1IE) != 0U) && ((isr & RTC_ISR_TAMP1F) != 0U)) { RTCD1.callback(&RTCD1, RTC_EVENT_TAMP1); } #endif #if defined(RTC_ISR_TAMP2F) - if (((tampcr & RTC_TAMPCR_TAMP2IE) != 0U) && + if (((tcr & RTC_TAMPCR_TAMP2IE) != 0U) && ((isr & RTC_ISR_TAMP2F) != 0U)) { RTCD1.callback(&RTCD1, RTC_EVENT_TAMP2); } #endif #if defined(RTC_ISR_TAMP3F) - if (((tampcr & RTC_TAMPCR_TAMP3IE) != 0U) && + if (((tcr & RTC_TAMPCR_TAMP3IE) != 0U) && ((isr & RTC_ISR_TAMP3F) != 0U)) { RTCD1.callback(&RTCD1, RTC_EVENT_TAMP3); } #endif +#endif /* !defined(RTC_TAFCR_TAMP1E) */ } OSAL_IRQ_EPILOGUE(); diff --git a/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.h b/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.h index e538a6480..cab56c94b 100644 --- a/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.h +++ b/os/hal/ports/STM32/LLD/RTCv2/hal_rtc_lld.h @@ -120,7 +120,7 @@ * @brief RTC TAMPCR register initialization value. * @note Use this value to initialize features not directly handled by * the RTC driver. - * @note On F0 devices this values goes in the similar TAFCR register. + * @note On some devices this values goes in the similar TAFCR register. */ #if !defined(STM32_RTC_TAMPCR_INIT) || defined(__DOXYGEN__) #define STM32_RTC_TAMPCR_INIT 0 diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.h b/os/hal/ports/STM32/STM32F3xx/hal_lld.h index e98905172..a3b1f3d11 100644 --- a/os/hal/ports/STM32/STM32F3xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.h @@ -1180,6 +1180,7 @@ #include "mpu_v7m.h" #include "stm32_isr.h" #include "stm32_dma.h" +#include "stm32_exti.h" #include "stm32_rcc.h" #ifdef __cplusplus diff --git a/os/hal/ports/STM32/STM32F3xx/platform.mk b/os/hal/ports/STM32/STM32F3xx/platform.mk index 53aa814ca..ae7b3ff19 100644 --- a/os/hal/ports/STM32/STM32F3xx/platform.mk +++ b/os/hal/ports/STM32/STM32F3xx/platform.mk @@ -25,6 +25,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h index c1b793e85..ecaa8cf09 100644 --- a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h @@ -32,10 +32,6 @@ #define STM32F3XX #endif -/*===========================================================================*/ -/* Common features. */ -/*===========================================================================*/ - /*===========================================================================*/ /* Platform capabilities. */ /*===========================================================================*/ @@ -44,6 +40,14 @@ * @name STM32F3xx capabilities * @{ */ + +/*===========================================================================*/ +/* Common. */ +/*===========================================================================*/ + +/* RNG attributes.*/ +#define STM32_HAS_RNG1 TRUE + /*===========================================================================*/ /* STM32F303xC. */ /*===========================================================================*/ @@ -133,7 +137,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 34 -#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* GPIO attributes.*/ @@ -174,7 +178,21 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 1 -#define STM32_RTC_HAS_INTERRUPTS FALSE +#define STM32_RTC_STORAGE_SIZE 64 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE @@ -396,7 +414,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 34 -#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* GPIO attributes.*/ @@ -443,7 +461,21 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE +#define STM32_RTC_STORAGE_SIZE 64 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE @@ -653,7 +685,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 33 -#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* GPIO attributes.*/ @@ -691,7 +723,21 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE +#define STM32_RTC_STORAGE_SIZE 64 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE @@ -865,7 +911,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 33 -#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* GPIO attributes.*/ @@ -909,7 +955,21 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE +#define STM32_RTC_STORAGE_SIZE 64 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE @@ -1080,7 +1140,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 33 -#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* GPIO attributes.*/ @@ -1124,7 +1184,21 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE +#define STM32_RTC_STORAGE_SIZE 64 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE @@ -1314,7 +1388,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 34 -#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* GPIO attributes.*/ @@ -1356,7 +1430,21 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE +#define STM32_RTC_STORAGE_SIZE 64 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE @@ -1560,7 +1648,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 34 -#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* GPIO attributes.*/ @@ -1607,7 +1695,21 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE +#define STM32_RTC_STORAGE_SIZE 64 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE @@ -1799,7 +1901,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 33 -#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* GPIO attributes.*/ @@ -1842,7 +1944,21 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE +#define STM32_RTC_STORAGE_SIZE 64 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE @@ -2023,7 +2139,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 33 -#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* GPIO attributes.*/ @@ -2061,7 +2177,21 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE +#define STM32_RTC_STORAGE_SIZE 64 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE @@ -2250,7 +2380,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 34 -#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* GPIO attributes.*/ @@ -2292,7 +2422,21 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 1 -#define STM32_RTC_HAS_INTERRUPTS FALSE +#define STM32_RTC_STORAGE_SIZE 64 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE @@ -2490,7 +2634,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 33 -#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* GPIO attributes.*/ @@ -2528,7 +2672,21 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 1 -#define STM32_RTC_HAS_INTERRUPTS FALSE +#define STM32_RTC_STORAGE_SIZE 64 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE @@ -2730,7 +2888,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 34 -#define STM32_EXTI_IMR_MASK 0x1F800000U +#define STM32_EXTI_IMR1_MASK 0x1F800000U #define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU /* GPIO attributes.*/ @@ -2777,7 +2935,21 @@ #define STM32_RTC_HAS_SUBSECONDS TRUE #define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE #define STM32_RTC_NUM_ALARMS 2 -#define STM32_RTC_HAS_INTERRUPTS FALSE +#define STM32_RTC_STORAGE_SIZE 64 +#define STM32_RTC_TAMP_STAMP_HANDLER Vector48 +#define STM32_RTC_WKUP_HANDLER Vector4C +#define STM32_RTC_ALARM_HANDLER VectorE4 +#define STM32_RTC_TAMP_STAMP_NUMBER 2 +#define STM32_RTC_WKUP_NUMBER 3 +#define STM32_RTC_ALARM_NUMBER 41 +#define STM32_RTC_ALARM_EXTI 17 +#define STM32_RTC_TAMP_STAMP_EXTI 19 +#define STM32_RTC_WKUP_EXTI 20 +#define STM32_RTC_IRQ_ENABLE() do { \ + nvicEnableVector(STM32_RTC_TAMP_STAMP_NUMBER, STM32_IRQ_EXTI19_PRIORITY); \ + nvicEnableVector(STM32_RTC_WKUP_NUMBER, STM32_IRQ_EXTI20_PRIORITY); \ + nvicEnableVector(STM32_RTC_ALARM_NUMBER, STM32_IRQ_EXTI17_PRIORITY); \ +} while (false) /* SDIO attributes.*/ #define STM32_HAS_SDIO FALSE diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h index 735af3781..f6d316137 100644 --- a/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h @@ -48,7 +48,7 @@ #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_STORAGE_SIZE 128 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 -#define STM32_RTC_WKUP_HANDLER Vector49 +#define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h index 9c22b96f2..a2e911592 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h @@ -48,7 +48,7 @@ #define STM32_RTC_NUM_ALARMS 2 #define STM32_RTC_STORAGE_SIZE 128 #define STM32_RTC_TAMP_STAMP_HANDLER Vector48 -#define STM32_RTC_WKUP_HANDLER Vector49 +#define STM32_RTC_WKUP_HANDLER Vector4C #define STM32_RTC_ALARM_HANDLER VectorE4 #define STM32_RTC_TAMP_STAMP_NUMBER 2 #define STM32_RTC_WKUP_NUMBER 3 -- cgit v1.2.3