From cc826010ae690e91d8bd36ca3abccd8dc27a139f Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 28 Jul 2018 09:11:04 +0000
Subject: More L4+ preparation.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12203 110e8d01-0319-4d1e-a829-52ad28d1bb01
---
 os/hal/ports/STM32/STM32L4xx+/hal_lld.c |  3 ++
 os/hal/ports/STM32/STM32L4xx+/hal_lld.h | 54 ++++++++++++---------------------
 2 files changed, 23 insertions(+), 34 deletions(-)

(limited to 'os/hal/ports/STM32')

diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
index fa843f86d..439fb80ad 100644
--- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.c
@@ -92,6 +92,9 @@ static void hal_lld_backup_domain_init(void) {
     RCC->BDCR |= RCC_BDCR_RTCEN;
   }
 #endif /* HAL_USE_RTC */
+
+  /* Low speed output mode.*/
+  RCC->BDCR |= STM32_LSCOSEL;
 }
 
 /*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32L4xx+/hal_lld.h b/os/hal/ports/STM32/STM32L4xx+/hal_lld.h
index 5cd2f50cd..d274d58f2 100644
--- a/os/hal/ports/STM32/STM32L4xx+/hal_lld.h
+++ b/os/hal/ports/STM32/STM32L4xx+/hal_lld.h
@@ -535,7 +535,7 @@
  * @note    The allowed values are 2, 4, 6, 8.
  */
 #if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLQ_VALUE                    6
+#define STM32_PLLQ_VALUE                    4
 #endif
 
 /**
@@ -604,7 +604,7 @@
  * @note    The allowed values are 8..127.
  */
 #if !defined(STM32_PLLSAI1N_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAI1N_VALUE                80
+#define STM32_PLLSAI1N_VALUE                72
 #endif
 
 /**
@@ -612,7 +612,7 @@
  * @note    The allowed values are 0, 2..31.
  */
 #if !defined(STM32_PLLSAI1PDIV_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAI1PDIV_VALUE             0
+#define STM32_PLLSAI1PDIV_VALUE             6
 #endif
 
 /**
@@ -636,7 +636,7 @@
  * @note    The allowed values are 2, 4, 6, 8.
  */
 #if !defined(STM32_PLLSAI1R_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAI1R_VALUE                4
+#define STM32_PLLSAI1R_VALUE                6
 #endif
 
 /**
@@ -644,7 +644,7 @@
  * @note    The allowed values are 8..127.
  */
 #if !defined(STM32_PLLSAI2N_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAI2N_VALUE                80
+#define STM32_PLLSAI2N_VALUE                72
 #endif
 
 /**
@@ -652,7 +652,7 @@
  * @note    The allowed values are 0, 2..31.
  */
 #if !defined(STM32_PLLSAI2PDIV_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAI2PDIV_VALUE             0
+#define STM32_PLLSAI2PDIV_VALUE             6
 #endif
 
 /**
@@ -663,12 +663,20 @@
 #define STM32_PLLSAI2P_VALUE                7
 #endif
 
+/**
+ * @brief   PLLSAI2Q divider value.
+ * @note    The allowed values are 2, 4, 6, 8.
+ */
+#if !defined(STM32_PLLSAI2Q_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2Q_VALUE                6
+#endif
+
 /**
  * @brief   PLLSAI2R divider value.
  * @note    The allowed values are 2, 4, 6, 8.
  */
 #if !defined(STM32_PLLSAI2R_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLSAI2R_VALUE                4
+#define STM32_PLLSAI2R_VALUE                6
 #endif
 
 /**
@@ -1855,12 +1863,10 @@
 
 /**
  * @brief   STM32_PLLSAI2REN field.
+ * @note    Always enabled.
+ * @todo    It should depend on some condition.
  */
-#if (STM32_ADCSEL == STM32_ADCSEL_PLLSAI2) || defined(__DOXYGEN__)
 #define STM32_PLLSAI2REN            (1 << 24)
-#else
-#define STM32_PLLSAI2REN            (0 << 24)
-#endif
 
 /**
  * @brief   PLLSAI2 VCO frequency.
@@ -2142,22 +2148,6 @@
 /**
  * @brief   48MHz clock frequency.
  */
-#if !STM32_CLOCK_HAS_HSI48 || defined(__DOXYGEN__)
-
-#if (STM32_CLK48SEL == STM32_CLK48SEL_NOCLK) || defined(__DOXYGEN__)
-#define STM32_48CLK                 0
-#elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
-#define STM32_48CLK                 (STM32_PLLSAI1VCO / STM32_PLLSAI1Q_VALUE)
-#elif STM32_CLK48SEL == STM32_CLK48SEL_PLL
-#define STM32_48CLK                 (STM32_PLLVCO / STM32_PLLQ_VALUE)
-#elif STM32_CLK48SEL == STM32_CLK48SEL_MSI
-#define STM32_48CLK                 STM32_MSICLK
-#else
-#error "invalid source selected for 48CLK clock"
-#endif
-
-#else /* STM32_CLOCK_HAS_HSI48 */
-
 #if (STM32_CLK48SEL == STM32_CLK48SEL_HSI48) || defined(__DOXYGEN__)
 #define STM32_48CLK                 STM32_HSI48CLK
 #elif STM32_CLK48SEL == STM32_CLK48SEL_PLLSAI1
@@ -2170,8 +2160,6 @@
 #error "invalid source selected for 48CLK clock"
 #endif
 
-#endif /* STM32_CLOCK_HAS_HSI48 */
-
 /**
  * @brief   USB clock point.
  */
@@ -2184,8 +2172,6 @@
 #define STM32_ADCCLK                0
 #elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI1
 #define STM32_ADCCLK                STM32_PLLSAI1_R_CLKOUT
-#elif STM32_ADCSEL == STM32_ADCSEL_PLLSAI2
-#define STM32_ADCCLK                STM32_PLLSAI2_R_CLKOUT
 #elif STM32_ADCSEL == STM32_ADCSEL_SYSCLK
 #define STM32_ADCCLK                STM32_SYSCLK
 #else
@@ -2195,8 +2181,8 @@
 /**
  * @brief   DFSDM clock frequency.
  */
-#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK1) || defined(__DOXYGEN__)
-#define STM32_DFSDMCLK              STM32_PCLK1
+#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK2) || defined(__DOXYGEN__)
+#define STM32_DFSDMCLK              STM32_PCLK2
 #elif STM32_DFSDMSEL == STM32_DFSDMSEL_SYSCLK
 #define STM32_DFSDMCLK              STM32_SYSCLK
 #else
@@ -2290,7 +2276,7 @@
 #include "cache.h"
 #include "mpu_v7m.h"
 #include "stm32_isr.h"
-#include "stm32_dma.h"
+//#include "stm32_dma.h"
 #include "stm32_rcc.h"
 
 #ifdef __cplusplus
-- 
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