From 261a2e7e8bfd6f7234f9b4a63a7f029656263165 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 2 May 2015 12:28:09 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7936
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/ports/STM32/LLD/DACv1/dac_lld.c   | 35 ++++++++++++++++++--------------
 os/hal/ports/STM32/LLD/DACv1/dac_lld.h   | 16 ++++++++++++---
 os/hal/ports/STM32/STM32F4xx/stm32_rcc.h |  6 +++---
 3 files changed, 36 insertions(+), 21 deletions(-)

(limited to 'os/hal/ports/STM32')

diff --git a/os/hal/ports/STM32/LLD/DACv1/dac_lld.c b/os/hal/ports/STM32/LLD/DACv1/dac_lld.c
index 32573a781..8afa4e505 100644
--- a/os/hal/ports/STM32/LLD/DACv1/dac_lld.c
+++ b/os/hal/ports/STM32/LLD/DACv1/dac_lld.c
@@ -260,14 +260,18 @@ void dac_lld_start(DACDriver *dacp) {
       rccEnableDAC2(false);
     }
 #endif
-  }
 
-  /* DAC initially disabled.*/
+    /* Enabling DAC in SW triggering mode initially, initializing data to
+       zero.*/
 #if STM32_DAC_DUAL_MODE == FALSE
-  dacp->params->dac->CR = dacp->params->regmask;
+    dacp->params->dac->CR &= dacp->params->regmask;
+    dacp->params->dac->CR |= DAC_CR_EN1 << dacp->params->regshift;
+    *(&dacp->params->dac->DHR12R1 + dacp->params->dataoffset) = 0U;
 #else
-  dacp->params->dac->CR = 0U;
+    dacp->params->dac->CR = DAC_CR_EN2 | DAC_CR_EN1;
+    dacp->params->dac->DAC_DHR12RD = 0U;
 #endif
+  }
 }
 
 /**
@@ -285,10 +289,11 @@ void dac_lld_stop(DACDriver *dacp) {
     /* DMA channel released.*/
     dmaStreamRelease(dacp->params->dma);
 
+    /* Disabling DAC.*/
+    dacp->params->dac->CR &= dacp->params->regmask;
+
 #if STM32_DAC_USE_DAC1_CH1
     if (&DACD1 == dacp) {
-      dacp->params->dac->CR &= ~DAC_CR_EN1;
-
       if ((dacp->params->dac->CR & DAC_CR_EN2) == 0U) {
         rccDisableDAC1(false);
       }
@@ -297,8 +302,6 @@ void dac_lld_stop(DACDriver *dacp) {
 
 #if STM32_DAC_USE_DAC1_CH2
     if (&DACD2 == dacp) {
-      dacp->params->dac->CR &= ~DAC_CR_EN2;
-
       if ((dacp->params->dac->CR & DAC_CR_EN1) == 0U) {
         rccDisableDAC1(false);
       }
@@ -319,7 +322,7 @@ void dac_lld_start_conversion(DACDriver *dacp) {
   uint32_t cr, dmamode;
 
 #if STM32_DAC_DUAL_MODE == FALSE
-  switch (dacp->grpp->dhrm) {
+  switch (dacp->grpp->datamode) {
   /* Sets the DAC data register */
   case DAC_DHRM_12BIT_RIGHT:
     dmaStreamSetPeripheral(dacp->params->dma, &dacp->params->dac->DHR12R1 +
@@ -372,10 +375,9 @@ void dac_lld_start_conversion(DACDriver *dacp) {
 
   /* DAC configuration.*/
 #if STM32_DAC_DUAL_MODE == FALSE
-  cr = DAC_CR_DMAEN1 | (dacp->grpp->cr_tsel << 3) |
-       DAC_CR_TEN1 | DAC_CR_EN1;
-  dacp->params->dac->CR = (dacp->params->dac->CR & dacp->params->regmask) |
-                          (cr << dacp->params->regshift);
+  cr = DAC_CR_DMAEN1 | (dacp->grpp->trigger << 3) | DAC_CR_TEN1 | DAC_CR_EN1;
+  dacp->params->dac->CR &= dacp->params->regmask;
+  dacp->params->dac->CR |= cr << dacp->params->regshift;
 #else
   /* TODO: Dual.*/
 #endif
@@ -396,9 +398,12 @@ void dac_lld_stop_conversion(DACDriver *dacp) {
 
   dmaStreamDisable(dacp->params->dma);
 #if STM32_DAC_DUAL_MODE == FALSE
-  dacp->params->dac->CR = dacp->params->regmask;
+  dacp->params->dac->CR  = dacp->params->regmask;
+  dacp->params->dac->CR |= DAC_CR_EN1 << dacp->params->regshift;
+  *(&dacp->params->dac->DHR12R1 + dacp->params->dataoffset) = 0U;
 #else
-  dacp->params->dac->CR = 0U;
+  dacp->params->dac->CR = DAC_CR_EN2 | DAC_CR_EN1;
+  dacp->params->dac->DAC_DHR12RD = 0U;
 #endif
 }
 
diff --git a/os/hal/ports/STM32/LLD/DACv1/dac_lld.h b/os/hal/ports/STM32/LLD/DACv1/dac_lld.h
index fe0e21006..36842f295 100644
--- a/os/hal/ports/STM32/LLD/DACv1/dac_lld.h
+++ b/os/hal/ports/STM32/LLD/DACv1/dac_lld.h
@@ -33,6 +33,16 @@
 /* Driver constants.                                                         */
 /*===========================================================================*/
 
+/**
+ * @name    DAC trigger modes
+ * @{
+ */
+#define DAC_TRG_MASK                    7U
+#define DAC_TRG(n)                      (n)
+#define DAC_TRG_EXT                     6U
+#define DAC_TRG_SW                      7U
+/** @} */
+
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
@@ -293,7 +303,7 @@ typedef void (*daccallback_t)(DACDriver *dacp,
  *                      callback
  * @param[in] err       ADC error code
  */
-typedef void (*dacerrorcallback_t)(DACDriver *adcp, dacerror_t err);
+typedef void (*dacerrorcallback_t)(DACDriver *dacp, dacerror_t err);
 
 /**
  * @brief   Samples alignment and size mode.
@@ -329,14 +339,14 @@ typedef struct {
   /**
    * @brief   DAC data holding register mode.
    */
-  dacdhrmode_t              dhrm;
+  dacdhrmode_t              datamode;
   /**
    * @brief   DAC initialization data.
    * @note    This field contains the (not shifted) value to be put into the
    *          TSEL field of the DAC CR register during initialization. All
    *          other fields are handled internally.
    */
-  uint32_t                  cr_tsel;
+  uint32_t                  trigger;
 } DACConversionGroup;
 
 /**
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
index 083d08e02..33659dc2c 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
@@ -343,7 +343,7 @@
  *
  * @api
  */
-#define rccEnableDAC1(lp) rccEnableAPB2(RCC_APB1ENR_DACEN, lp)
+#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp)
 
 /**
  * @brief   Disables the DAC1 peripheral clock.
@@ -352,14 +352,14 @@
  *
  * @api
  */
-#define rccDisableDAC1(lp) rccDisableAPB2(RCC_APB1ENR_DACEN, lp)
+#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp)
 
 /**
  * @brief   Resets the DAC1 peripheral.
  *
  * @api
  */
-#define rccResetDAC1() rccResetAPB2(RCC_APB1RSTR_DACRST)
+#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST)
 /** @} */
 
 /**
-- 
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