From f7c23bcc06574b91f5ece441cd0449f7e553feca Mon Sep 17 00:00:00 2001
From: Rocco Marco Guglielmi <roccomarco.guglielmi@live.com>
Date: Sat, 25 Jun 2016 14:46:25 +0000
Subject: Fixed Bug #759 and #760.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9662 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/ports/STM32/STM32L4xx/hal_lld.c | 20 +++++++++++++++++---
 os/hal/ports/STM32/STM32L4xx/hal_lld.h |  7 +++++++
 2 files changed, 24 insertions(+), 3 deletions(-)

(limited to 'os/hal/ports/STM32/STM32L4xx')

diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
index ef1b7e481..730629c86 100644
--- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
@@ -114,7 +114,7 @@ void hal_lld_init(void) {
 }
 
 /**
- * @brief   STM32F2xx clocks and PLL initialization.
+ * @brief   STM32L4xx clocks and PLL initialization.
  * @note    All the involved constants come from the file @p board.h.
  * @note    This function should be invoked just after the system reset.
  *
@@ -124,12 +124,14 @@ void stm32_clock_init(void) {
 
 #if !STM32_NO_INIT
   /* PWR clock enable.*/
-  RCC->APB1ENR1 = RCC_APB1ENR1_PWREN;
+  RCC->APB1ENR1 |= RCC_APB1ENR1_PWREN;
 
   /* Initial clocks setup and wait for MSI stabilization, the MSI clock is
      always enabled because it is the fall back clock when PLL the fails.
      Trim fields are not altered from reset values.*/
-  RCC->CR = RCC_CR_MSION | STM32_MSIRANGE_4M;
+
+  /* MSIRANGE can be set only when MSI is OFF or READY.*/
+  RCC->CR = RCC_CR_MSION;
   while ((RCC->CR & RCC_CR_MSIRDY) == 0)
     ;                                       /* Wait until MSI is stable.    */
 
@@ -189,6 +191,18 @@ void stm32_clock_init(void) {
   RCC->CR |= RCC_CR_MSIPLLEN;
 #endif
 
+  /* Note that  MSI range is the MSISRANGE by default which is 4M.*/
+  RCC->CR |= STM32_MSIRANGE;
+
+  /* Switching from MSISRANGE to MSIRANGE.*/
+  RCC->CR |= RCC_CR_MSIRGSEL;
+  while ((RCC->CR & RCC_CR_MSIRDY) == 0)
+    ;
+
+  /* Updating MSISRANGE value. MSISRANGE can be set only when MSIRGSEL is high. 
+     This range is used exiting the Standby mode until MSIRGSEL is set.*/
+  RCC->CSR |= STM32_MSISRANGE;
+
 #if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 || STM32_ACTIVATE_PLLSAI2
   /* PLLM and PLLSRC are common to all PLLs.*/
   RCC->PLLCFGR = STM32_PLLR   | STM32_PLLREN |
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h
index 7bca2517b..e20c9fdfa 100644
--- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h
@@ -1108,6 +1108,13 @@
 
 #endif /* !STM32_LSE_ENABLED */
 
+/*
+ * MSI related checks.
+ */
+#if (STM32_MSIRANGE == STM32_MSIRANGE_48M) && !STM32_MSIPLL_ENABLED
+#warning "STM32_MSIRANGE_48M should be used with STM32_MSIPLL_ENABLED"
+#endif
+
 /**
  * @brief   STM32_PLLM field.
  */
-- 
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