From 52b961258008124cecb3f6f62f8c1aa7b608de12 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sat, 17 Mar 2018 09:14:35 +0000 Subject: Added HAL support for STM32L443. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11791 110e8d01-0319-4d1e-a829-52ad28d1bb01 --- os/hal/ports/STM32/STM32L4xx/hal_lld.h | 11 +- os/hal/ports/STM32/STM32L4xx/stm32_registry.h | 362 ++++++++++++++++++++++++++ 2 files changed, 368 insertions(+), 5 deletions(-) (limited to 'os/hal/ports/STM32/STM32L4xx') diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h index 3e6ac5da9..d054d5679 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h @@ -26,8 +26,9 @@ * - STM32_HSE_BYPASS (optionally). * . * One of the following macros must also be defined: - * - STM32L471xx, STM32L475xx, STM32L476xx. - * - STM32L485xx, STM32L486xx. + * - STM32L432xx, STM32L443xx. + * - STM32L471xx, STM32L475xx, STM32L476xx, STM32L496xx. + * - STM32L485xx, STM32L486xx, STM32L4A6xx. * . * * @addtogroup HAL @@ -47,9 +48,9 @@ * @name Platform identification * @{ */ -#if defined(STM32L432xx) || defined(STM32L471xx) || \ - defined(STM32L475xx) || defined(STM32L476xx) || \ - defined(STM32L496xx) || defined(__DOXYGEN__) +#if defined(STM32L432xx) || defined(STM32L443xx) || \ + defined(STM32L471xx) || defined(STM32L475xx) || \ + defined(STM32L476xx) || defined(STM32L496xx) || defined(__DOXYGEN__) #define PLATFORM_NAME "STM32L4xx Ultra Low Power" #elif defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx) diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h index 534dfe1e2..4df280389 100644 --- a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h @@ -28,6 +28,9 @@ #if defined(STM32L432xx) #define STM32L432xx +#elif defined(STM32L443xx) +#define STM32L443xx + #elif defined(STM32L476xx) #define STM32L476xx @@ -368,6 +371,365 @@ #endif /* defined(STM32L432xx) */ +/*===========================================================================*/ +/* STM32L443xx. */ +/*===========================================================================*/ + +#if defined(STM32L443xx) || defined(__DOXYGEN__) + +/* Clock attributes.*/ +#define STM32_CLOCK_HAS_HSI48 TRUE + +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_HANDLER Vector88 +#define STM32_ADC1_NUMBER 18 +#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_ADC1_DMA_CHN 0x00000000 + +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 TRUE +#define STM32_CAN_MAX_FILTERS 14 +#define STM32_CAN1_TX_HANDLER Vector8C +#define STM32_CAN1_RX0_HANDLER Vector90 +#define STM32_CAN1_RX1_HANDLER Vector94 +#define STM32_CAN1_SCE_HANDLER Vector98 +#define STM32_CAN1_TX_NUMBER 19 +#define STM32_CAN1_RX0_NUMBER 20 +#define STM32_CAN1_RX1_NUMBER 21 +#define STM32_CAN1_SCE_NUMBER 22 + +#define STM32_HAS_CAN2 FALSE +#define STM32_HAS_CAN3 FALSE + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_DAC1_CH1_DMA_CHN 0x00003600 + +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_DAC1_CH2_DMA_CHN 0x00035000 + +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_DAC1_CH1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)|\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_DAC1_CH1_DMA_CHN 0x00003600 + +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_DAC1_CH2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)|\ + STM32_DMA_STREAM_ID_MSK(2, 5)) +#define STM32_DAC1_CH2_DMA_CHN 0x00035000 + +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_SUPPORTS_CSELR TRUE +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector6C +#define STM32_DMA1_CH2_HANDLER Vector70 +#define STM32_DMA1_CH3_HANDLER Vector74 +#define STM32_DMA1_CH4_HANDLER Vector78 +#define STM32_DMA1_CH5_HANDLER Vector7C +#define STM32_DMA1_CH6_HANDLER Vector80 +#define STM32_DMA1_CH7_HANDLER Vector84 +#define STM32_DMA1_CH1_NUMBER 11 +#define STM32_DMA1_CH2_NUMBER 12 +#define STM32_DMA1_CH3_NUMBER 13 +#define STM32_DMA1_CH4_NUMBER 14 +#define STM32_DMA1_CH5_NUMBER 15 +#define STM32_DMA1_CH6_NUMBER 16 +#define STM32_DMA1_CH7_NUMBER 17 + +#define STM32_DMA2_NUM_CHANNELS 7 +#define STM32_DMA2_CH1_HANDLER Vector120 +#define STM32_DMA2_CH2_HANDLER Vector124 +#define STM32_DMA2_CH3_HANDLER Vector128 +#define STM32_DMA2_CH4_HANDLER Vector12C +#define STM32_DMA2_CH5_HANDLER Vector130 +#define STM32_DMA2_CH6_HANDLER Vector150 +#define STM32_DMA2_CH7_HANDLER Vector154 +#define STM32_DMA2_CH1_NUMBER 56 +#define STM32_DMA2_CH2_NUMBER 57 +#define STM32_DMA2_CH3_NUMBER 58 +#define STM32_DMA2_CH4_NUMBER 59 +#define STM32_DMA2_CH5_NUMBER 60 +#define STM32_DMA2_CH6_NUMBER 68 +#define STM32_DMA2_CH7_NUMBER 69 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 37 +#define STM32_EXTI_IMR_MASK 0xFF820000U +#define STM32_EXTI_IMR2_MASK 0x00000087U + +#define STM32_EXTI_LINE0_HANDLER Vector58 +#define STM32_EXTI_LINE1_HANDLER Vector5C +#define STM32_EXTI_LINE2_HANDLER Vector60 +#define STM32_EXTI_LINE3_HANDLER Vector64 +#define STM32_EXTI_LINE4_HANDLER Vector68 +#define STM32_EXTI_LINE5_9_HANDLER Vector9C +#define STM32_EXTI_LINE10_15_HANDLER VectorE0 +#define STM32_EXTI_LINE1635_38_HANDLER Vector44 +#define STM32_EXTI_LINE18_HANDLER VectorE4 +#define STM32_EXTI_LINE19_HANDLER Vector48 +#define STM32_EXTI_LINE20_HANDLER Vector4C +#define STM32_EXTI_LINE2122_HANDLER Vector140 + +#define STM32_EXTI_LINE0_NUMBER 6 +#define STM32_EXTI_LINE1_NUMBER 7 +#define STM32_EXTI_LINE2_NUMBER 8 +#define STM32_EXTI_LINE3_NUMBER 9 +#define STM32_EXTI_LINE4_NUMBER 10 +#define STM32_EXTI_LINE5_9_NUMBER 23 +#define STM32_EXTI_LINE10_15_NUMBER 40 +#define STM32_EXTI_LINE1635_38_NUMBER 1 +#define STM32_EXTI_LINE18_NUMBER 41 +#define STM32_EXTI_LINE19_NUMBER 2 +#define STM32_EXTI_LINE20_NUMBER 3 +#define STM32_EXTI_LINE2122_NUMBER 64 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD FALSE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF FALSE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \ + RCC_AHB2ENR_GPIOBEN | \ + RCC_AHB2ENR_GPIOCEN | \ + RCC_AHB2ENR_GPIOHEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_I2C1_EVENT_HANDLER VectorBC +#define STM32_I2C1_EVENT_NUMBER 31 +#define STM32_I2C1_ERROR_HANDLER VectorC0 +#define STM32_I2C1_ERROR_NUMBER 32 +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_I2C1_RX_DMA_CHN 0x03500000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_I2C1_TX_DMA_CHN 0x05300000 + +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_EVENT_HANDLER VectorC4 +#define STM32_I2C2_EVENT_NUMBER 33 +#define STM32_I2C2_ERROR_HANDLER VectorC8 +#define STM32_I2C2_ERROR_NUMBER 34 +#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_I2C2_RX_DMA_CHN 0x00030000 +#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_I2C2_TX_DMA_CHN 0x00003000 + +#define STM32_HAS_I2C3 TRUE +#define STM32_I2C3_EVENT_HANDLER Vector160 +#define STM32_I2C3_EVENT_NUMBER 72 +#define STM32_I2C3_ERROR_HANDLER Vector164 +#define STM32_I2C3_ERROR_NUMBER 73 +#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_I2C3_RX_DMA_CHN 0x00000300 +#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_I2C3_TX_DMA_CHN 0x00000030 + +#define STM32_HAS_I2C4 FALSE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 TRUE +#define STM32_QUADSPI1_HANDLER Vector15C +#define STM32_QUADSPI1_NUMBER 71 +#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_QUADSPI1_DMA_CHN 0x03050000 + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_HAS_INTERRUPTS FALSE + +/* SDMMC attributes.*/ +#define STM32_HAS_SDMMC1 TRUE +#define STM32_HAS_SDMMC2 FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(2, 3)) +#define STM32_SPI1_RX_DMA_CHN 0x00000410 +#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(2, 4)) +#define STM32_SPI1_TX_DMA_CHN 0x00004100 + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S FALSE +#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_SPI2_RX_DMA_CHN 0x00001000 +#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_SPI2_TX_DMA_CHN 0x00010000 + +#define STM32_HAS_SPI3 TRUE +#define STM32_SPI3_SUPPORTS_I2S FALSE +#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1)) +#define STM32_SPI3_RX_DMA_CHN 0x00000003 +#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2)) +#define STM32_SPI3_TX_DMA_CHN 0x00000030 + +#define STM32_HAS_SPI4 FALSE +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 6 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 4 +#define STM32_TIM1_UP_HANDLER VectorA4 +#define STM32_TIM1_CC_HANDLER VectorAC +#define STM32_TIM1_UP_NUMBER 25 +#define STM32_TIM1_CC_NUMBER 27 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 +#define STM32_TIM2_HANDLER VectorB0 +#define STM32_TIM2_NUMBER 28 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 +#define STM32_TIM6_HANDLER Vector118 +#define STM32_TIM6_NUMBER 54 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 +#define STM32_TIM7_HANDLER Vector11C +#define STM32_TIM7_NUMBER 55 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 +#define STM32_TIM15_HANDLER VectorA0 +#define STM32_TIM15_NUMBER 24 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_HANDLER VectorA4 +#define STM32_TIM16_NUMBER 25 + +#define STM32_HAS_TIM3 FALSE +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE +#define STM32_HAS_TIM17 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_HANDLER VectorD4 +#define STM32_USART1_NUMBER 37 +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(2, 7)) +#define STM32_USART1_RX_DMA_CHN 0x02020000 +#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ + STM32_DMA_STREAM_ID_MSK(2, 6)) +#define STM32_USART1_TX_DMA_CHN 0x00202000 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_HANDLER VectorD8 +#define STM32_USART2_NUMBER 38 +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00200000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x02000000 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_HANDLER VectorDC +#define STM32_USART3_NUMBER 39 +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3)) +#define STM32_USART3_RX_DMA_CHN 0x00000200 +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2)) +#define STM32_USART3_TX_DMA_CHN 0x00000020 + +#define STM32_HAS_LPUART1 TRUE +#define STM32_LPUART1_HANDLER Vector158 +#define STM32_LPUART1_NUMBER 70 + +#define STM32_HAS_UART4 FALSE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE + +/* USB attributes.*/ +#define STM32_HAS_USB TRUE +#define STM32_USB_ACCESS_SCHEME_2x16 TRUE +#define STM32_USB_PMA_SIZE 1024 +#define STM32_USB_HAS_BCDR TRUE +#define STM32_USB1_HP_HANDLER Vector14C +#define STM32_USB1_LP_HANDLER Vector14C +#define STM32_USB1_HP_NUMBER 67 +#define STM32_USB1_LP_NUMBER 67 + +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC TRUE + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE TRUE + +#endif /* defined(STM32L443xx) */ + /*===========================================================================*/ /* STM32L476xx. */ /*===========================================================================*/ -- cgit v1.2.3