From b4e1ecc760fb1dea0089428a4ba4cdd9510e1cdb Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Wed, 11 Jan 2017 10:32:33 +0000 Subject: Various STM32 timers-related fixes into registry and RCC files. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10030 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F1xx/stm32_rcc.h | 247 ++++++++++++++++++++++++++ os/hal/ports/STM32/STM32F1xx/stm32_registry.h | 42 ++--- 2 files changed, 259 insertions(+), 30 deletions(-) (limited to 'os/hal/ports/STM32/STM32F1xx') diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h index b14261d3a..6abb74876 100644 --- a/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F1xx/stm32_rcc.h @@ -876,6 +876,253 @@ * @api */ #define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) + +/** + + * @brief Enables the TIM9 peripheral clock. + + * @note The @p lp parameter is ignored in this family. + + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp) + +/** + * @brief Disables the TIM9 peripheral clock. + + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp) + +/** + * @brief Resets the TIM9 peripheral. + * + * @api + */ +#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST) + +/** + * @brief Enables the TIM10 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp) + +/** + * @brief Disables the TIM10 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp) + +/** + * @brief Resets the TIM10 peripheral. + * + * @api + */ +#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST) + +/** + * @brief Enables the TIM11 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp) + +/** + * @brief Disables the TIM11 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp) + +/** + * @brief Resets the TIM11 peripheral. + * + * @api + */ +#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST) + +/** + * @brief Enables the TIM12 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp) + +/** + * @brief Disables the TIM12 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp) + +/** + * @brief Resets the TIM12 peripheral. + * + * @api + */ +#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST) + +/** + * @brief Enables the TIM13 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp) + +/** + * @brief Disables the TIM13 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp) + +/** + * @brief Resets the TIM13 peripheral. + * + * @api + */ +#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST) + +/** + * @brief Enables the TIM14 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp) + +/** + * @brief Disables the TIM14 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp) + +/** + * @brief Resets the TIM14 peripheral. + * + * @api + */ +#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST) + +/** + * @brief Enables the TIM15 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp) + +/** + * @brief Disables the TIM15 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM15(lp) rccDisableAPB2(RCC_APB2ENR_TIM15EN, lp) + +/** + * @brief Resets the TIM15 peripheral. + * + * @api + */ +#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST) + +/** + * @brief Enables the TIM16 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp) + +/** + * @brief Disables the TIM16 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM16(lp) rccDisableAPB2(RCC_APB2ENR_TIM16EN, lp) + +/** + * @brief Resets the TIM16 peripheral. + * + * @api + */ +#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST) + +/** + * @brief Enables the TIM17 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp) + +/** + * @brief Disables the TIM17 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM17(lp) rccDisableAPB2(RCC_APB2ENR_TIM17EN, lp) + +/** + * @brief Resets the TIM17 peripheral. + * + * @api + */ +#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST) /** @} */ /** diff --git a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h index e1e3d5e8e..e8d19a246 100644 --- a/os/hal/ports/STM32/STM32F1xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F1xx/stm32_registry.h @@ -199,11 +199,11 @@ #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE -#define STM32_TIM16_CHANNELS 2 +#define STM32_TIM16_CHANNELS 1 #define STM32_HAS_TIM17 TRUE #define STM32_TIM17_IS_32BITS FALSE -#define STM32_TIM17_CHANNELS 2 +#define STM32_TIM17_CHANNELS 1 #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM8 FALSE @@ -800,30 +800,12 @@ #define STM32_TIM8_IS_32BITS FALSE #define STM32_TIM8_CHANNELS 4 -#define STM32_HAS_TIM9 TRUE -#define STM32_TIM9_IS_32BITS FALSE -#define STM32_TIM9_CHANNELS 2 - -#define STM32_HAS_TIM10 TRUE -#define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 - -#define STM32_HAS_TIM11 TRUE -#define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 - -#define STM32_HAS_TIM12 TRUE -#define STM32_TIM12_IS_32BITS FALSE -#define STM32_TIM12_CHANNELS 2 - -#define STM32_HAS_TIM13 TRUE -#define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 - -#define STM32_HAS_TIM14 TRUE -#define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 - +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM14 FALSE #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE #define STM32_HAS_TIM17 FALSE @@ -1056,11 +1038,11 @@ #define STM32_HAS_TIM10 TRUE #define STM32_TIM10_IS_32BITS FALSE -#define STM32_TIM10_CHANNELS 2 +#define STM32_TIM10_CHANNELS 1 #define STM32_HAS_TIM11 TRUE #define STM32_TIM11_IS_32BITS FALSE -#define STM32_TIM11_CHANNELS 2 +#define STM32_TIM11_CHANNELS 1 #define STM32_HAS_TIM12 TRUE #define STM32_TIM12_IS_32BITS FALSE @@ -1068,11 +1050,11 @@ #define STM32_HAS_TIM13 TRUE #define STM32_TIM13_IS_32BITS FALSE -#define STM32_TIM13_CHANNELS 2 +#define STM32_TIM13_CHANNELS 1 #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE -#define STM32_TIM14_CHANNELS 2 +#define STM32_TIM14_CHANNELS 1 #define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM16 FALSE -- cgit v1.2.3