From ef027ec84e88621d228475ec1daa47647514ef50 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 29 Nov 2014 09:47:15 +0000 Subject: Fixed bug #550. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7548 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F0xx/hal_lld.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'os/hal/ports/STM32/STM32F0xx/hal_lld.c') diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c index d61f9a02d..7cc925c70 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c @@ -134,10 +134,18 @@ void stm32_clock_init(void) { RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ while (!(RCC->CR & RCC_CR_HSIRDY)) ; /* Wait until HSI is stable. */ + + /* HSI is selected as new source without touching the other fields in + CFGR. Clearing the register has to be postponed after HSI is the + new source.*/ + RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */ + RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + ; /* Wait until HSI is selected. */ + + /* Registers finally cleared to reset values.*/ RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ RCC->CFGR = 0; /* CFGR reset value. */ - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) - ; /* Waits until HSI is selected. */ #if STM32_HSE_ENABLED /* HSE activation.*/ -- cgit v1.2.3