From d25139221ec71ed2fbd6a9e06aa3c039c6cf9551 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Mon, 21 Sep 2015 11:01:37 +0000
Subject: Fixed bug #609. Updated STM32F1xx headers. STM32F1xx, STM32F3xx and
 STM32F37x now use the common DMAv1 driver.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8319 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c | 37 +++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

(limited to 'os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c')

diff --git a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
index 4f4daf04b..42b0001ce 100644
--- a/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
+++ b/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c
@@ -70,6 +70,11 @@
 #define STM32_DMA1_CH7_NUMBER       STM32_DMA1_CH4567_NUMBER
 #endif
 
+#if defined(STM32_DMA2_CH45_NUMBER)
+#define STM32_DMA2_CH4_NUMBER       STM32_DMA2_CH45_NUMBER
+#define STM32_DMA2_CH5_NUMBER       STM32_DMA2_CH45_NUMBER
+#endif
+
 #if STM32_DMA_SUPPORTS_CSELR == TRUE
 #define ADDR_DMA1_CSELR             &DMA1_CSELR->CSELR
 #define ADDR_DMA2_CSELR             &DMA2_CSELR->CSELR
@@ -103,8 +108,13 @@
 #define DMA2_CH1_CMASK              0x00000080U
 #define DMA2_CH2_CMASK              0x00000100U
 #define DMA2_CH3_CMASK              0x00000200U
+#if !defined(STM32_DMA2_CH45_NUMBER)
 #define DMA2_CH4_CMASK              0x00000400U
 #define DMA2_CH5_CMASK              0x00000800U
+#else
+#define DMA2_CH4_CMASK              0x00000C00U
+#define DMA2_CH5_CMASK              0x00000C00U
+#endif
 
 /*===========================================================================*/
 /* Driver exported variables.                                                */
@@ -254,7 +264,6 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH3_HANDLER) {
 }
 #endif /*!defined(STM32_DMA1_CH23_HANDLER) */
 
-
 /* Channels 4, 5, 6 and 7 are shared on some devices.*/
 #if defined(STM32_DMA1_CH4567_HANDLER)
 /**
@@ -438,6 +447,31 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH3_HANDLER) {
   OSAL_IRQ_EPILOGUE();
 }
 
+/* Channels 4 and 5 are shared on some devices.*/
+#if defined(STM32_DMA2_CH45_HANDLER)
+/**
+ * @brief   DMA2 streams 4 and 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(STM32_DMA2_CH4_HANDLER) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 12;
+  if (dma_isr_redir[10].dma_func)
+    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
+
+  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 16;
+  if (dma_isr_redir[11].dma_func)
+    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#else /* !defined(STM32_DMA2_CH45_HANDLER) */
 /**
  * @brief   DMA2 stream 4 shared interrupt handler.
  *
@@ -473,6 +507,7 @@ OSAL_IRQ_HANDLER(STM32_DMA2_CH5_HANDLER) {
 
   OSAL_IRQ_EPILOGUE();
 }
+#endif /* defined(STM32_DMA2_CH45_HANDLER) */
 #endif /* STM32_DMA2_NUM_CHANNELS > 0 */
 
 /*===========================================================================*/
-- 
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