From e50bc32840f4711a60214711d2b3982f158919f6 Mon Sep 17 00:00:00 2001 From: isiora Date: Fri, 18 Aug 2017 21:06:02 +0000 Subject: Added check to verify that the matrix H64H32 clock ratio is compatible with master clock frequency. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10451 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/SAMA/SAMA5D2x/hal_lld.h | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) (limited to 'os/hal/ports/SAMA') diff --git a/os/hal/ports/SAMA/SAMA5D2x/hal_lld.h b/os/hal/ports/SAMA/SAMA5D2x/hal_lld.h index 643afa66e..7ca8b5e1b 100644 --- a/os/hal/ports/SAMA/SAMA5D2x/hal_lld.h +++ b/os/hal/ports/SAMA/SAMA5D2x/hal_lld.h @@ -406,18 +406,6 @@ #error "PLLADIV2 must be always enabled when Main Clock Divider is 3" #endif -/** - * @brief Matrix H64H32 clock ratio. - */ - -#if ((SAMA_H64MX_H32MX_RATIO == 2) || defined(__DOXYGEN__)) -#define SAMA_H64MX_H32MX_DIV PMC_MCKR_H32MXDIV_H32MXDIV2 -#elif (SAMA_H64MX_H32MX_RATIO == 1) -#define SAMA_H64MX_H32MX_DIV PMC_MCKR_H32MXDIV_H32MXDIV1 -#else -#error "H64MX H32MX clock ratio out of range." -#endif - /** * @brief Processor Clock frequency. */ @@ -451,6 +439,21 @@ #if (SAMA_MCK > SAMA_MCK_MAX) || (SAMA_MCK < SAMA_MCK_MIN) #error "Master clock frequency out of range." #endif + +/** + * @brief Matrix H64H32 clock ratio. + */ +#if ((SAMA_H64MX_H32MX_RATIO == 2) || defined(__DOXYGEN__)) +#define SAMA_H64MX_H32MX_DIV PMC_MCKR_H32MXDIV_H32MXDIV2 +#elif (SAMA_H64MX_H32MX_RATIO == 1) +#define SAMA_H64MX_H32MX_DIV PMC_MCKR_H32MXDIV_H32MXDIV1 +#if (SAMA_MCK > 83000000) +#error "Invalid H32MXCLK. MCK > 83MHz wants SAMA_H64MX_H32MX_RATIO == 2" +#endif +#else +#error "H64MX H32MX clock ratio out of range." +#endif + /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ -- cgit v1.2.3