From f9229daa87c2b60b0a9e6be6e1cb4ebf8c8ad85f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 23 Jul 2011 07:38:56 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3170 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/DMAv1/adc_lld.c | 229 ++++++++++ os/hal/platforms/STM32/DMAv1/adc_lld.h | 354 +++++++++++++++ os/hal/platforms/STM32/DMAv1/sdc_lld.c | 722 +++++++++++++++++++++++++++++++ os/hal/platforms/STM32/DMAv1/sdc_lld.h | 203 +++++++++ os/hal/platforms/STM32/DMAv1/spi_lld.c | 428 ++++++++++++++++++ os/hal/platforms/STM32/DMAv1/spi_lld.h | 285 ++++++++++++ os/hal/platforms/STM32/DMAv1/stm32_dma.c | 468 ++++++++++++++++++++ os/hal/platforms/STM32/DMAv1/stm32_dma.h | 280 ++++++++++++ os/hal/platforms/STM32/DMAv1/uart_lld.c | 559 ++++++++++++++++++++++++ os/hal/platforms/STM32/DMAv1/uart_lld.h | 322 ++++++++++++++ os/hal/platforms/STM32/adc_lld.c | 229 ---------- os/hal/platforms/STM32/adc_lld.h | 354 --------------- os/hal/platforms/STM32/sdc_lld.c | 722 ------------------------------- os/hal/platforms/STM32/sdc_lld.h | 203 --------- os/hal/platforms/STM32/spi_lld.c | 428 ------------------ os/hal/platforms/STM32/spi_lld.h | 285 ------------ os/hal/platforms/STM32/stm32_dma.c | 468 -------------------- os/hal/platforms/STM32/stm32_dma.h | 280 ------------ os/hal/platforms/STM32/uart_lld.c | 559 ------------------------ os/hal/platforms/STM32/uart_lld.h | 322 -------------- 20 files changed, 3850 insertions(+), 3850 deletions(-) create mode 100644 os/hal/platforms/STM32/DMAv1/adc_lld.c create mode 100644 os/hal/platforms/STM32/DMAv1/adc_lld.h create mode 100644 os/hal/platforms/STM32/DMAv1/sdc_lld.c create mode 100644 os/hal/platforms/STM32/DMAv1/sdc_lld.h create mode 100644 os/hal/platforms/STM32/DMAv1/spi_lld.c create mode 100644 os/hal/platforms/STM32/DMAv1/spi_lld.h create mode 100644 os/hal/platforms/STM32/DMAv1/stm32_dma.c create mode 100644 os/hal/platforms/STM32/DMAv1/stm32_dma.h create mode 100644 os/hal/platforms/STM32/DMAv1/uart_lld.c create mode 100644 os/hal/platforms/STM32/DMAv1/uart_lld.h delete mode 100644 os/hal/platforms/STM32/adc_lld.c delete mode 100644 os/hal/platforms/STM32/adc_lld.h delete mode 100644 os/hal/platforms/STM32/sdc_lld.c delete mode 100644 os/hal/platforms/STM32/sdc_lld.h delete mode 100644 os/hal/platforms/STM32/spi_lld.c delete mode 100644 os/hal/platforms/STM32/spi_lld.h delete mode 100644 os/hal/platforms/STM32/stm32_dma.c delete mode 100644 os/hal/platforms/STM32/stm32_dma.h delete mode 100644 os/hal/platforms/STM32/uart_lld.c delete mode 100644 os/hal/platforms/STM32/uart_lld.h (limited to 'os/hal/platforms') diff --git a/os/hal/platforms/STM32/DMAv1/adc_lld.c b/os/hal/platforms/STM32/DMAv1/adc_lld.c new file mode 100644 index 000000000..8a8027e55 --- /dev/null +++ b/os/hal/platforms/STM32/DMAv1/adc_lld.c @@ -0,0 +1,229 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/adc_lld.c + * @brief STM32 ADC subsystem low level driver source. + * + * @addtogroup ADC + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared ADC DMA ISR service routine. + * + * @param[in] adcp pointer to the @p ADCDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_ADC_DMA_ERROR_HOOK) + if ((flags & DMA_ISR_TEIF1) != 0) { + STM32_ADC_DMA_ERROR_HOOK(spip); + } +#else + (void)flags; +#endif + if ((flags & DMA_ISR_HTIF1) != 0) { + /* Half transfer processing.*/ + _adc_isr_half_code(adcp); + } + if ((flags & DMA_ISR_TCIF1) != 0) { + /* Transfer complete processing.*/ + _adc_isr_full_code(adcp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if STM32_ADC_USE_ADC1 + /* Driver initialization.*/ + adcObjectInit(&ADCD1); + ADCD1.adc = ADC1; + ADCD1.dmachp = STM32_DMA1_CH1; + ADCD1.dmaccr = (STM32_ADC_ADC1_DMA_PRIORITY << 12) | + DMA_CCR1_EN | DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0 | + DMA_CCR1_MINC | DMA_CCR1_TCIE | DMA_CCR1_TEIE; + + /* Temporary activation.*/ + RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; + ADC1->CR1 = 0; + ADC1->CR2 = ADC_CR2_ADON; + + /* Reset calibration just to be safe.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; + while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) + ; + + /* Calibration.*/ + ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; + while ((ADC1->CR2 & ADC_CR2_CAL) != 0) + ; + + /* Return the ADC in low power mode.*/ + ADC1->CR2 = 0; + RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN; +#endif +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC and DMA clocks.*/ + if (adcp->state == ADC_STOP) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_1, + (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, (void *)adcp); + NVICEnableVector(DMA1_Channel1_IRQn, + CORTEX_PRIORITY_MASK(STM32_ADC_ADC1_IRQ_PRIORITY)); + dmaChannelSetPeripheral(adcp->dmachp, &ADC1->DR); + RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; + } +#endif + + /* ADC setup, the calibration procedure has already been performed + during initialization.*/ + adcp->adc->CR1 = ADC_CR1_SCAN; + adcp->adc->CR2 = 0; + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { +#if STM32_ADC_USE_ADC1 + if (&ADCD1 == adcp) { + ADC1->CR1 = 0; + ADC1->CR2 = 0; + NVICDisableVector(DMA1_Channel1_IRQn); + dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_1); + RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN; + } +#endif + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + uint32_t ccr, n; + const ADCConversionGroup *grpp = adcp->grpp; + + /* DMA setup.*/ + ccr = adcp->dmaccr; + if (grpp->circular) + ccr |= DMA_CCR1_CIRC; + if (adcp->depth > 1) { + /* If the buffer depth is greater than one then the half transfer interrupt + interrupt is enabled in order to allows streaming processing.*/ + ccr |= DMA_CCR1_HTIE; + n = (uint32_t)grpp->num_channels * (uint32_t)adcp->depth; + } + else + n = (uint32_t)grpp->num_channels; + dmaChannelSetup(adcp->dmachp, n, adcp->samples, ccr); + + /* ADC setup.*/ + adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN; + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | + ADC_CR2_CONT | ADC_CR2_ADON; + adcp->adc->SMPR1 = grpp->smpr1; + adcp->adc->SMPR2 = grpp->smpr2; + adcp->adc->SQR1 = grpp->sqr1; + adcp->adc->SQR2 = grpp->sqr2; + adcp->adc->SQR3 = grpp->sqr3; + + /* ADC start by writing ADC_CR2_ADON a second time.*/ + adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | + ADC_CR2_CONT | ADC_CR2_ADON; +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + + dmaChannelDisable(adcp->dmachp); + adcp->adc->CR2 = 0; +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/adc_lld.h b/os/hal/platforms/STM32/DMAv1/adc_lld.h new file mode 100644 index 000000000..ce93e60ed --- /dev/null +++ b/os/hal/platforms/STM32/DMAv1/adc_lld.h @@ -0,0 +1,354 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/adc_lld.h + * @brief STM32 ADC subsystem low level driver header. + * + * @addtogroup ADC + * @{ + */ + +#ifndef _ADC_LLD_H_ +#define _ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ +#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ + +#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ +#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ +#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ +#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ +#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ +#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ +#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ +#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ +#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ +#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ +#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ +#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ +#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ +#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ +#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ +#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ +#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ +#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ + +#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ +#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ +#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ +#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ +#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ +#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ +#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ +#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief ADC1 driver enable switch. + * @details If set to @p TRUE the support for ADC1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) +#define STM32_ADC_USE_ADC1 TRUE +#endif + +/** + * @brief ADC1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#endif + +/** + * @brief ADC1 interrupt priority level setting. + */ +#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_ADC_ADC1_IRQ_PRIORITY 5 +#endif + +/** + * @brief ADC DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_ADC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 +#error "ADC1 not present in the selected device" +#endif + +#if !STM32_ADC_USE_ADC1 +#error "ADC driver activated but no ADC peripheral assigned" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief ADC sample data type. + */ +typedef uint16_t adcsample_t; + +/** + * @brief Channels number in a conversion group. + */ +typedef uint16_t adc_channels_num_t; + +/** + * @brief Type of a structure representing an ADC driver. + */ +typedef struct ADCDriver ADCDriver; + +/** + * @brief ADC notification callback type. + * + * @param[in] adcp pointer to the @p ADCDriver object triggering the + * callback + * @param[in] buffer pointer to the most recent samples data + * @param[in] n number of buffer rows available starting from @p buffer + */ +typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); + +/** + * @brief Conversion group configuration structure. + * @details This implementation-dependent structure describes a conversion + * operation. + * @note The use of this configuration structure requires knowledge of + * STM32 ADC cell registers interface, please refer to the STM32 + * reference manual for details. + */ +typedef struct { + /** + * @brief Enables the circular buffer mode for the group. + */ + bool_t circular; + /** + * @brief Number of the analog channels belonging to the conversion group. + */ + adc_channels_num_t num_channels; + /** + * @brief Callback function associated to the group or @p NULL. + */ + adccallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief ADC CR1 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR1_SCAN that is enforced inside the driver. + */ + uint32_t cr1; + /** + * @brief ADC CR2 register initialization data. + * @note All the required bits must be defined into this field except + * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are + * enforced inside the driver. + */ + uint32_t cr2; + /** + * @brief ADC SMPR1 register initialization data. + * @details In this field must be specified the sample times for channels + * 10...17. + */ + uint32_t smpr1; + /** + * @brief ADC SMPR2 register initialization data. + * @details In this field must be specified the sample times for channels + * 0...9. + */ + uint32_t smpr2; + /** + * @brief ADC SQR1 register initialization data. + * @details Conversion group sequence 13...16 + sequence length. + */ + uint32_t sqr1; + /** + * @brief ADC SQR2 register initialization data. + * @details Conversion group sequence 7...12. + */ + uint32_t sqr2; + /** + * @brief ADC SQR3 register initialization data. + * @details Conversion group sequence 0...6. + */ + uint32_t sqr3; +} ADCConversionGroup; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} ADCConfig; + +/** + * @brief Structure representing an ADC driver. + */ +struct ADCDriver { + /** + * @brief Driver state. + */ + adcstate_t state; + /** + * @brief Current configuration data. + */ + const ADCConfig *config; + /** + * @brief Current samples buffer pointer or @p NULL. + */ + adcsample_t *samples; + /** + * @brief Current samples buffer depth or @p 0. + */ + size_t depth; + /** + * @brief Current conversion group pointer or @p NULL. + */ + const ADCConversionGroup *grpp; +#if ADC_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif +#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the peripheral. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* ADC_USE_MUTUAL_EXCLUSION */ +#if defined(ADC_DRIVER_EXT_FIELDS) + ADC_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the ADCx registers block. + */ + ADC_TypeDef *adc; + /** + * @brief Pointer to the DMA registers block. + */ + stm32_dma_channel_t *dmachp; + /** + * @brief DMA CCR register bit mask. + */ + uint32_t dmaccr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Number of channels in a conversion sequence. + */ +#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) + +#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ +#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ +#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ +#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ +#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ +#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ + +#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ +#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ +#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ +#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ +#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ +#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ + +#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ +#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ +#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ +#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ + +#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ +#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ +#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ +#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ +#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ +#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ +#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ +#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ +#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ +#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ + +#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ +#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ +#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ +#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ +#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ +#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ +#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor + sampling time. */ +#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference + sampling time. */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) +extern ADCDriver ADCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void adc_lld_init(void); + void adc_lld_start(ADCDriver *adcp); + void adc_lld_stop(ADCDriver *adcp); + void adc_lld_start_conversion(ADCDriver *adcp); + void adc_lld_stop_conversion(ADCDriver *adcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_ADC */ + +#endif /* _ADC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/sdc_lld.c b/os/hal/platforms/STM32/DMAv1/sdc_lld.c new file mode 100644 index 000000000..a88ad53fa --- /dev/null +++ b/os/hal/platforms/STM32/DMAv1/sdc_lld.c @@ -0,0 +1,722 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/sdc_lld.c + * @brief STM32 SDC subsystem low level driver source. + * + * @addtogroup SDC + * @{ + */ + +#include + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SDCD1 driver identifier.*/ +SDCDriver SDCD1; + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +#if STM32_SDC_UNALIGNED_SUPPORT +/** + * @brief Buffer for temporary storage during unaligned transfers. + */ +static union { + uint32_t alignment; + uint8_t buf[SDC_BLOCK_SIZE]; +} u; +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Reads one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer, it must be aligned to + * four bytes boundary + * @param[in] n number of blocks to read + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * read. + * @retval TRUE operation failed, the state of the buffer is uncertain. + * + * @notapi + */ +static bool_t sdc_lld_read_multiple(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n) { + uint32_t resp[1]; + + /* Checks for errors and waits for the card to be ready for reading.*/ + if (sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Prepares the DMA channel for reading.*/ + dmaChannelSetup(&STM32_DMA2->channels[STM32_DMA_CHANNEL_4], + (n * SDC_BLOCK_SIZE) / sizeof (uint32_t), buf, + (STM32_SDC_SDIO_DMA_PRIORITY << 12) | + DMA_CCR1_PSIZE_1 | DMA_CCR1_MSIZE_1 | + DMA_CCR1_MINC); + + /* Setting up data transfer. + Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/ + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_DATAENDIE | SDIO_MASK_STBITERRIE; + SDIO->DLEN = n * SDC_BLOCK_SIZE; + SDIO->DCTRL = SDIO_DCTRL_DTDIR | + SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + + /* DMA channel activation.*/ + dmaEnableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + + /* Read multiple blocks command.*/ + if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) + startblk *= SDC_BLOCK_SIZE; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_MULTIPLE_BLOCK, + startblk, resp) || + SDC_R1_ERROR(resp[0])) + goto error; + + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_read_multiple(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_read_multiple(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + goto error; + } + dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->DCTRL = 0; + chSysUnlock(); + + return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp); +error: + dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + return TRUE; +} + +/** + * @brief Reads one block. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer, it must be aligned to + * four bytes boundary + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * read. + * @retval TRUE operation failed, the state of the buffer is uncertain. + * + * @notapi + */ +static bool_t sdc_lld_read_single(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf) { + uint32_t resp[1]; + + /* Checks for errors and waits for the card to be ready for reading.*/ + if (sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Prepares the DMA channel for reading.*/ + dmaChannelSetup(&STM32_DMA2->channels[STM32_DMA_CHANNEL_4], + SDC_BLOCK_SIZE / sizeof (uint32_t), buf, + (STM32_SDC_SDIO_DMA_PRIORITY << 12) | + DMA_CCR1_PSIZE_1 | DMA_CCR1_MSIZE_1 | + DMA_CCR1_MINC); + + /* Setting up data transfer. + Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/ + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_DATAENDIE | SDIO_MASK_STBITERRIE; + SDIO->DLEN = SDC_BLOCK_SIZE; + SDIO->DCTRL = SDIO_DCTRL_DTDIR | + SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + + /* DMA channel activation.*/ + dmaEnableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + + /* Read single block command.*/ + if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) + startblk *= SDC_BLOCK_SIZE; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_SINGLE_BLOCK, + startblk, resp) || + SDC_R1_ERROR(resp[0])) + goto error; + + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_read_single(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_read_single(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + goto error; + } + dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->DCTRL = 0; + chSysUnlock(); + + return FALSE; +error: + dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + return TRUE; +} + +/** + * @brief Writes one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer, it must be aligned to + * four bytes boundary + * @param[in] n number of blocks to write + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * written. + * @retval TRUE operation failed. + * + * @notapi + */ +static bool_t sdc_lld_write_multiple(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n) { + uint32_t resp[1]; + + /* Checks for errors and waits for the card to be ready for writing.*/ + if (sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Prepares the DMA channel for writing.*/ + dmaChannelSetup(&STM32_DMA2->channels[STM32_DMA_CHANNEL_4], + (n * SDC_BLOCK_SIZE) / sizeof (uint32_t), buf, + (STM32_SDC_SDIO_DMA_PRIORITY << 12) | + DMA_CCR1_PSIZE_1 | DMA_CCR1_MSIZE_1 | + DMA_CCR1_MINC | DMA_CCR1_DIR); + + /* Write multiple blocks command.*/ + if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) + startblk *= SDC_BLOCK_SIZE; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_MULTIPLE_BLOCK, + startblk, resp) || + SDC_R1_ERROR(resp[0])) + return TRUE; + + /* Setting up data transfer. + Options: Controller to Card, Block mode, DMA mode, 512 bytes blocks.*/ + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | + SDIO_MASK_STBITERRIE; + SDIO->DLEN = n * SDC_BLOCK_SIZE; + SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + + /* DMA channel activation.*/ + dmaEnableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + + /* Note the mask is checked before going to sleep because the interrupt + may have occurred before reaching the critical zone.*/ + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_write_multiple(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_write_multiple(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + goto error; + } + dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->DCTRL = 0; + chSysUnlock(); + + return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp); +error: + dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + return TRUE; +} + +/** + * @brief Writes one block. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer, it must be aligned to + * four bytes boundary + * @param[in] n number of blocks to write + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * written. + * @retval TRUE operation failed. + * + * @notapi + */ +static bool_t sdc_lld_write_single(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf) { + uint32_t resp[1]; + + /* Checks for errors and waits for the card to be ready for writing.*/ + if (sdc_wait_for_transfer_state(sdcp)) + return TRUE; + + /* Prepares the DMA channel for writing.*/ + dmaChannelSetup(&STM32_DMA2->channels[STM32_DMA_CHANNEL_4], + SDC_BLOCK_SIZE / sizeof (uint32_t), buf, + (STM32_SDC_SDIO_DMA_PRIORITY << 12) | + DMA_CCR1_PSIZE_1 | DMA_CCR1_MSIZE_1 | + DMA_CCR1_MINC | DMA_CCR1_DIR); + + /* Write single block command.*/ + if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) + startblk *= SDC_BLOCK_SIZE; + if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_BLOCK, + startblk, resp) || + SDC_R1_ERROR(resp[0])) + return TRUE; + + /* Setting up data transfer. + Options: Controller to Card, Block mode, DMA mode, 512 bytes blocks.*/ + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | + SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | + SDIO_MASK_STBITERRIE; + SDIO->DLEN = SDC_BLOCK_SIZE; + SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | + SDIO_DCTRL_DMAEN | + SDIO_DCTRL_DTEN; + + /* DMA channel activation.*/ + dmaEnableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + + /* Note the mask is checked before going to sleep because the interrupt + may have occurred before reaching the critical zone.*/ + chSysLock(); + if (SDIO->MASK != 0) { + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_write_single(), #1", "not NULL"); + sdcp->thread = chThdSelf(); + chSchGoSleepS(THD_STATE_SUSPENDED); + chDbgAssert(sdcp->thread == NULL, + "sdc_lld_write_single(), #2", "not NULL"); + } + if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { + chSysUnlock(); + goto error; + } + dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->DCTRL = 0; + chSysUnlock(); + + return FALSE; +error: + dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + SDIO->ICR = 0xFFFFFFFF; + SDIO->MASK = 0; + SDIO->DCTRL = 0; + return TRUE; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief SDIO IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(SDIO_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + if (SDCD1.thread != NULL) { + chSchReadyI(SDCD1.thread); + SDCD1.thread = NULL; + } + chSysUnlockFromIsr(); + + /* Disables the source but the status flags are not reset because the + read/write functions need to check them.*/ + SDIO->MASK = 0; + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SDC driver initialization. + * + * @notapi + */ +void sdc_lld_init(void) { + + sdcObjectInit(&SDCD1); + SDCD1.thread = NULL; +} + +/** + * @brief Configures and activates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object, must be @p NULL, + * this driver does not require any configuration + * + * @notapi + */ +void sdc_lld_start(SDCDriver *sdcp) { + + if (sdcp->state == SDC_STOP) { + /* Note, the DMA must be enabled before the IRQs.*/ + dmaAllocate(STM32_DMA2_ID, STM32_DMA_CHANNEL_4, NULL, NULL); + dmaChannelSetPeripheral(&STM32_DMA2->channels[STM32_DMA_CHANNEL_4], &SDIO->FIFO); + NVICEnableVector(SDIO_IRQn, + CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY)); + RCC->AHBENR |= RCC_AHBENR_SDIOEN; + } + /* Configuration, card clock is initially stopped.*/ + SDIO->POWER = 0; + SDIO->CLKCR = 0; + SDIO->DCTRL = 0; + SDIO->DTIMER = STM32_SDC_DATATIMEOUT; +} + +/** + * @brief Deactivates the SDC peripheral. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_stop(SDCDriver *sdcp) { + + if ((sdcp->state == SDC_READY) || (sdcp->state == SDC_ACTIVE)) { + SDIO->POWER = 0; + SDIO->CLKCR = 0; + SDIO->DCTRL = 0; + SDIO->DTIMER = 0; + + /* Clock deactivation.*/ + NVICDisableVector(SDIO_IRQn); + dmaRelease(STM32_DMA2_ID, STM32_DMA_CHANNEL_4); + } +} + +/** + * @brief Starts the SDIO clock and sets it to init mode (400KHz or less). + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_start_clk(SDCDriver *sdcp) { + + (void)sdcp; + /* Initial clock setting: 400KHz, 1bit mode.*/ + SDIO->CLKCR = STM32_SDIO_DIV_LS; + SDIO->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1; + SDIO->CLKCR |= SDIO_CLKCR_CLKEN; +} + +/** + * @brief Sets the SDIO clock to data mode (25MHz or less). + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_set_data_clk(SDCDriver *sdcp) { + + (void)sdcp; + SDIO->CLKCR = (SDIO->CLKCR & 0xFFFFFF00) | STM32_SDIO_DIV_HS; +} + +/** + * @brief Stops the SDIO clock. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * + * @notapi + */ +void sdc_lld_stop_clk(SDCDriver *sdcp) { + + (void)sdcp; + SDIO->CLKCR = 0; + SDIO->POWER = 0; +} + +/** + * @brief Switches the bus to 4 bits mode. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] mode bus mode + * + * @notapi + */ +void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { + uint32_t clk = SDIO->CLKCR & ~SDIO_CLKCR_WIDBUS; + + (void)sdcp; + switch (mode) { + case SDC_MODE_1BIT: + SDIO->CLKCR = clk; + break; + case SDC_MODE_4BIT: + SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_0; + break; + case SDC_MODE_8BIT: + SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_1; + } +} + +/** + * @brief Sends an SDIO command with no response expected. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * + * @notapi + */ +void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { + + (void)sdcp; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_CPSMEN; + while ((SDIO->STA & SDIO_STA_CMDSENT) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDSENTC; +} + +/** + * @brief Sends an SDIO command with a short response expected. + * @note The CRC is not verified. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (one word) + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed because timeout, CRC check or + * other errors. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + uint32_t sta; + + (void)sdcp; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; + while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | + SDIO_STA_CCRCFAIL)) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; + if ((sta & (SDIO_STA_CTIMEOUT)) != 0) + return TRUE; + *resp = SDIO->RESP1; + return FALSE; +} + +/** + * @brief Sends an SDIO command with a short response expected and CRC. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (one word) + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed because timeout, CRC check or + * other errors. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + uint32_t sta; + + (void)sdcp; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; + while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | + SDIO_STA_CCRCFAIL)) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; + if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) + return TRUE; + *resp = SDIO->RESP1; + return FALSE; +} + +/** + * @brief Sends an SDIO command with a long response expected and CRC. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] cmd card command + * @param[in] arg command argument + * @param[out] resp pointer to the response buffer (four words) + * @return The operation status. + * @retval FALSE the operation succeeded. + * @retval TRUE the operation failed because timeout, CRC check or + * other errors. + * + * @notapi + */ +bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp) { + + uint32_t sta; + + (void)sdcp; + SDIO->ARG = arg; + SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_WAITRESP_1 | + SDIO_CMD_CPSMEN; + while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | + SDIO_STA_CCRCFAIL)) == 0) + ; + SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; + if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) + return TRUE; + *resp = SDIO->RESP1; + return FALSE; +} + +/** + * @brief Reads one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to read + * @param[out] buf pointer to the read buffer + * @param[in] n number of blocks to read + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * read. + * @retval TRUE operation failed, the state of the buffer is uncertain. + * + * @notapi + */ +bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n) { + +#if STM32_SDC_UNALIGNED_SUPPORT + if (((unsigned)buf & 3) != 0) { + uint32_t i; + for (i = 0; i < n; i++) { + if (sdc_lld_read_single(sdcp, startblk, u.buf)) + return TRUE; + memcpy(buf, u.buf, SDC_BLOCK_SIZE); + buf += SDC_BLOCK_SIZE; + startblk++; + } + return FALSE; + } +#endif + if (n == 1) + return sdc_lld_read_single(sdcp, startblk, buf); + return sdc_lld_read_multiple(sdcp, startblk, buf, n); +} + +/** + * @brief Writes one or more blocks. + * + * @param[in] sdcp pointer to the @p SDCDriver object + * @param[in] startblk first block to write + * @param[out] buf pointer to the write buffer + * @param[in] n number of blocks to write + * @return The operation status. + * @retval FALSE operation succeeded, the requested blocks have been + * written. + * @retval TRUE operation failed. + * + * @notapi + */ +bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n) { + + #if STM32_SDC_UNALIGNED_SUPPORT + if (((unsigned)buf & 3) != 0) { + uint32_t i; + for (i = 0; i < n; i++) { + memcpy(u.buf, buf, SDC_BLOCK_SIZE); + buf += SDC_BLOCK_SIZE; + if (sdc_lld_write_single(sdcp, startblk, u.buf)) + return TRUE; + startblk++; + } + return FALSE; + } +#endif + if (n == 1) + return sdc_lld_write_single(sdcp, startblk, buf); + return sdc_lld_write_multiple(sdcp, startblk, buf, n); +} + +#endif /* HAL_USE_SDC */ + +/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/sdc_lld.h b/os/hal/platforms/STM32/DMAv1/sdc_lld.h new file mode 100644 index 000000000..5466eacad --- /dev/null +++ b/os/hal/platforms/STM32/DMAv1/sdc_lld.h @@ -0,0 +1,203 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/sdc_lld.h + * @brief STM32 SDC subsystem low level driver header. + * + * @addtogroup SDC + * @{ + */ + +#ifndef _SDC_LLD_H_ +#define _SDC_LLD_H_ + +#if HAL_USE_SDC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SDIO data timeout in SDIO clock cycles. + */ +#if !defined(STM32_SDC_DATATIMEOUT) || defined(__DOXYGEN__) +#define STM32_SDC_DATATIMEOUT 0x000FFFFF +#endif + +/** + * @brief SDIO DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_SDC_SDIO_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#endif + +/** + * @brief SDIO interrupt priority level setting. + */ +#if !defined(STM32_SDC_SDIO_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#endif + +/** + * @brief SDIO support for unaligned transfers. + */ +#if !defined(STM32_SDC_UNALIGNED_SUPPORT) || defined(__DOXYGEN__) +#define STM32_SDC_UNALIGNED_SUPPORT TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_HAS_SDIO +#error "SDIO not present in the selected device" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/* + * SDIO clock divider. + */ +#if STM32_HCLK > 48000000 +#define STM32_SDIO_DIV_HS 0x01 +#define STM32_SDIO_DIV_LS 0xB2 +#else +#define STM32_SDIO_DIV_HS 0x00 +#define STM32_SDIO_DIV_LS 0x76 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of SDIO bus mode. + */ +typedef enum { + SDC_MODE_1BIT = 0, + SDC_MODE_4BIT, + SDC_MODE_8BIT +} sdcbusmode_t; + +/** + * @brief Type of card flags. + */ +typedef uint32_t sdcmode_t; + +/** + * @brief Type of a structure representing an SDC driver. + */ +typedef struct SDCDriver SDCDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + uint32_t dummy; +} SDCConfig; + +/** + * @brief Structure representing an SDC driver. + */ +struct SDCDriver { + /** + * @brief Driver state. + */ + sdcstate_t state; + /** + * @brief Current configuration data. + */ + const SDCConfig *config; + /** + * @brief Various flags regarding the mounted card. + */ + sdcmode_t cardmode; + /** + * @brief Card CID. + */ + uint32_t cid[4]; + /** + * @brief Card CSD. + */ + uint32_t csd[4]; + /** + * @brief Card RCA. + */ + uint32_t rca; + /* End of the mandatory fields.*/ + /** + * @brief Tthread waiting for I/O completion IRQ. + */ + Thread *thread; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern SDCDriver SDCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sdc_lld_init(void); + void sdc_lld_start(SDCDriver *sdcp); + void sdc_lld_stop(SDCDriver *sdcp); + void sdc_lld_start_clk(SDCDriver *sdcp); + void sdc_lld_set_data_clk(SDCDriver *sdcp); + void sdc_lld_stop_clk(SDCDriver *sdcp); + void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode); + void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg); + bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, + uint32_t *resp); + bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, + uint8_t *buf, uint32_t n); + bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, + const uint8_t *buf, uint32_t n); + bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp); + bool_t sdc_lld_is_write_protected(SDCDriver *sdcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SDC */ + +#endif /* _SDC_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/spi_lld.c b/os/hal/platforms/STM32/DMAv1/spi_lld.c new file mode 100644 index 000000000..d8ae657a7 --- /dev/null +++ b/os/hal/platforms/STM32/DMAv1/spi_lld.c @@ -0,0 +1,428 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/spi_lld.c + * @brief STM32 SPI subsystem low level driver source. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SPI1 driver identifier.*/ +#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/** @brief SPI2 driver identifier.*/ +#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) +SPIDriver SPID2; +#endif + +/** @brief SPI3 driver identifier.*/ +#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__) +SPIDriver SPID3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +static uint16_t dummytx; +static uint16_t dummyrx; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Stops the SPI DMA channels. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +#define dma_stop(spip) { \ + dmaChannelDisable(spip->dmatx); \ + dmaChannelDisable(spip->dmarx); \ +} + +/** + * @brief Starts the SPI DMA channels. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +#define dma_start(spip) { \ + dmaChannelEnable((spip)->dmarx); \ + dmaChannelEnable((spip)->dmatx); \ +} + +/** + * @brief Shared end-of-rx service routine. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_SPI_DMA_ERROR_HOOK) + if ((flags & DMA_ISR_TEIF1) != 0) { + STM32_SPI_DMA_ERROR_HOOK(spip); + } +#else + (void)flags; +#endif + + /* Stop everything.*/ + dma_stop(spip); + + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); +} + +/** + * @brief Shared end-of-tx service routine. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_SPI_DMA_ERROR_HOOK) + (void)spip; + if ((flags & DMA_ISR_TEIF1) != 0) { + STM32_SPI_DMA_ERROR_HOOK(spip); + } +#else + (void)spip; + (void)flags; +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + + dummytx = 0xFFFF; + +#if STM32_SPI_USE_SPI1 + spiObjectInit(&SPID1); + SPID1.thread = NULL; + SPID1.spi = SPI1; + SPID1.dmarx = STM32_DMA1_CH2; + SPID1.dmatx = STM32_DMA1_CH3; +#endif + +#if STM32_SPI_USE_SPI2 + spiObjectInit(&SPID2); + SPID2.thread = NULL; + SPID2.spi = SPI2; + SPID2.dmarx = STM32_DMA1_CH4; + SPID2.dmatx = STM32_DMA1_CH5; +#endif + +#if STM32_SPI_USE_SPI3 + spiObjectInit(&SPID3); + SPID3.thread = NULL; + SPID3.spi = SPI3; + SPID3.dmarx = STM32_DMA2_CH1; + SPID3.dmatx = STM32_DMA2_CH2; +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + /* If in stopped state then enables the SPI and DMA clocks.*/ + if (spip->state == SPI_STOP) { +#if STM32_SPI_USE_SPI1 + if (&SPID1 == spip) { + /* Note, the DMA must be enabled before the IRQs.*/ + dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_2, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); + dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_3, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); + NVICEnableVector(DMA1_Channel2_IRQn, + CORTEX_PRIORITY_MASK(STM32_SPI_SPI1_IRQ_PRIORITY)); + NVICEnableVector(DMA1_Channel3_IRQn, + CORTEX_PRIORITY_MASK(STM32_SPI_SPI1_IRQ_PRIORITY)); + RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; + } +#endif +#if STM32_SPI_USE_SPI2 + if (&SPID2 == spip) { + /* Note, the DMA must be enabled before the IRQs.*/ + dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_4, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); + dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_5, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); + NVICEnableVector(DMA1_Channel4_IRQn, + CORTEX_PRIORITY_MASK(STM32_SPI_SPI2_IRQ_PRIORITY)); + NVICEnableVector(DMA1_Channel5_IRQn, + CORTEX_PRIORITY_MASK(STM32_SPI_SPI2_IRQ_PRIORITY)); + RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; + } +#endif +#if STM32_SPI_USE_SPI3 + if (&SPID3 == spip) { + /* Note, the DMA must be enabled before the IRQs.*/ + dmaAllocate(STM32_DMA2_ID, STM32_DMA_CHANNEL_1, + (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); + dmaAllocate(STM32_DMA2_ID, STM32_DMA_CHANNEL_2, + (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); + NVICEnableVector(DMA2_Channel1_IRQn, + CORTEX_PRIORITY_MASK(STM32_SPI_SPI3_IRQ_PRIORITY)); + NVICEnableVector(DMA2_Channel2_IRQn, + CORTEX_PRIORITY_MASK(STM32_SPI_SPI3_IRQ_PRIORITY)); + RCC->APB1ENR |= RCC_APB1ENR_SPI3EN; + } +#endif + + /* DMA setup.*/ + dmaChannelSetPeripheral(spip->dmarx, &spip->spi->DR); + dmaChannelSetPeripheral(spip->dmatx, &spip->spi->DR); + } + + /* More DMA setup.*/ + if ((spip->config->cr1 & SPI_CR1_DFF) == 0) + spip->dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) | + DMA_CCR1_TEIE; /* 8 bits transfers. */ + else + spip->dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) | + DMA_CCR1_TEIE | DMA_CCR1_MSIZE_0 | + DMA_CCR1_PSIZE_0; /* 16 bits transfers. */ + + /* SPI setup and enable.*/ + spip->spi->CR1 = 0; + spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | + SPI_CR1_SSI; + spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; + spip->spi->CR1 |= SPI_CR1_SPE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + /* If in ready state then disables the SPI clock.*/ + if (spip->state == SPI_READY) { + + /* SPI disable.*/ + spip->spi->CR1 = 0; + +#if STM32_SPI_USE_SPI1 + if (&SPID1 == spip) { + NVICDisableVector(DMA1_Channel2_IRQn); + NVICDisableVector(DMA1_Channel3_IRQn); + dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_2); + dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_3); + RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN; + } +#endif +#if STM32_SPI_USE_SPI2 + if (&SPID2 == spip) { + NVICDisableVector(DMA1_Channel4_IRQn); + NVICDisableVector(DMA1_Channel5_IRQn); + dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_4); + dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_5); + RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN; + } +#endif +#if STM32_SPI_USE_SPI3 + if (&SPID3 == spip) { + NVICDisableVector(DMA2_Channel1_IRQn); + NVICDisableVector(DMA2_Channel2_IRQn); + dmaRelease(STM32_DMA2_ID, STM32_DMA_CHANNEL_1); + dmaRelease(STM32_DMA2_ID, STM32_DMA_CHANNEL_2); + RCC->APB1ENR &= ~RCC_APB1ENR_SPI3EN; + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + dmaChannelSetup(spip->dmarx, n, &dummyrx, + spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN); + dmaChannelSetup(spip->dmatx, n, &dummytx, + spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN); +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + dmaChannelSetup(spip->dmarx, n, rxbuf, + spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC | + DMA_CCR1_EN); + dmaChannelSetup(spip->dmatx, n, txbuf, + spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC | + DMA_CCR1_EN); +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + dmaChannelSetup(spip->dmarx, n, &dummyrx, + spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN); + dmaChannelSetup(spip->dmatx, n, txbuf, + spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC | + DMA_CCR1_EN); +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + dmaChannelSetup(spip->dmarx, n, rxbuf, + spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC | + DMA_CCR1_EN); + dmaChannelSetup(spip->dmatx, n, &dummytx, + spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN); +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->spi->DR = frame; + while ((spip->spi->SR & SPI_SR_RXNE) == 0) + ; + return spip->spi->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/spi_lld.h b/os/hal/platforms/STM32/DMAv1/spi_lld.h new file mode 100644 index 000000000..6f1e94096 --- /dev/null +++ b/os/hal/platforms/STM32/DMAv1/spi_lld.h @@ -0,0 +1,285 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/spi_lld.h + * @brief STM32 SPI subsystem low level driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for SPI1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI1 TRUE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for SPI2 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI2 TRUE +#endif + +/** + * @brief SPI3 driver enable switch. + * @details If set to @p TRUE the support for SPI3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__) +#define STM32_SPI_USE_SPI3 FALSE +#endif + +/** + * @brief SPI1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI2 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI3 interrupt priority level setting. + */ +#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#endif + +/** + * @brief SPI DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1 +#error "SPI1 not present in the selected device" +#endif + +#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2 +#error "SPI2 not present in the selected device" +#endif + +#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3 +#error "SPI3 not present in the selected device" +#endif + +#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SPI initialization data. + */ + uint16_t cr1; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver{ + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SPIx registers block. + */ + SPI_TypeDef *spi; + /** + * @brief Pointer to the receive DMA channel registers block. + */ + stm32_dma_channel_t *dmarx; + /** + * @brief Pointer to the transmit DMA channel registers block. + */ + stm32_dma_channel_t *dmatx; + /** + * @brief DMA priority bit mask. + */ + uint32_t dmaccr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__) +extern SPIDriver SPID3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/stm32_dma.c b/os/hal/platforms/STM32/DMAv1/stm32_dma.c new file mode 100644 index 000000000..2232df448 --- /dev/null +++ b/os/hal/platforms/STM32/DMAv1/stm32_dma.c @@ -0,0 +1,468 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file stm32_dma.c + * @brief STM32 DMA helper driver code. + * + * @addtogroup STM32_DMA + * @details DMA sharing helper driver. In the STM32 the DMA channels are a + * shared resource, this driver allows to allocate and free DMA + * channels at runtime in order to allow all the other device + * drivers to coordinate the access to the resource. + * @note The DMA ISR handlers are all declared into this module because + * sharing, the various device drivers can associate a callback to + * IRSs when allocating channels. + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief DMA ISR redirector type. + */ +typedef struct { + stm32_dmaisr_t dmaisrfunc; + void *dmaisrparam; +} dma_isr_redir_t; + +static uint32_t dmamsk1; +static dma_isr_redir_t dma1[7]; + +#if STM32_HAS_DMA2 +static uint32_t dmamsk2; +static dma_isr_redir_t dma2[5]; +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief DMA1 channel 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_1 * 4); + dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_1); + if (dma1[0].dmaisrfunc) + dma1[0].dmaisrfunc(dma1[0].dmaisrparam, isr); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 channel 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_2 * 4); + dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_2); + if (dma1[1].dmaisrfunc) + dma1[1].dmaisrfunc(dma1[1].dmaisrparam, isr); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 channel 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_3 * 4); + dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_3); + if (dma1[2].dmaisrfunc) + dma1[2].dmaisrfunc(dma1[2].dmaisrparam, isr); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 channel 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_4 * 4); + dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_4); + if (dma1[3].dmaisrfunc) + dma1[3].dmaisrfunc(dma1[3].dmaisrparam, isr); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 channel 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_5 * 4); + dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_5); + if (dma1[4].dmaisrfunc) + dma1[4].dmaisrfunc(dma1[4].dmaisrparam, isr); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 channel 6 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_6 * 4); + dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_6); + if (dma1[5].dmaisrfunc) + dma1[5].dmaisrfunc(dma1[5].dmaisrparam, isr); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA1 channel 7 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_7 * 4); + dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_7); + if (dma1[6].dmaisrfunc) + dma1[6].dmaisrfunc(dma1[6].dmaisrparam, isr); + + CH_IRQ_EPILOGUE(); +} + +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) +/** + * @brief DMA2 channel 1 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_1 * 4); + dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_1); + if (dma2[0].dmaisrfunc) + dma2[0].dmaisrfunc(dma2[0].dmaisrparam, isr); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 channel 2 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_2 * 4); + dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_2); + if (dma2[1].dmaisrfunc) + dma2[1].dmaisrfunc(dma2[1].dmaisrparam, isr); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 channel 3 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_3 * 4); + dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_3); + if (dma2[2].dmaisrfunc) + dma2[2].dmaisrfunc(dma2[2].dmaisrparam, isr); + + CH_IRQ_EPILOGUE(); +} + +#if defined(STM32F10X_CL) || defined(__DOXYGEN__) +/** + * @brief DMA2 channel 4 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_4 * 4); + dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); + if (dma2[3].dmaisrfunc) + dma2[3].dmaisrfunc(dma2[3].dmaisrparam, isr); + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief DMA2 channel 5 shared interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_5 * 4); + dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_5); + if (dma2[4].dmaisrfunc) + dma2[4].dmaisrfunc(dma2[4].dmaisrparam, isr); + + CH_IRQ_EPILOGUE(); +} + +#else /* !STM32F10X_CL */ +/** + * @brief DMA2 channels 4 and 5 shared interrupt handler. + * @note This IRQ is shared between DMA2 channels 4 and 5 so it is a + * bit less efficient because an extra check. + * + * @isr + */ +CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) { + uint32_t isr; + + CH_IRQ_PROLOGUE(); + + /* Check on channel 4.*/ + isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_5 * 4); + if (isr & DMA_ISR_GIF1) { + dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_5); + if (dma2[3].dmaisrfunc) + dma2[3].dmaisrfunc(dma2[3].dmaisrparam, isr); + } + + /* Check on channel 5.*/ + isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_4 * 4); + if (isr & DMA_ISR_GIF1) { + dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_5); + if (dma2[4].dmaisrfunc) + dma2[4].dmaisrfunc(dma2[4].dmaisrparam, isr); + } + + CH_IRQ_EPILOGUE(); +} +#endif /* !STM32F10X_CL */ +#endif /* STM32_HAS_DMA2 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA helper initialization. + * + * @init + */ +void dmaInit(void) { + int i; + + dmamsk1 = 0; + for (i = STM32_DMA_CHANNEL_7; i >= STM32_DMA_CHANNEL_1; i--) { + dmaDisableChannel(STM32_DMA1, i); + dma1[i].dmaisrfunc = NULL; + } + STM32_DMA1->IFCR = 0xFFFFFFFF; +#if STM32_HAS_DMA2 + dmamsk2 = 0; + for (i = STM32_DMA_CHANNEL_5; i >= STM32_DMA_CHANNEL_1; i--) { + dmaDisableChannel(STM32_DMA2, i); + dma2[i].dmaisrfunc = NULL; + } + STM32_DMA1->IFCR = 0xFFFFFFFF; +#endif +} + +/** + * @brief Allocates a DMA channel. + * @details The channel is allocated and, if required, the DMA clock enabled. + * Trying to allocate a channel already allocated is an illegal + * operation and is trapped if assertions are enabled. + * @pre The channel must not be already in use. + * @post The channel is allocated and the default ISR handler redirected + * to the specified function. + * @post The channel must be freed using @p dmaRelease() before it can + * be reused with another peripheral. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dma DMA controller id + * @param[in] channel requested channel id + * @param[in] func handling function pointer, can be @p NULL + * @param[in] param a parameter to be passed to the handling function + * @return The operation status. + * @retval FALSE operation successfully allocated. + * @retval TRUE the channel was already in use. + * + * @special + */ +void dmaAllocate(uint32_t dma, uint32_t channel, + stm32_dmaisr_t func, void *param) { + + chDbgCheck(func != NULL, "dmaAllocate"); + +#if STM32_HAS_DMA2 + switch (dma) { + case STM32_DMA1_ID: +#else + (void)dma; +#endif + /* Check if the channel is already taken.*/ + chDbgAssert((dmamsk1 & (1 << channel)) == 0, + "dmaAllocate(), #1", "already allocated"); + + /* If the DMA unit was idle then the clock is enabled.*/ + if (dmamsk1 == 0) { + RCC->AHBENR |= RCC_AHBENR_DMA1EN; + DMA1->IFCR = 0x0FFFFFFF; + } + + dmamsk1 |= 1 << channel; + dma1[channel].dmaisrfunc = func; + dma1[channel].dmaisrparam = param; +#if STM32_HAS_DMA2 + break; + case STM32_DMA2_ID: + /* Check if the channel is already taken.*/ + chDbgAssert((dmamsk2 & (1 << channel)) == 0, + "dmaAllocate(), #2", "already allocated"); + + /* If the DMA unit was idle then the clock is enabled.*/ + if (dmamsk2 == 0) { + RCC->AHBENR |= RCC_AHBENR_DMA2EN; + DMA2->IFCR = 0x0FFFFFFF; + } + + dmamsk2 |= 1 << channel; + dma2[channel].dmaisrfunc = func; + dma2[channel].dmaisrparam = param; + break; + } +#endif +} + +/** + * @brief Releases a DMA channel. + * @details The channel is freed and, if required, the DMA clock disabled. + * Trying to release a unallocated channel is an illegal operation + * and is trapped if assertions are enabled. + * @pre The channel must have been allocated using @p dmaRequest(). + * @post The channel is again available. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dma DMA controller id + * @param[in] channel requested channel id + * + * @special + */ +void dmaRelease(uint32_t dma, uint32_t channel) { + +#if STM32_HAS_DMA2 + switch (dma) { + case STM32_DMA1_ID: +#else + (void)dma; +#endif + /* Check if the channel is not taken.*/ + chDbgAssert((dmamsk1 & (1 << channel)) != 0, + "dmaRelease(), #1", "not allocated"); + + dma1[channel].dmaisrfunc = NULL; + dmamsk1 &= ~(1 << channel); + if (dmamsk1 == 0) + RCC->AHBENR &= ~RCC_AHBENR_DMA1EN; +#if STM32_HAS_DMA2 + break; + case STM32_DMA2_ID: + /* Check if the channel is not taken.*/ + chDbgAssert((dmamsk2 & (1 << channel)) != 0, + "dmaRelease(), #2", "not allocated"); + + dma2[channel].dmaisrfunc = NULL; + dmamsk2 &= ~(1 << channel); + if (dmamsk2 == 0) + RCC->AHBENR &= ~RCC_AHBENR_DMA2EN; + break; + } +#endif +} + +#endif /* STM32_DMA_REQUIRED */ + +/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/stm32_dma.h b/os/hal/platforms/STM32/DMAv1/stm32_dma.h new file mode 100644 index 000000000..66a2f8c69 --- /dev/null +++ b/os/hal/platforms/STM32/DMAv1/stm32_dma.h @@ -0,0 +1,280 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file stm32_dma.h + * @brief STM32 DMA helper driver header. + * @note This file requires definitions from the ST STM32 header file + * stm3232f10x.h. + * + * @addtogroup STM32_DMA + * @{ + */ + +#ifndef _STM32_DMA_H_ +#define _STM32_DMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** @brief DMA1 identifier.*/ +#define STM32_DMA1_ID 0 + +/** @brief DMA2 identifier.*/ +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) +#define STM32_DMA2_ID 1 +#endif + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief STM32 DMA channel memory structure type. + */ +typedef struct { + volatile uint32_t CCR; + volatile uint32_t CNDTR; + volatile uint32_t CPAR; + volatile uint32_t CMAR; + volatile uint32_t dummy; +} stm32_dma_channel_t; + +/** + * @brief STM32 DMA subsystem memory structure type. + * @note This structure has been redefined here because it is convenient to + * have the channels organized as an array, the ST header does not + * do that. + */ +typedef struct { + volatile uint32_t ISR; + volatile uint32_t IFCR; + stm32_dma_channel_t channels[7]; +} stm32_dma_t; + +/** + * @brief STM32 DMA ISR function type. + * + * @param[in] p parameter for the registered function + * @param[in] flags pre-shifted content of the ISR register + */ +typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** DMA1 registers block numeric address.*/ +#define STM32_DMA1_BASE (AHBPERIPH_BASE + 0x0000) +/** Pointer to the DMA1 registers block.*/ +#define STM32_DMA1 ((stm32_dma_t *)STM32_DMA1_BASE) +/** Pointer to the DMA1 channel 1 registers block.*/ +#define STM32_DMA1_CH1 (&STM32_DMA1->channels[0]) +/** Pointer to the DMA1 channel 2 registers block.*/ +#define STM32_DMA1_CH2 (&STM32_DMA1->channels[1]) +/** Pointer to the DMA1 channel 3 registers block.*/ +#define STM32_DMA1_CH3 (&STM32_DMA1->channels[2]) +/** Pointer to the DMA1 channel 4 registers block.*/ +#define STM32_DMA1_CH4 (&STM32_DMA1->channels[3]) +/** Pointer to the DMA1 channel 5 registers block.*/ +#define STM32_DMA1_CH5 (&STM32_DMA1->channels[4]) +/** Pointer to the DMA1 channel 6 registers block.*/ +#define STM32_DMA1_CH6 (&STM32_DMA1->channels[5]) +/** Pointer to the DMA1 channel 7 registers block.*/ +#define STM32_DMA1_CH7 (&STM32_DMA1->channels[6]) + +#if STM32_HAS_DMA2 || defined(__DOXYGEN__) +/** DMA2 registers block numeric address.*/ +#define STM32_DMA2_BASE (AHBPERIPH_BASE + 0x0400) +/** Pointer to the DMA2 registers block.*/ +#define STM32_DMA2 ((stm32_dma_t *)STM32_DMA2_BASE) +/** Pointer to the DMA2 channel 1 registers block.*/ +#define STM32_DMA2_CH1 (&STM32_DMA2->channels[0]) +/** Pointer to the DMA2 channel 2 registers block.*/ +#define STM32_DMA2_CH2 (&STM32_DMA2->channels[1]) +/** Pointer to the DMA2 channel 3 registers block.*/ +#define STM32_DMA2_CH3 (&STM32_DMA2->channels[2]) +/** Pointer to the DMA2 channel 4 registers block.*/ +#define STM32_DMA2_CH4 (&STM32_DMA2->channels[3]) +/** Pointer to the DMA2 channel 5 registers block.*/ +#define STM32_DMA2_CH5 (&STM32_DMA2->channels[4]) +#endif + +#define STM32_DMA_CHANNEL_1 0 /**< @brief DMA channel 1. */ +#define STM32_DMA_CHANNEL_2 1 /**< @brief DMA channel 2. */ +#define STM32_DMA_CHANNEL_3 2 /**< @brief DMA channel 3. */ +#define STM32_DMA_CHANNEL_4 3 /**< @brief DMA channel 4. */ +#define STM32_DMA_CHANNEL_5 4 /**< @brief DMA channel 5. */ +#define STM32_DMA_CHANNEL_6 5 /**< @brief DMA channel 6. */ +#define STM32_DMA_CHANNEL_7 6 /**< @brief DMA channel 7. */ + +/** + * @brief Associates a peripheral data register to a DMA channel. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmachp dmachp to a stm32_dma_channel_t structure + * @param[in] cpar value to be written in the CPAR register + * + * @special + */ +#define dmaChannelSetPeripheral(dmachp, cpar) { \ + (dmachp)->CPAR = (uint32_t)(cpar); \ +} + +/** + * @brief DMA channel setup by channel pointer. + * @note This macro does not change the CPAR register because that register + * value does not change frequently, it usually points to a peripheral + * data register. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmachp dmachp to a stm32_dma_channel_t structure + * @param[in] cndtr value to be written in the CNDTR register + * @param[in] cmar value to be written in the CMAR register + * @param[in] ccr value to be written in the CCR register + * + * @special + */ +#define dmaChannelSetup(dmachp, cndtr, cmar, ccr) { \ + (dmachp)->CNDTR = (uint32_t)(cndtr); \ + (dmachp)->CMAR = (uint32_t)(cmar); \ + (dmachp)->CCR = (uint32_t)(ccr); \ +} + +/** + * @brief DMA channel enable by channel pointer. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmachp dmachp to a stm32_dma_channel_t structure + * + * @special + */ +#define dmaChannelEnable(dmachp) { \ + (dmachp)->CCR |= DMA_CCR1_EN; \ +} + + +/** + * @brief DMA channel disable by channel pointer. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmachp dmachp to a stm32_dma_channel_t structure + * + * @special + */ +#define dmaChannelDisable(dmachp) { \ + (dmachp)->CCR = 0; \ +} + +/** + * @brief DMA channel setup by channel ID. + * @note This macro does not change the CPAR register because that register + * value does not change frequently, it usually points to a peripheral + * data register. + * @note Channels are numbered from 0 to 6, use the appropriate macro + * as parameter. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmap pointer to a stm32_dma_t structure + * @param[in] ch channel number + * @param[in] cndtr value to be written in the CNDTR register + * @param[in] cmar value to be written in the CMAR register + * @param[in] ccr value to be written in the CCR register + * + * @special + */ +#define dmaSetupChannel(dmap, ch, cndtr, cmar, ccr) { \ + dmaChannelSetup(&(dmap)->channels[ch], (cndtr), (cmar), (ccr)); \ +} + +/** + * @brief DMA channel enable by channel ID. + * @note Channels are numbered from 0 to 6, use the appropriate macro + * as parameter. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmap pointer to a stm32_dma_t structure + * @param[in] ch channel number + * + * @special + */ +#define dmaEnableChannel(dmap, ch) { \ + dmaChannelEnable(&(dmap)->channels[ch]); \ +} + +/** + * @brief DMA channel disable by channel ID. + * @note Channels are numbered from 0 to 6, use the appropriate macro + * as parameter. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmap pointer to a stm32_dma_t structure + * @param[in] ch channel number + * + * @special + */ +#define dmaDisableChannel(dmap, ch) { \ + dmaChannelDisable(&(dmap)->channels[ch]); \ +} + +/** + * @brief DMA channel interrupt sources clear. + * @details Sets the appropriate CGIF bit into the IFCR register in order to + * withdraw all the pending interrupt bits from the ISR register. + * @note Channels are numbered from 0 to 6, use the appropriate macro + * as parameter. + * @note This function can be invoked in both ISR or thread context. + * + * @param[in] dmap pointer to a stm32_dma_t structure + * @param[in] ch channel number + * + * @special + */ +#define dmaClearChannel(dmap, ch){ \ + (dmap)->IFCR = 1 << ((ch) * 4); \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void dmaInit(void); + void dmaAllocate(uint32_t dma, uint32_t channel, + stm32_dmaisr_t func, void *param); + void dmaRelease(uint32_t dma, uint32_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_DMA_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/uart_lld.c b/os/hal/platforms/STM32/DMAv1/uart_lld.c new file mode 100644 index 000000000..e2f306302 --- /dev/null +++ b/os/hal/platforms/STM32/DMAv1/uart_lld.c @@ -0,0 +1,559 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/uart_lld.c + * @brief STM32 low level UART driver code. + * + * @addtogroup UART + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief USART1 UART driver identifier.*/ +#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) +UARTDriver UARTD1; +#endif + +/** @brief USART2 UART driver identifier.*/ +#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) +UARTDriver UARTD2; +#endif + +/** @brief USART3 UART driver identifier.*/ +#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) +UARTDriver UARTD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Status bits translation. + * + * @param[in] sr USART SR register value + * + * @return The error flags. + */ +static uartflags_t translate_errors(uint16_t sr) { + uartflags_t sts = 0; + + if (sr & USART_SR_ORE) + sts |= UART_OVERRUN_ERROR; + if (sr & USART_SR_PE) + sts |= UART_PARITY_ERROR; + if (sr & USART_SR_FE) + sts |= UART_FRAMING_ERROR; + if (sr & USART_SR_NE) + sts |= UART_NOISE_ERROR; + if (sr & USART_SR_LBD) + sts |= UART_BREAK_DETECTED; + return sts; +} + +/** + * @brief Puts the receiver in the UART_RX_IDLE state. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void set_rx_idle_loop(UARTDriver *uartp) { + uint32_t ccr; + + /* RX DMA channel preparation, if the char callback is defined then the + TCIE interrupt is enabled too.*/ + if (uartp->config->rxchar_cb == NULL) + ccr = DMA_CCR1_CIRC | DMA_CCR1_TEIE; + else + ccr = DMA_CCR1_CIRC | DMA_CCR1_TEIE | DMA_CCR1_TCIE; + dmaSetupChannel(uartp->dmap, uartp->dmarx, 1, + &uartp->rxbuf, uartp->dmaccr | ccr); + dmaEnableChannel(uartp->dmap, uartp->dmarx); +} + +/** + * @brief USART de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void usart_stop(UARTDriver *uartp) { + + /* Stops RX and TX DMA channels.*/ + dmaDisableChannel(uartp->dmap, uartp->dmarx); + dmaDisableChannel(uartp->dmap, uartp->dmatx); + dmaClearChannel(uartp->dmap, uartp->dmarx); + dmaClearChannel(uartp->dmap, uartp->dmatx); + + /* Stops USART operations.*/ + uartp->usart->CR1 = 0; + uartp->usart->CR2 = 0; + uartp->usart->CR3 = 0; +} + +/** + * @brief USART initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void usart_start(UARTDriver *uartp) { + uint16_t cr1; + USART_TypeDef *u = uartp->usart; + + /* Defensive programming, starting from a clean state.*/ + usart_stop(uartp); + + /* Baud rate setting.*/ + if (uartp->usart == USART1) + u->BRR = STM32_PCLK2 / uartp->config->speed; + else + u->BRR = STM32_PCLK1 / uartp->config->speed; + + /* Resetting eventual pending status flags.*/ + (void)u->SR; /* SR reset step 1.*/ + (void)u->DR; /* SR reset step 2.*/ + u->SR = 0; + + /* Note that some bits are enforced because required for correct driver + operations.*/ + if (uartp->config->txend2_cb == NULL) + cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE; + else + cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE | + USART_CR1_TCIE; + u->CR1 = uartp->config->cr1 | cr1; + u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE; + u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR | + USART_CR3_EIE; + + /* Starting the receiver idle loop.*/ + set_rx_idle_loop(uartp); +} + +/** + * @brief RX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_UART_DMA_ERROR_HOOK) + if ((flags & DMA_ISR_TEIF1) != 0) { + STM32_UART_DMA_ERROR_HOOK(uartp); + } +#else + (void)flags; +#endif + + if (uartp->rxstate == UART_RX_IDLE) { + /* Receiver in idle state, a callback is generated, if enabled, for each + received character and then the driver stays in the same state.*/ + if (uartp->config->rxchar_cb != NULL) + uartp->config->rxchar_cb(uartp, uartp->rxbuf); + } + else { + /* Receiver in active state, a callback is generated, if enabled, after + a completed transfer.*/ + dmaDisableChannel(uartp->dmap, uartp->dmarx); + uartp->rxstate = UART_RX_COMPLETE; + if (uartp->config->rxend_cb != NULL) + uartp->config->rxend_cb(uartp); + /* If the callback didn't explicitly change state then the receiver + automatically returns to the idle state.*/ + if (uartp->rxstate == UART_RX_COMPLETE) { + uartp->rxstate = UART_RX_IDLE; + set_rx_idle_loop(uartp); + } + } +} + +/** + * @brief TX DMA common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] flags pre-shifted content of the ISR register + */ +static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { + + /* DMA errors handling.*/ +#if defined(STM32_UART_DMA_ERROR_HOOK) + if ((flags & DMA_ISR_TEIF1) != 0) { + STM32_UART_DMA_ERROR_HOOK(uartp); + } +#else + (void)flags; +#endif + + dmaDisableChannel(uartp->dmap, uartp->dmatx); + /* A callback is generated, if enabled, after a completed transfer.*/ + uartp->txstate = UART_TX_COMPLETE; + if (uartp->config->txend1_cb != NULL) + uartp->config->txend1_cb(uartp); + /* If the callback didn't explicitly change state then the transmitter + automatically returns to the idle state.*/ + if (uartp->txstate == UART_TX_COMPLETE) + uartp->txstate = UART_TX_IDLE; +} + +/** + * @brief USART common service routine. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +static void serve_usart_irq(UARTDriver *uartp) { + uint16_t sr; + USART_TypeDef *u = uartp->usart; + + sr = u->SR; /* SR reset step 1.*/ + (void)u->DR; /* SR reset step 2.*/ + if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE | + USART_SR_FE | USART_SR_PE)) { + u->SR = ~USART_SR_LBD; + if (uartp->config->rxerr_cb != NULL) + uartp->config->rxerr_cb(uartp, translate_errors(sr)); + } + if (sr & USART_SR_TC) { + u->SR = ~USART_SR_TC; + /* End of transmission, a callback is generated.*/ + if (uartp->config->txend2_cb != NULL) + uartp->config->txend2_cb(uartp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) +/** + * @brief USART1 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART1_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART1 */ + +#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) +/** + * @brief USART2 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART2_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART2 */ + +#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) +/** + * @brief USART3 IRQ handler. + * + * @isr + */ +CH_IRQ_HANDLER(USART3_IRQHandler) { + + CH_IRQ_PROLOGUE(); + + serve_usart_irq(&UARTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM32_UART_USE_USART3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level UART driver initialization. + * + * @notapi + */ +void uart_lld_init(void) { + +#if STM32_UART_USE_USART1 + uartObjectInit(&UARTD1); + UARTD1.usart = USART1; + UARTD1.dmap = STM32_DMA1; + UARTD1.dmarx = STM32_DMA_CHANNEL_5; + UARTD1.dmatx = STM32_DMA_CHANNEL_4; + UARTD1.dmaccr = 0; +#endif + +#if STM32_UART_USE_USART2 + uartObjectInit(&UARTD2); + UARTD2.usart = USART2; + UARTD2.dmap = STM32_DMA1; + UARTD2.dmarx = STM32_DMA_CHANNEL_6; + UARTD2.dmatx = STM32_DMA_CHANNEL_7; + UARTD2.dmaccr = 0; +#endif + +#if STM32_UART_USE_USART3 + uartObjectInit(&UARTD3); + UARTD3.usart = USART3; + UARTD3.dmap = STM32_DMA1; + UARTD3.dmarx = STM32_DMA_CHANNEL_3; + UARTD3.dmatx = STM32_DMA_CHANNEL_2; + UARTD3.dmaccr = 0; +#endif +} + +/** + * @brief Configures and activates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_start(UARTDriver *uartp) { + + if (uartp->state == UART_STOP) { +#if STM32_UART_USE_USART1 + if (&UARTD1 == uartp) { + /* Note, the DMA must be enabled before the IRQs.*/ + dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_4, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); + dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_5, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); + NVICEnableVector(USART1_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); + NVICEnableVector(DMA1_Channel4_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); + NVICEnableVector(DMA1_Channel5_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); + RCC->APB2ENR |= RCC_APB2ENR_USART1EN; + } +#endif + +#if STM32_UART_USE_USART2 + if (&UARTD2 == uartp) { + /* Note, the DMA must be enabled before the IRQs.*/ + dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_6, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); + dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_7, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); + NVICEnableVector(USART2_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); + NVICEnableVector(DMA1_Channel6_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); + NVICEnableVector(DMA1_Channel7_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); + RCC->APB1ENR |= RCC_APB1ENR_USART2EN; + } +#endif + +#if STM32_UART_USE_USART3 + if (&UARTD3 == uartp) { + /* Note, the DMA must be enabled before the IRQs.*/ + dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_2, + (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); + dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_3, + (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); + NVICEnableVector(USART3_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); + NVICEnableVector(DMA1_Channel2_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); + NVICEnableVector(DMA1_Channel3_IRQn, + CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); + RCC->APB1ENR |= RCC_APB1ENR_USART3EN; + } +#endif + + /* Static DMA setup, the transfer size depends on the USART settings, + it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ + uartp->dmaccr = STM32_UART_USART1_DMA_PRIORITY << 12; + if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) + uartp->dmaccr |= DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0; + dmaChannelSetPeripheral(&uartp->dmap->channels[uartp->dmarx], + &uartp->usart->DR); + dmaChannelSetPeripheral(&uartp->dmap->channels[uartp->dmatx], + &uartp->usart->DR); + uartp->rxbuf = 0; + } + + uartp->rxstate = UART_RX_IDLE; + uartp->txstate = UART_TX_IDLE; + usart_start(uartp); +} + +/** + * @brief Deactivates the UART peripheral. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @notapi + */ +void uart_lld_stop(UARTDriver *uartp) { + + if (uartp->state == UART_READY) { + usart_stop(uartp); + +#if STM32_UART_USE_USART1 + if (&UARTD1 == uartp) { + NVICDisableVector(USART1_IRQn); + NVICDisableVector(DMA1_Channel4_IRQn); + NVICDisableVector(DMA1_Channel5_IRQn); + dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_4); + dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_5); + RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN; + return; + } +#endif + +#if STM32_UART_USE_USART2 + if (&UARTD2 == uartp) { + NVICDisableVector(USART2_IRQn); + NVICDisableVector(DMA1_Channel6_IRQn); + NVICDisableVector(DMA1_Channel7_IRQn); + dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_6); + dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_7); + RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN; + return; + } +#endif + +#if STM32_UART_USE_USART3 + if (&UARTD3 == uartp) { + NVICDisableVector(USART3_IRQn); + NVICDisableVector(DMA1_Channel2_IRQn); + NVICDisableVector(DMA1_Channel3_IRQn); + dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_2); + dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_3); + RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN; + return; + } +#endif + } +} + +/** + * @brief Starts a transmission on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { + + /* TX DMA channel preparation and start.*/ + dmaSetupChannel(uartp->dmap, uartp->dmatx, n, txbuf, + uartp->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC | + DMA_CCR1_TEIE | DMA_CCR1_TCIE); + dmaEnableChannel(uartp->dmap, uartp->dmatx); +} + +/** + * @brief Stops any ongoing transmission. + * @note Stopping a transmission also suppresses the transmission callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not transmitted by the + * stopped transmit operation. + * + * @notapi + */ +size_t uart_lld_stop_send(UARTDriver *uartp) { + + dmaDisableChannel(uartp->dmap, uartp->dmatx); + dmaClearChannel(uartp->dmap, uartp->dmatx); + return (size_t)uartp->dmap->channels[uartp->dmatx].CNDTR; +} + +/** + * @brief Starts a receive operation on the UART peripheral. + * @note The buffers are organized as uint8_t arrays for data sizes below + * or equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] n number of data frames to send + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { + + /* Stopping previous activity (idle state).*/ + dmaDisableChannel(uartp->dmap, uartp->dmarx); + dmaClearChannel(uartp->dmap, uartp->dmarx); + + /* RX DMA channel preparation and start.*/ + dmaSetupChannel(uartp->dmap, uartp->dmarx, n, rxbuf, + uartp->dmaccr | DMA_CCR1_MINC | + DMA_CCR1_TEIE | DMA_CCR1_TCIE); + dmaEnableChannel(uartp->dmap, uartp->dmarx); +} + +/** + * @brief Stops any ongoing receive operation. + * @note Stopping a receive operation also suppresses the receive callbacks. + * + * @param[in] uartp pointer to the @p UARTDriver object + * + * @return The number of data frames not received by the + * stopped receive operation. + * + * @notapi + */ +size_t uart_lld_stop_receive(UARTDriver *uartp) { + size_t n; + + dmaDisableChannel(uartp->dmap, uartp->dmarx); + dmaClearChannel(uartp->dmap, uartp->dmarx); + n = (size_t)uartp->dmap->channels[uartp->dmarx].CNDTR; + set_rx_idle_loop(uartp); + return n; +} + +#endif /* HAL_USE_UART */ + +/** @} */ diff --git a/os/hal/platforms/STM32/DMAv1/uart_lld.h b/os/hal/platforms/STM32/DMAv1/uart_lld.h new file mode 100644 index 000000000..9321df85c --- /dev/null +++ b/os/hal/platforms/STM32/DMAv1/uart_lld.h @@ -0,0 +1,322 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32/uart_lld.h + * @brief STM32 low level UART driver header. + * + * @addtogroup UART + * @{ + */ + +#ifndef _UART_LLD_H_ +#define _UART_LLD_H_ + +#if HAL_USE_UART || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART driver on USART1 enable switch. + * @details If set to @p TRUE the support for USART1 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART1 TRUE +#endif + +/** + * @brief UART driver on USART2 enable switch. + * @details If set to @p TRUE the support for USART2 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART2 TRUE +#endif + +/** + * @brief UART driver on USART3 enable switch. + * @details If set to @p TRUE the support for USART3 is included. + * @note The default is @p FALSE. + */ +#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__) +#define STM32_UART_USE_USART3 TRUE +#endif + +/** + * @brief USART1 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART2 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART3 interrupt priority level setting. + */ +#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#endif + +/** + * @brief USART1 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART1_DMA_PRIORITY 0 +#endif + +/** + * @brief USART2 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART2_DMA_PRIORITY 0 +#endif +/** + * @brief USART3 DMA priority (0..3|lowest..highest). + * @note The priority level is used for both the TX and RX DMA channels but + * because of the channels ordering the RX channel has always priority + * over the TX channel. + */ +#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_UART_USART3_DMA_PRIORITY 0 +#endif + +/** + * @brief USART1 DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 && !STM32_HAS_USART1 +#error "USART1 not present in the selected device" +#endif + +#if STM32_UART_USE_USART2 && !STM32_HAS_USART2 +#error "USART2 not present in the selected device" +#endif + +#if STM32_UART_USE_USART3 && !STM32_HAS_USART3 +#error "USART3 not present in the selected device" +#endif + +#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \ + !STM32_UART_USE_USART3 +#error "UART driver activated but no USART/UART peripheral assigned" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief UART driver condition flags type. + */ +typedef uint32_t uartflags_t; + +/** + * @brief Structure representing an UART driver. + */ +typedef struct UARTDriver UARTDriver; + +/** + * @brief Generic UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + */ +typedef void (*uartcb_t)(UARTDriver *uartp); + +/** + * @brief Character received UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] c received character + */ +typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); + +/** + * @brief Receive error UART notification callback type. + * + * @param[in] uartp pointer to the @p UARTDriver object + * @param[in] e receive error mask + */ +typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief End of transmission buffer callback. + */ + uartcb_t txend1_cb; + /** + * @brief Physical end of transmission callback. + */ + uartcb_t txend2_cb; + /** + * @brief Receive buffer filled callback. + */ + uartcb_t rxend_cb; + /** + * @brief Character received while out if the @p UART_RECEIVE state. + */ + uartccb_t rxchar_cb; + /** + * @brief Receive error callback. + */ + uartecb_t rxerr_cb; + /* End of the mandatory fields.*/ + /** + * @brief Bit rate. + */ + uint32_t speed; + /** + * @brief Initialization value for the CR1 register. + */ + uint16_t cr1; + /** + * @brief Initialization value for the CR2 register. + */ + uint16_t cr2; + /** + * @brief Initialization value for the CR3 register. + */ + uint16_t cr3; +} UARTConfig; + +/** + * @brief Structure representing an UART driver. + */ +struct UARTDriver { + /** + * @brief Driver state. + */ + uartstate_t state; + /** + * @brief Transmitter state. + */ + uarttxstate_t txstate; + /** + * @brief Receiver state. + */ + uartrxstate_t rxstate; + /** + * @brief Current configuration data. + */ + const UARTConfig *config; +#if defined(UART_DRIVER_EXT_FIELDS) + UART_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the USART registers block. + */ + USART_TypeDef *usart; + /** + * @brief Pointer to the DMA registers block. + */ + stm32_dma_t *dmap; + /** + * @brief DMA priority bit mask. + */ + uint32_t dmaccr; + /** + * @brief Receive DMA channel. + */ + uint8_t dmarx; + /** + * @brief Transmit DMA channel. + */ + uint8_t dmatx; + /** + * @brief Default receive buffer while into @p UART_RX_IDLE state. + */ + volatile uint16_t rxbuf; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__) +extern UARTDriver UARTD1; +#endif + +#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__) +extern UARTDriver UARTD2; +#endif + +#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__) +extern UARTDriver UARTD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void uart_lld_init(void); + void uart_lld_start(UARTDriver *uartp); + void uart_lld_stop(UARTDriver *uartp); + void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); + size_t uart_lld_stop_send(UARTDriver *uartp); + void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); + size_t uart_lld_stop_receive(UARTDriver *uartp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_UART */ + +#endif /* _UART_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM32/adc_lld.c b/os/hal/platforms/STM32/adc_lld.c deleted file mode 100644 index 8a8027e55..000000000 --- a/os/hal/platforms/STM32/adc_lld.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/adc_lld.c - * @brief STM32 ADC subsystem low level driver source. - * - * @addtogroup ADC - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief ADC1 driver identifier.*/ -#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__) -ADCDriver ADCD1; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared ADC DMA ISR service routine. - * - * @param[in] adcp pointer to the @p ADCDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_ADC_DMA_ERROR_HOOK) - if ((flags & DMA_ISR_TEIF1) != 0) { - STM32_ADC_DMA_ERROR_HOOK(spip); - } -#else - (void)flags; -#endif - if ((flags & DMA_ISR_HTIF1) != 0) { - /* Half transfer processing.*/ - _adc_isr_half_code(adcp); - } - if ((flags & DMA_ISR_TCIF1) != 0) { - /* Transfer complete processing.*/ - _adc_isr_full_code(adcp); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ADC driver initialization. - * - * @notapi - */ -void adc_lld_init(void) { - -#if STM32_ADC_USE_ADC1 - /* Driver initialization.*/ - adcObjectInit(&ADCD1); - ADCD1.adc = ADC1; - ADCD1.dmachp = STM32_DMA1_CH1; - ADCD1.dmaccr = (STM32_ADC_ADC1_DMA_PRIORITY << 12) | - DMA_CCR1_EN | DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0 | - DMA_CCR1_MINC | DMA_CCR1_TCIE | DMA_CCR1_TEIE; - - /* Temporary activation.*/ - RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; - ADC1->CR1 = 0; - ADC1->CR2 = ADC_CR2_ADON; - - /* Reset calibration just to be safe.*/ - ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_RSTCAL; - while ((ADC1->CR2 & ADC_CR2_RSTCAL) != 0) - ; - - /* Calibration.*/ - ADC1->CR2 = ADC_CR2_ADON | ADC_CR2_CAL; - while ((ADC1->CR2 & ADC_CR2_CAL) != 0) - ; - - /* Return the ADC in low power mode.*/ - ADC1->CR2 = 0; - RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN; -#endif -} - -/** - * @brief Configures and activates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start(ADCDriver *adcp) { - - /* If in stopped state then enables the ADC and DMA clocks.*/ - if (adcp->state == ADC_STOP) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_1, - (stm32_dmaisr_t)adc_lld_serve_rx_interrupt, (void *)adcp); - NVICEnableVector(DMA1_Channel1_IRQn, - CORTEX_PRIORITY_MASK(STM32_ADC_ADC1_IRQ_PRIORITY)); - dmaChannelSetPeripheral(adcp->dmachp, &ADC1->DR); - RCC->APB2ENR |= RCC_APB2ENR_ADC1EN; - } -#endif - - /* ADC setup, the calibration procedure has already been performed - during initialization.*/ - adcp->adc->CR1 = ADC_CR1_SCAN; - adcp->adc->CR2 = 0; - } -} - -/** - * @brief Deactivates the ADC peripheral. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop(ADCDriver *adcp) { - - /* If in ready state then disables the ADC clock.*/ - if (adcp->state == ADC_READY) { -#if STM32_ADC_USE_ADC1 - if (&ADCD1 == adcp) { - ADC1->CR1 = 0; - ADC1->CR2 = 0; - NVICDisableVector(DMA1_Channel1_IRQn); - dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_1); - RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN; - } -#endif - } -} - -/** - * @brief Starts an ADC conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_start_conversion(ADCDriver *adcp) { - uint32_t ccr, n; - const ADCConversionGroup *grpp = adcp->grpp; - - /* DMA setup.*/ - ccr = adcp->dmaccr; - if (grpp->circular) - ccr |= DMA_CCR1_CIRC; - if (adcp->depth > 1) { - /* If the buffer depth is greater than one then the half transfer interrupt - interrupt is enabled in order to allows streaming processing.*/ - ccr |= DMA_CCR1_HTIE; - n = (uint32_t)grpp->num_channels * (uint32_t)adcp->depth; - } - else - n = (uint32_t)grpp->num_channels; - dmaChannelSetup(adcp->dmachp, n, adcp->samples, ccr); - - /* ADC setup.*/ - adcp->adc->CR1 = grpp->cr1 | ADC_CR1_SCAN; - adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | - ADC_CR2_CONT | ADC_CR2_ADON; - adcp->adc->SMPR1 = grpp->smpr1; - adcp->adc->SMPR2 = grpp->smpr2; - adcp->adc->SQR1 = grpp->sqr1; - adcp->adc->SQR2 = grpp->sqr2; - adcp->adc->SQR3 = grpp->sqr3; - - /* ADC start by writing ADC_CR2_ADON a second time.*/ - adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA | - ADC_CR2_CONT | ADC_CR2_ADON; -} - -/** - * @brief Stops an ongoing conversion. - * - * @param[in] adcp pointer to the @p ADCDriver object - * - * @notapi - */ -void adc_lld_stop_conversion(ADCDriver *adcp) { - - dmaChannelDisable(adcp->dmachp); - adcp->adc->CR2 = 0; -} - -#endif /* HAL_USE_ADC */ - -/** @} */ diff --git a/os/hal/platforms/STM32/adc_lld.h b/os/hal/platforms/STM32/adc_lld.h deleted file mode 100644 index ce93e60ed..000000000 --- a/os/hal/platforms/STM32/adc_lld.h +++ /dev/null @@ -1,354 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/adc_lld.h - * @brief STM32 ADC subsystem low level driver header. - * - * @addtogroup ADC - * @{ - */ - -#ifndef _ADC_LLD_H_ -#define _ADC_LLD_H_ - -#if HAL_USE_ADC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define ADC_CR2_EXTSEL_SRC(n) ((n) << 17) /**< @brief Trigger source. */ -#define ADC_CR2_EXTSEL_SWSTART (7 << 17) /**< @brief Software trigger. */ - -#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */ -#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */ -#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */ -#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */ -#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */ -#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */ -#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */ -#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */ -#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */ -#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */ -#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */ -#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */ -#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */ -#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */ -#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */ -#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */ -#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.*/ -#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference. */ - -#define ADC_SAMPLE_1P5 0 /**< @brief 1.5 cycles sampling time. */ -#define ADC_SAMPLE_7P5 1 /**< @brief 7.5 cycles sampling time. */ -#define ADC_SAMPLE_13P5 2 /**< @brief 13.5 cycles sampling time. */ -#define ADC_SAMPLE_28P5 3 /**< @brief 28.5 cycles sampling time. */ -#define ADC_SAMPLE_41P5 4 /**< @brief 41.5 cycles sampling time. */ -#define ADC_SAMPLE_55P5 5 /**< @brief 55.5 cycles sampling time. */ -#define ADC_SAMPLE_71P5 6 /**< @brief 71.5 cycles sampling time. */ -#define ADC_SAMPLE_239P5 7 /**< @brief 239.5 cycles sampling time. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief ADC1 driver enable switch. - * @details If set to @p TRUE the support for ADC1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__) -#define STM32_ADC_USE_ADC1 TRUE -#endif - -/** - * @brief ADC1 DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_DMA_PRIORITY 2 -#endif - -/** - * @brief ADC1 interrupt priority level setting. - */ -#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_ADC_ADC1_IRQ_PRIORITY 5 -#endif - -/** - * @brief ADC DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_ADC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_ADC_DMA_ERROR_HOOK(adcp) chSysHalt() -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1 -#error "ADC1 not present in the selected device" -#endif - -#if !STM32_ADC_USE_ADC1 -#error "ADC driver activated but no ADC peripheral assigned" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief ADC sample data type. - */ -typedef uint16_t adcsample_t; - -/** - * @brief Channels number in a conversion group. - */ -typedef uint16_t adc_channels_num_t; - -/** - * @brief Type of a structure representing an ADC driver. - */ -typedef struct ADCDriver ADCDriver; - -/** - * @brief ADC notification callback type. - * - * @param[in] adcp pointer to the @p ADCDriver object triggering the - * callback - * @param[in] buffer pointer to the most recent samples data - * @param[in] n number of buffer rows available starting from @p buffer - */ -typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n); - -/** - * @brief Conversion group configuration structure. - * @details This implementation-dependent structure describes a conversion - * operation. - * @note The use of this configuration structure requires knowledge of - * STM32 ADC cell registers interface, please refer to the STM32 - * reference manual for details. - */ -typedef struct { - /** - * @brief Enables the circular buffer mode for the group. - */ - bool_t circular; - /** - * @brief Number of the analog channels belonging to the conversion group. - */ - adc_channels_num_t num_channels; - /** - * @brief Callback function associated to the group or @p NULL. - */ - adccallback_t end_cb; - /* End of the mandatory fields.*/ - /** - * @brief ADC CR1 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR1_SCAN that is enforced inside the driver. - */ - uint32_t cr1; - /** - * @brief ADC CR2 register initialization data. - * @note All the required bits must be defined into this field except - * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are - * enforced inside the driver. - */ - uint32_t cr2; - /** - * @brief ADC SMPR1 register initialization data. - * @details In this field must be specified the sample times for channels - * 10...17. - */ - uint32_t smpr1; - /** - * @brief ADC SMPR2 register initialization data. - * @details In this field must be specified the sample times for channels - * 0...9. - */ - uint32_t smpr2; - /** - * @brief ADC SQR1 register initialization data. - * @details Conversion group sequence 13...16 + sequence length. - */ - uint32_t sqr1; - /** - * @brief ADC SQR2 register initialization data. - * @details Conversion group sequence 7...12. - */ - uint32_t sqr2; - /** - * @brief ADC SQR3 register initialization data. - * @details Conversion group sequence 0...6. - */ - uint32_t sqr3; -} ADCConversionGroup; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - uint32_t dummy; -} ADCConfig; - -/** - * @brief Structure representing an ADC driver. - */ -struct ADCDriver { - /** - * @brief Driver state. - */ - adcstate_t state; - /** - * @brief Current configuration data. - */ - const ADCConfig *config; - /** - * @brief Current samples buffer pointer or @p NULL. - */ - adcsample_t *samples; - /** - * @brief Current samples buffer depth or @p 0. - */ - size_t depth; - /** - * @brief Current conversion group pointer or @p NULL. - */ - const ADCConversionGroup *grpp; -#if ADC_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - Thread *thread; -#endif -#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the peripheral. - */ - Mutex mutex; -#elif CH_USE_SEMAPHORES - Semaphore semaphore; -#endif -#endif /* ADC_USE_MUTUAL_EXCLUSION */ -#if defined(ADC_DRIVER_EXT_FIELDS) - ADC_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the ADCx registers block. - */ - ADC_TypeDef *adc; - /** - * @brief Pointer to the DMA registers block. - */ - stm32_dma_channel_t *dmachp; - /** - * @brief DMA CCR register bit mask. - */ - uint32_t dmaccr; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Number of channels in a conversion sequence. - */ -#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20) - -#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */ -#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */ -#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */ -#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */ -#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */ -#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */ - -#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */ -#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */ -#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */ -#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/ -#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/ -#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/ - -#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/ -#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/ -#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/ -#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/ - -#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */ -#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */ -#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */ -#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */ -#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */ -#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */ -#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */ -#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */ -#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */ -#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */ - -#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */ -#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */ -#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */ -#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */ -#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */ -#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */ -#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor - sampling time. */ -#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference - sampling time. */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__) -extern ADCDriver ADCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void adc_lld_init(void); - void adc_lld_start(ADCDriver *adcp); - void adc_lld_stop(ADCDriver *adcp); - void adc_lld_start_conversion(ADCDriver *adcp); - void adc_lld_stop_conversion(ADCDriver *adcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_ADC */ - -#endif /* _ADC_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c deleted file mode 100644 index a88ad53fa..000000000 --- a/os/hal/platforms/STM32/sdc_lld.c +++ /dev/null @@ -1,722 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/sdc_lld.c - * @brief STM32 SDC subsystem low level driver source. - * - * @addtogroup SDC - * @{ - */ - -#include - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief SDCD1 driver identifier.*/ -SDCDriver SDCD1; - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -#if STM32_SDC_UNALIGNED_SUPPORT -/** - * @brief Buffer for temporary storage during unaligned transfers. - */ -static union { - uint32_t alignment; - uint8_t buf[SDC_BLOCK_SIZE]; -} u; -#endif - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Reads one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer, it must be aligned to - * four bytes boundary - * @param[in] n number of blocks to read - * @return The operation status. - * @retval FALSE operation succeeded, the requested blocks have been - * read. - * @retval TRUE operation failed, the state of the buffer is uncertain. - * - * @notapi - */ -static bool_t sdc_lld_read_multiple(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n) { - uint32_t resp[1]; - - /* Checks for errors and waits for the card to be ready for reading.*/ - if (sdc_wait_for_transfer_state(sdcp)) - return TRUE; - - /* Prepares the DMA channel for reading.*/ - dmaChannelSetup(&STM32_DMA2->channels[STM32_DMA_CHANNEL_4], - (n * SDC_BLOCK_SIZE) / sizeof (uint32_t), buf, - (STM32_SDC_SDIO_DMA_PRIORITY << 12) | - DMA_CCR1_PSIZE_1 | DMA_CCR1_MSIZE_1 | - DMA_CCR1_MINC); - - /* Setting up data transfer. - Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/ - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_DATAENDIE | SDIO_MASK_STBITERRIE; - SDIO->DLEN = n * SDC_BLOCK_SIZE; - SDIO->DCTRL = SDIO_DCTRL_DTDIR | - SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - - /* DMA channel activation.*/ - dmaEnableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - - /* Read multiple blocks command.*/ - if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) - startblk *= SDC_BLOCK_SIZE; - if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_MULTIPLE_BLOCK, - startblk, resp) || - SDC_R1_ERROR(resp[0])) - goto error; - - chSysLock(); - if (SDIO->MASK != 0) { - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_read_multiple(), #1", "not NULL"); - sdcp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_read_multiple(), #2", "not NULL"); - } - if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { - chSysUnlock(); - goto error; - } - dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->DCTRL = 0; - chSysUnlock(); - - return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp); -error: - dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = 0; - SDIO->DCTRL = 0; - return TRUE; -} - -/** - * @brief Reads one block. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer, it must be aligned to - * four bytes boundary - * @return The operation status. - * @retval FALSE operation succeeded, the requested blocks have been - * read. - * @retval TRUE operation failed, the state of the buffer is uncertain. - * - * @notapi - */ -static bool_t sdc_lld_read_single(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf) { - uint32_t resp[1]; - - /* Checks for errors and waits for the card to be ready for reading.*/ - if (sdc_wait_for_transfer_state(sdcp)) - return TRUE; - - /* Prepares the DMA channel for reading.*/ - dmaChannelSetup(&STM32_DMA2->channels[STM32_DMA_CHANNEL_4], - SDC_BLOCK_SIZE / sizeof (uint32_t), buf, - (STM32_SDC_SDIO_DMA_PRIORITY << 12) | - DMA_CCR1_PSIZE_1 | DMA_CCR1_MSIZE_1 | - DMA_CCR1_MINC); - - /* Setting up data transfer. - Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/ - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_DATAENDIE | SDIO_MASK_STBITERRIE; - SDIO->DLEN = SDC_BLOCK_SIZE; - SDIO->DCTRL = SDIO_DCTRL_DTDIR | - SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - - /* DMA channel activation.*/ - dmaEnableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - - /* Read single block command.*/ - if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) - startblk *= SDC_BLOCK_SIZE; - if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_SINGLE_BLOCK, - startblk, resp) || - SDC_R1_ERROR(resp[0])) - goto error; - - chSysLock(); - if (SDIO->MASK != 0) { - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_read_single(), #1", "not NULL"); - sdcp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_read_single(), #2", "not NULL"); - } - if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { - chSysUnlock(); - goto error; - } - dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->DCTRL = 0; - chSysUnlock(); - - return FALSE; -error: - dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = 0; - SDIO->DCTRL = 0; - return TRUE; -} - -/** - * @brief Writes one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer, it must be aligned to - * four bytes boundary - * @param[in] n number of blocks to write - * @return The operation status. - * @retval FALSE operation succeeded, the requested blocks have been - * written. - * @retval TRUE operation failed. - * - * @notapi - */ -static bool_t sdc_lld_write_multiple(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n) { - uint32_t resp[1]; - - /* Checks for errors and waits for the card to be ready for writing.*/ - if (sdc_wait_for_transfer_state(sdcp)) - return TRUE; - - /* Prepares the DMA channel for writing.*/ - dmaChannelSetup(&STM32_DMA2->channels[STM32_DMA_CHANNEL_4], - (n * SDC_BLOCK_SIZE) / sizeof (uint32_t), buf, - (STM32_SDC_SDIO_DMA_PRIORITY << 12) | - DMA_CCR1_PSIZE_1 | DMA_CCR1_MSIZE_1 | - DMA_CCR1_MINC | DMA_CCR1_DIR); - - /* Write multiple blocks command.*/ - if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) - startblk *= SDC_BLOCK_SIZE; - if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_MULTIPLE_BLOCK, - startblk, resp) || - SDC_R1_ERROR(resp[0])) - return TRUE; - - /* Setting up data transfer. - Options: Controller to Card, Block mode, DMA mode, 512 bytes blocks.*/ - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | - SDIO_MASK_STBITERRIE; - SDIO->DLEN = n * SDC_BLOCK_SIZE; - SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - - /* DMA channel activation.*/ - dmaEnableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - - /* Note the mask is checked before going to sleep because the interrupt - may have occurred before reaching the critical zone.*/ - chSysLock(); - if (SDIO->MASK != 0) { - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_write_multiple(), #1", "not NULL"); - sdcp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_write_multiple(), #2", "not NULL"); - } - if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { - chSysUnlock(); - goto error; - } - dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->DCTRL = 0; - chSysUnlock(); - - return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp); -error: - dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = 0; - SDIO->DCTRL = 0; - return TRUE; -} - -/** - * @brief Writes one block. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer, it must be aligned to - * four bytes boundary - * @param[in] n number of blocks to write - * @return The operation status. - * @retval FALSE operation succeeded, the requested blocks have been - * written. - * @retval TRUE operation failed. - * - * @notapi - */ -static bool_t sdc_lld_write_single(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf) { - uint32_t resp[1]; - - /* Checks for errors and waits for the card to be ready for writing.*/ - if (sdc_wait_for_transfer_state(sdcp)) - return TRUE; - - /* Prepares the DMA channel for writing.*/ - dmaChannelSetup(&STM32_DMA2->channels[STM32_DMA_CHANNEL_4], - SDC_BLOCK_SIZE / sizeof (uint32_t), buf, - (STM32_SDC_SDIO_DMA_PRIORITY << 12) | - DMA_CCR1_PSIZE_1 | DMA_CCR1_MSIZE_1 | - DMA_CCR1_MINC | DMA_CCR1_DIR); - - /* Write single block command.*/ - if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0) - startblk *= SDC_BLOCK_SIZE; - if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_BLOCK, - startblk, resp) || - SDC_R1_ERROR(resp[0])) - return TRUE; - - /* Setting up data transfer. - Options: Controller to Card, Block mode, DMA mode, 512 bytes blocks.*/ - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | - SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | - SDIO_MASK_STBITERRIE; - SDIO->DLEN = SDC_BLOCK_SIZE; - SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 | - SDIO_DCTRL_DMAEN | - SDIO_DCTRL_DTEN; - - /* DMA channel activation.*/ - dmaEnableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - - /* Note the mask is checked before going to sleep because the interrupt - may have occurred before reaching the critical zone.*/ - chSysLock(); - if (SDIO->MASK != 0) { - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_write_single(), #1", "not NULL"); - sdcp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - chDbgAssert(sdcp->thread == NULL, - "sdc_lld_write_single(), #2", "not NULL"); - } - if ((SDIO->STA & SDIO_STA_DATAEND) == 0) { - chSysUnlock(); - goto error; - } - dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->DCTRL = 0; - chSysUnlock(); - - return FALSE; -error: - dmaDisableChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - SDIO->ICR = 0xFFFFFFFF; - SDIO->MASK = 0; - SDIO->DCTRL = 0; - return TRUE; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief SDIO IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(SDIO_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - chSysLockFromIsr(); - if (SDCD1.thread != NULL) { - chSchReadyI(SDCD1.thread); - SDCD1.thread = NULL; - } - chSysUnlockFromIsr(); - - /* Disables the source but the status flags are not reset because the - read/write functions need to check them.*/ - SDIO->MASK = 0; - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SDC driver initialization. - * - * @notapi - */ -void sdc_lld_init(void) { - - sdcObjectInit(&SDCD1); - SDCD1.thread = NULL; -} - -/** - * @brief Configures and activates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object, must be @p NULL, - * this driver does not require any configuration - * - * @notapi - */ -void sdc_lld_start(SDCDriver *sdcp) { - - if (sdcp->state == SDC_STOP) { - /* Note, the DMA must be enabled before the IRQs.*/ - dmaAllocate(STM32_DMA2_ID, STM32_DMA_CHANNEL_4, NULL, NULL); - dmaChannelSetPeripheral(&STM32_DMA2->channels[STM32_DMA_CHANNEL_4], &SDIO->FIFO); - NVICEnableVector(SDIO_IRQn, - CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY)); - RCC->AHBENR |= RCC_AHBENR_SDIOEN; - } - /* Configuration, card clock is initially stopped.*/ - SDIO->POWER = 0; - SDIO->CLKCR = 0; - SDIO->DCTRL = 0; - SDIO->DTIMER = STM32_SDC_DATATIMEOUT; -} - -/** - * @brief Deactivates the SDC peripheral. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_stop(SDCDriver *sdcp) { - - if ((sdcp->state == SDC_READY) || (sdcp->state == SDC_ACTIVE)) { - SDIO->POWER = 0; - SDIO->CLKCR = 0; - SDIO->DCTRL = 0; - SDIO->DTIMER = 0; - - /* Clock deactivation.*/ - NVICDisableVector(SDIO_IRQn); - dmaRelease(STM32_DMA2_ID, STM32_DMA_CHANNEL_4); - } -} - -/** - * @brief Starts the SDIO clock and sets it to init mode (400KHz or less). - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_start_clk(SDCDriver *sdcp) { - - (void)sdcp; - /* Initial clock setting: 400KHz, 1bit mode.*/ - SDIO->CLKCR = STM32_SDIO_DIV_LS; - SDIO->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1; - SDIO->CLKCR |= SDIO_CLKCR_CLKEN; -} - -/** - * @brief Sets the SDIO clock to data mode (25MHz or less). - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_set_data_clk(SDCDriver *sdcp) { - - (void)sdcp; - SDIO->CLKCR = (SDIO->CLKCR & 0xFFFFFF00) | STM32_SDIO_DIV_HS; -} - -/** - * @brief Stops the SDIO clock. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * - * @notapi - */ -void sdc_lld_stop_clk(SDCDriver *sdcp) { - - (void)sdcp; - SDIO->CLKCR = 0; - SDIO->POWER = 0; -} - -/** - * @brief Switches the bus to 4 bits mode. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] mode bus mode - * - * @notapi - */ -void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) { - uint32_t clk = SDIO->CLKCR & ~SDIO_CLKCR_WIDBUS; - - (void)sdcp; - switch (mode) { - case SDC_MODE_1BIT: - SDIO->CLKCR = clk; - break; - case SDC_MODE_4BIT: - SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_0; - break; - case SDC_MODE_8BIT: - SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_1; - } -} - -/** - * @brief Sends an SDIO command with no response expected. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * - * @notapi - */ -void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) { - - (void)sdcp; - SDIO->ARG = arg; - SDIO->CMD = (uint32_t)cmd | SDIO_CMD_CPSMEN; - while ((SDIO->STA & SDIO_STA_CMDSENT) == 0) - ; - SDIO->ICR = SDIO_ICR_CMDSENTC; -} - -/** - * @brief Sends an SDIO command with a short response expected. - * @note The CRC is not verified. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (one word) - * @return The operation status. - * @retval FALSE the operation succeeded. - * @retval TRUE the operation failed because timeout, CRC check or - * other errors. - * - * @notapi - */ -bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - (void)sdcp; - SDIO->ARG = arg; - SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; - while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL)) == 0) - ; - SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; - if ((sta & (SDIO_STA_CTIMEOUT)) != 0) - return TRUE; - *resp = SDIO->RESP1; - return FALSE; -} - -/** - * @brief Sends an SDIO command with a short response expected and CRC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (one word) - * @return The operation status. - * @retval FALSE the operation succeeded. - * @retval TRUE the operation failed because timeout, CRC check or - * other errors. - * - * @notapi - */ -bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - uint32_t sta; - - (void)sdcp; - SDIO->ARG = arg; - SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_CPSMEN; - while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL)) == 0) - ; - SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; - if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) - return TRUE; - *resp = SDIO->RESP1; - return FALSE; -} - -/** - * @brief Sends an SDIO command with a long response expected and CRC. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] cmd card command - * @param[in] arg command argument - * @param[out] resp pointer to the response buffer (four words) - * @return The operation status. - * @retval FALSE the operation succeeded. - * @retval TRUE the operation failed because timeout, CRC check or - * other errors. - * - * @notapi - */ -bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp) { - - uint32_t sta; - - (void)sdcp; - SDIO->ARG = arg; - SDIO->CMD = (uint32_t)cmd | SDIO_CMD_WAITRESP_0 | SDIO_CMD_WAITRESP_1 | - SDIO_CMD_CPSMEN; - while (((sta = SDIO->STA) & (SDIO_STA_CMDREND | SDIO_STA_CTIMEOUT | - SDIO_STA_CCRCFAIL)) == 0) - ; - SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC; - if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0) - return TRUE; - *resp = SDIO->RESP1; - return FALSE; -} - -/** - * @brief Reads one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to read - * @param[out] buf pointer to the read buffer - * @param[in] n number of blocks to read - * @return The operation status. - * @retval FALSE operation succeeded, the requested blocks have been - * read. - * @retval TRUE operation failed, the state of the buffer is uncertain. - * - * @notapi - */ -bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n) { - -#if STM32_SDC_UNALIGNED_SUPPORT - if (((unsigned)buf & 3) != 0) { - uint32_t i; - for (i = 0; i < n; i++) { - if (sdc_lld_read_single(sdcp, startblk, u.buf)) - return TRUE; - memcpy(buf, u.buf, SDC_BLOCK_SIZE); - buf += SDC_BLOCK_SIZE; - startblk++; - } - return FALSE; - } -#endif - if (n == 1) - return sdc_lld_read_single(sdcp, startblk, buf); - return sdc_lld_read_multiple(sdcp, startblk, buf, n); -} - -/** - * @brief Writes one or more blocks. - * - * @param[in] sdcp pointer to the @p SDCDriver object - * @param[in] startblk first block to write - * @param[out] buf pointer to the write buffer - * @param[in] n number of blocks to write - * @return The operation status. - * @retval FALSE operation succeeded, the requested blocks have been - * written. - * @retval TRUE operation failed. - * - * @notapi - */ -bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n) { - - #if STM32_SDC_UNALIGNED_SUPPORT - if (((unsigned)buf & 3) != 0) { - uint32_t i; - for (i = 0; i < n; i++) { - memcpy(u.buf, buf, SDC_BLOCK_SIZE); - buf += SDC_BLOCK_SIZE; - if (sdc_lld_write_single(sdcp, startblk, u.buf)) - return TRUE; - startblk++; - } - return FALSE; - } -#endif - if (n == 1) - return sdc_lld_write_single(sdcp, startblk, buf); - return sdc_lld_write_multiple(sdcp, startblk, buf, n); -} - -#endif /* HAL_USE_SDC */ - -/** @} */ diff --git a/os/hal/platforms/STM32/sdc_lld.h b/os/hal/platforms/STM32/sdc_lld.h deleted file mode 100644 index 5466eacad..000000000 --- a/os/hal/platforms/STM32/sdc_lld.h +++ /dev/null @@ -1,203 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/sdc_lld.h - * @brief STM32 SDC subsystem low level driver header. - * - * @addtogroup SDC - * @{ - */ - -#ifndef _SDC_LLD_H_ -#define _SDC_LLD_H_ - -#if HAL_USE_SDC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief SDIO data timeout in SDIO clock cycles. - */ -#if !defined(STM32_SDC_DATATIMEOUT) || defined(__DOXYGEN__) -#define STM32_SDC_DATATIMEOUT 0x000FFFFF -#endif - -/** - * @brief SDIO DMA priority (0..3|lowest..highest). - */ -#if !defined(STM32_SDC_SDIO_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SDC_SDIO_DMA_PRIORITY 3 -#endif - -/** - * @brief SDIO interrupt priority level setting. - */ -#if !defined(STM32_SDC_SDIO_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SDC_SDIO_IRQ_PRIORITY 9 -#endif - -/** - * @brief SDIO support for unaligned transfers. - */ -#if !defined(STM32_SDC_UNALIGNED_SUPPORT) || defined(__DOXYGEN__) -#define STM32_SDC_UNALIGNED_SUPPORT TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_HAS_SDIO -#error "SDIO not present in the selected device" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/* - * SDIO clock divider. - */ -#if STM32_HCLK > 48000000 -#define STM32_SDIO_DIV_HS 0x01 -#define STM32_SDIO_DIV_LS 0xB2 -#else -#define STM32_SDIO_DIV_HS 0x00 -#define STM32_SDIO_DIV_LS 0x76 -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of SDIO bus mode. - */ -typedef enum { - SDC_MODE_1BIT = 0, - SDC_MODE_4BIT, - SDC_MODE_8BIT -} sdcbusmode_t; - -/** - * @brief Type of card flags. - */ -typedef uint32_t sdcmode_t; - -/** - * @brief Type of a structure representing an SDC driver. - */ -typedef struct SDCDriver SDCDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - uint32_t dummy; -} SDCConfig; - -/** - * @brief Structure representing an SDC driver. - */ -struct SDCDriver { - /** - * @brief Driver state. - */ - sdcstate_t state; - /** - * @brief Current configuration data. - */ - const SDCConfig *config; - /** - * @brief Various flags regarding the mounted card. - */ - sdcmode_t cardmode; - /** - * @brief Card CID. - */ - uint32_t cid[4]; - /** - * @brief Card CSD. - */ - uint32_t csd[4]; - /** - * @brief Card RCA. - */ - uint32_t rca; - /* End of the mandatory fields.*/ - /** - * @brief Tthread waiting for I/O completion IRQ. - */ - Thread *thread; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern SDCDriver SDCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sdc_lld_init(void); - void sdc_lld_start(SDCDriver *sdcp); - void sdc_lld_stop(SDCDriver *sdcp); - void sdc_lld_start_clk(SDCDriver *sdcp); - void sdc_lld_set_data_clk(SDCDriver *sdcp); - void sdc_lld_stop_clk(SDCDriver *sdcp); - void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode); - void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg); - bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg, - uint32_t *resp); - bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk, - uint8_t *buf, uint32_t n); - bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk, - const uint8_t *buf, uint32_t n); - bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp); - bool_t sdc_lld_is_write_protected(SDCDriver *sdcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SDC */ - -#endif /* _SDC_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM32/spi_lld.c b/os/hal/platforms/STM32/spi_lld.c deleted file mode 100644 index d8ae657a7..000000000 --- a/os/hal/platforms/STM32/spi_lld.c +++ /dev/null @@ -1,428 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/spi_lld.c - * @brief STM32 SPI subsystem low level driver source. - * - * @addtogroup SPI - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief SPI1 driver identifier.*/ -#if STM32_SPI_USE_SPI1 || defined(__DOXYGEN__) -SPIDriver SPID1; -#endif - -/** @brief SPI2 driver identifier.*/ -#if STM32_SPI_USE_SPI2 || defined(__DOXYGEN__) -SPIDriver SPID2; -#endif - -/** @brief SPI3 driver identifier.*/ -#if STM32_SPI_USE_SPI3 || defined(__DOXYGEN__) -SPIDriver SPID3; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -static uint16_t dummytx; -static uint16_t dummyrx; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Stops the SPI DMA channels. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -#define dma_stop(spip) { \ - dmaChannelDisable(spip->dmatx); \ - dmaChannelDisable(spip->dmarx); \ -} - -/** - * @brief Starts the SPI DMA channels. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -#define dma_start(spip) { \ - dmaChannelEnable((spip)->dmarx); \ - dmaChannelEnable((spip)->dmatx); \ -} - -/** - * @brief Shared end-of-rx service routine. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void spi_lld_serve_rx_interrupt(SPIDriver *spip, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_SPI_DMA_ERROR_HOOK) - if ((flags & DMA_ISR_TEIF1) != 0) { - STM32_SPI_DMA_ERROR_HOOK(spip); - } -#else - (void)flags; -#endif - - /* Stop everything.*/ - dma_stop(spip); - - /* Portable SPI ISR code defined in the high level driver, note, it is - a macro.*/ - _spi_isr_code(spip); -} - -/** - * @brief Shared end-of-tx service routine. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void spi_lld_serve_tx_interrupt(SPIDriver *spip, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_SPI_DMA_ERROR_HOOK) - (void)spip; - if ((flags & DMA_ISR_TEIF1) != 0) { - STM32_SPI_DMA_ERROR_HOOK(spip); - } -#else - (void)spip; - (void)flags; -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - * - * @notapi - */ -void spi_lld_init(void) { - - dummytx = 0xFFFF; - -#if STM32_SPI_USE_SPI1 - spiObjectInit(&SPID1); - SPID1.thread = NULL; - SPID1.spi = SPI1; - SPID1.dmarx = STM32_DMA1_CH2; - SPID1.dmatx = STM32_DMA1_CH3; -#endif - -#if STM32_SPI_USE_SPI2 - spiObjectInit(&SPID2); - SPID2.thread = NULL; - SPID2.spi = SPI2; - SPID2.dmarx = STM32_DMA1_CH4; - SPID2.dmatx = STM32_DMA1_CH5; -#endif - -#if STM32_SPI_USE_SPI3 - spiObjectInit(&SPID3); - SPID3.thread = NULL; - SPID3.spi = SPI3; - SPID3.dmarx = STM32_DMA2_CH1; - SPID3.dmatx = STM32_DMA2_CH2; -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_start(SPIDriver *spip) { - - /* If in stopped state then enables the SPI and DMA clocks.*/ - if (spip->state == SPI_STOP) { -#if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) { - /* Note, the DMA must be enabled before the IRQs.*/ - dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_2, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); - dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_3, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); - NVICEnableVector(DMA1_Channel2_IRQn, - CORTEX_PRIORITY_MASK(STM32_SPI_SPI1_IRQ_PRIORITY)); - NVICEnableVector(DMA1_Channel3_IRQn, - CORTEX_PRIORITY_MASK(STM32_SPI_SPI1_IRQ_PRIORITY)); - RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; - } -#endif -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) { - /* Note, the DMA must be enabled before the IRQs.*/ - dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_4, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); - dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_5, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); - NVICEnableVector(DMA1_Channel4_IRQn, - CORTEX_PRIORITY_MASK(STM32_SPI_SPI2_IRQ_PRIORITY)); - NVICEnableVector(DMA1_Channel5_IRQn, - CORTEX_PRIORITY_MASK(STM32_SPI_SPI2_IRQ_PRIORITY)); - RCC->APB1ENR |= RCC_APB1ENR_SPI2EN; - } -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) { - /* Note, the DMA must be enabled before the IRQs.*/ - dmaAllocate(STM32_DMA2_ID, STM32_DMA_CHANNEL_1, - (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); - dmaAllocate(STM32_DMA2_ID, STM32_DMA_CHANNEL_2, - (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); - NVICEnableVector(DMA2_Channel1_IRQn, - CORTEX_PRIORITY_MASK(STM32_SPI_SPI3_IRQ_PRIORITY)); - NVICEnableVector(DMA2_Channel2_IRQn, - CORTEX_PRIORITY_MASK(STM32_SPI_SPI3_IRQ_PRIORITY)); - RCC->APB1ENR |= RCC_APB1ENR_SPI3EN; - } -#endif - - /* DMA setup.*/ - dmaChannelSetPeripheral(spip->dmarx, &spip->spi->DR); - dmaChannelSetPeripheral(spip->dmatx, &spip->spi->DR); - } - - /* More DMA setup.*/ - if ((spip->config->cr1 & SPI_CR1_DFF) == 0) - spip->dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) | - DMA_CCR1_TEIE; /* 8 bits transfers. */ - else - spip->dmaccr = (STM32_SPI_SPI2_DMA_PRIORITY << 12) | - DMA_CCR1_TEIE | DMA_CCR1_MSIZE_0 | - DMA_CCR1_PSIZE_0; /* 16 bits transfers. */ - - /* SPI setup and enable.*/ - spip->spi->CR1 = 0; - spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | - SPI_CR1_SSI; - spip->spi->CR2 = SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; - spip->spi->CR1 |= SPI_CR1_SPE; -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_stop(SPIDriver *spip) { - - /* If in ready state then disables the SPI clock.*/ - if (spip->state == SPI_READY) { - - /* SPI disable.*/ - spip->spi->CR1 = 0; - -#if STM32_SPI_USE_SPI1 - if (&SPID1 == spip) { - NVICDisableVector(DMA1_Channel2_IRQn); - NVICDisableVector(DMA1_Channel3_IRQn); - dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_2); - dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_3); - RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN; - } -#endif -#if STM32_SPI_USE_SPI2 - if (&SPID2 == spip) { - NVICDisableVector(DMA1_Channel4_IRQn); - NVICDisableVector(DMA1_Channel5_IRQn); - dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_4); - dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_5); - RCC->APB1ENR &= ~RCC_APB1ENR_SPI2EN; - } -#endif -#if STM32_SPI_USE_SPI3 - if (&SPID3 == spip) { - NVICDisableVector(DMA2_Channel1_IRQn); - NVICDisableVector(DMA2_Channel2_IRQn); - dmaRelease(STM32_DMA2_ID, STM32_DMA_CHANNEL_1); - dmaRelease(STM32_DMA2_ID, STM32_DMA_CHANNEL_2); - RCC->APB1ENR &= ~RCC_APB1ENR_SPI3EN; - } -#endif - } -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_select(SPIDriver *spip) { - - palClearPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_unselect(SPIDriver *spip) { - - palSetPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This asynchronous function starts the transmission of a series of - * idle words on the SPI bus and ignores the received data. - * @post At the end of the operation the configured callback is invoked. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @notapi - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) { - - dmaChannelSetup(spip->dmarx, n, &dummyrx, - spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN); - dmaChannelSetup(spip->dmatx, n, &dummytx, - spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - dmaChannelSetup(spip->dmarx, n, rxbuf, - spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC | - DMA_CCR1_EN); - dmaChannelSetup(spip->dmatx, n, txbuf, - spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC | - DMA_CCR1_EN); -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { - - dmaChannelSetup(spip->dmarx, n, &dummyrx, - spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_EN); - dmaChannelSetup(spip->dmatx, n, txbuf, - spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC | - DMA_CCR1_EN); -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { - - dmaChannelSetup(spip->dmarx, n, rxbuf, - spip->dmaccr | DMA_CCR1_TCIE | DMA_CCR1_MINC | - DMA_CCR1_EN); - dmaChannelSetup(spip->dmatx, n, &dummytx, - spip->dmaccr | DMA_CCR1_DIR | DMA_CCR1_EN); -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { - - spip->spi->DR = frame; - while ((spip->spi->SR & SPI_SR_RXNE) == 0) - ; - return spip->spi->DR; -} - -#endif /* HAL_USE_SPI */ - -/** @} */ diff --git a/os/hal/platforms/STM32/spi_lld.h b/os/hal/platforms/STM32/spi_lld.h deleted file mode 100644 index 6f1e94096..000000000 --- a/os/hal/platforms/STM32/spi_lld.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/spi_lld.h - * @brief STM32 SPI subsystem low level driver header. - * - * @addtogroup SPI - * @{ - */ - -#ifndef _SPI_LLD_H_ -#define _SPI_LLD_H_ - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief SPI1 driver enable switch. - * @details If set to @p TRUE the support for SPI1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI1 TRUE -#endif - -/** - * @brief SPI2 driver enable switch. - * @details If set to @p TRUE the support for SPI2 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI2 TRUE -#endif - -/** - * @brief SPI3 driver enable switch. - * @details If set to @p TRUE the support for SPI3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__) -#define STM32_SPI_USE_SPI3 FALSE -#endif - -/** - * @brief SPI1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_DMA_PRIORITY 1 -#endif - -/** - * @brief SPI1 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI1_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI2 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI2_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI3 interrupt priority level setting. - */ -#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_SPI_SPI3_IRQ_PRIORITY 10 -#endif - -/** - * @brief SPI DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt() -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1 -#error "SPI1 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2 -#error "SPI2 not present in the selected device" -#endif - -#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3 -#error "SPI3 not present in the selected device" -#endif - -#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 -#error "SPI driver activated but no SPI peripheral assigned" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an SPI driver. - */ -typedef struct SPIDriver SPIDriver; - -/** - * @brief SPI notification callback type. - * - * @param[in] spip pointer to the @p SPIDriver object triggering the - * callback - */ -typedef void (*spicallback_t)(SPIDriver *spip); - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief Operation complete callback or @p NULL. - */ - spicallback_t end_cb; - /* End of the mandatory fields.*/ - /** - * @brief The chip select line port. - */ - ioportid_t ssport; - /** - * @brief The chip select line pad number. - */ - uint16_t sspad; - /** - * @brief SPI initialization data. - */ - uint16_t cr1; -} SPIConfig; - -/** - * @brief Structure representing a SPI driver. - */ -struct SPIDriver{ - /** - * @brief Driver state. - */ - spistate_t state; - /** - * @brief Current configuration data. - */ - const SPIConfig *config; -#if SPI_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - Thread *thread; -#endif /* SPI_USE_WAIT */ -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - Mutex mutex; -#elif CH_USE_SEMAPHORES - Semaphore semaphore; -#endif -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#if defined(SPI_DRIVER_EXT_FIELDS) - SPI_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the SPIx registers block. - */ - SPI_TypeDef *spi; - /** - * @brief Pointer to the receive DMA channel registers block. - */ - stm32_dma_channel_t *dmarx; - /** - * @brief Pointer to the transmit DMA channel registers block. - */ - stm32_dma_channel_t *dmatx; - /** - * @brief DMA priority bit mask. - */ - uint32_t dmaccr; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__) -extern SPIDriver SPID2; -#endif - -#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__) -extern SPIDriver SPID3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); - uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SPI */ - -#endif /* _SPI_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM32/stm32_dma.c b/os/hal/platforms/STM32/stm32_dma.c deleted file mode 100644 index 2232df448..000000000 --- a/os/hal/platforms/STM32/stm32_dma.c +++ /dev/null @@ -1,468 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file stm32_dma.c - * @brief STM32 DMA helper driver code. - * - * @addtogroup STM32_DMA - * @details DMA sharing helper driver. In the STM32 the DMA channels are a - * shared resource, this driver allows to allocate and free DMA - * channels at runtime in order to allow all the other device - * drivers to coordinate the access to the resource. - * @note The DMA ISR handlers are all declared into this module because - * sharing, the various device drivers can associate a callback to - * IRSs when allocating channels. - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief DMA ISR redirector type. - */ -typedef struct { - stm32_dmaisr_t dmaisrfunc; - void *dmaisrparam; -} dma_isr_redir_t; - -static uint32_t dmamsk1; -static dma_isr_redir_t dma1[7]; - -#if STM32_HAS_DMA2 -static uint32_t dmamsk2; -static dma_isr_redir_t dma2[5]; -#endif - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief DMA1 channel 1 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_1 * 4); - dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_1); - if (dma1[0].dmaisrfunc) - dma1[0].dmaisrfunc(dma1[0].dmaisrparam, isr); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 channel 2 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch2_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_2 * 4); - dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_2); - if (dma1[1].dmaisrfunc) - dma1[1].dmaisrfunc(dma1[1].dmaisrparam, isr); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 channel 3 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch3_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_3 * 4); - dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_3); - if (dma1[2].dmaisrfunc) - dma1[2].dmaisrfunc(dma1[2].dmaisrparam, isr); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 channel 4 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch4_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_4 * 4); - dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_4); - if (dma1[3].dmaisrfunc) - dma1[3].dmaisrfunc(dma1[3].dmaisrparam, isr); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 channel 5 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch5_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_5 * 4); - dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_5); - if (dma1[4].dmaisrfunc) - dma1[4].dmaisrfunc(dma1[4].dmaisrparam, isr); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 channel 6 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch6_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_6 * 4); - dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_6); - if (dma1[5].dmaisrfunc) - dma1[5].dmaisrfunc(dma1[5].dmaisrparam, isr); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA1 channel 7 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA1_Ch7_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = STM32_DMA1->ISR >> (STM32_DMA_CHANNEL_7 * 4); - dmaClearChannel(STM32_DMA1, STM32_DMA_CHANNEL_7); - if (dma1[6].dmaisrfunc) - dma1[6].dmaisrfunc(dma1[6].dmaisrparam, isr); - - CH_IRQ_EPILOGUE(); -} - -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) -/** - * @brief DMA2 channel 1 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch1_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_1 * 4); - dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_1); - if (dma2[0].dmaisrfunc) - dma2[0].dmaisrfunc(dma2[0].dmaisrparam, isr); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 channel 2 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch2_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_2 * 4); - dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_2); - if (dma2[1].dmaisrfunc) - dma2[1].dmaisrfunc(dma2[1].dmaisrparam, isr); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 channel 3 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_3 * 4); - dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_3); - if (dma2[2].dmaisrfunc) - dma2[2].dmaisrfunc(dma2[2].dmaisrparam, isr); - - CH_IRQ_EPILOGUE(); -} - -#if defined(STM32F10X_CL) || defined(__DOXYGEN__) -/** - * @brief DMA2 channel 4 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch4_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_4 * 4); - dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_4); - if (dma2[3].dmaisrfunc) - dma2[3].dmaisrfunc(dma2[3].dmaisrparam, isr); - - CH_IRQ_EPILOGUE(); -} - -/** - * @brief DMA2 channel 5 shared interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_5 * 4); - dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_5); - if (dma2[4].dmaisrfunc) - dma2[4].dmaisrfunc(dma2[4].dmaisrparam, isr); - - CH_IRQ_EPILOGUE(); -} - -#else /* !STM32F10X_CL */ -/** - * @brief DMA2 channels 4 and 5 shared interrupt handler. - * @note This IRQ is shared between DMA2 channels 4 and 5 so it is a - * bit less efficient because an extra check. - * - * @isr - */ -CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) { - uint32_t isr; - - CH_IRQ_PROLOGUE(); - - /* Check on channel 4.*/ - isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_5 * 4); - if (isr & DMA_ISR_GIF1) { - dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_5); - if (dma2[3].dmaisrfunc) - dma2[3].dmaisrfunc(dma2[3].dmaisrparam, isr); - } - - /* Check on channel 5.*/ - isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_4 * 4); - if (isr & DMA_ISR_GIF1) { - dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_5); - if (dma2[4].dmaisrfunc) - dma2[4].dmaisrfunc(dma2[4].dmaisrparam, isr); - } - - CH_IRQ_EPILOGUE(); -} -#endif /* !STM32F10X_CL */ -#endif /* STM32_HAS_DMA2 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA helper initialization. - * - * @init - */ -void dmaInit(void) { - int i; - - dmamsk1 = 0; - for (i = STM32_DMA_CHANNEL_7; i >= STM32_DMA_CHANNEL_1; i--) { - dmaDisableChannel(STM32_DMA1, i); - dma1[i].dmaisrfunc = NULL; - } - STM32_DMA1->IFCR = 0xFFFFFFFF; -#if STM32_HAS_DMA2 - dmamsk2 = 0; - for (i = STM32_DMA_CHANNEL_5; i >= STM32_DMA_CHANNEL_1; i--) { - dmaDisableChannel(STM32_DMA2, i); - dma2[i].dmaisrfunc = NULL; - } - STM32_DMA1->IFCR = 0xFFFFFFFF; -#endif -} - -/** - * @brief Allocates a DMA channel. - * @details The channel is allocated and, if required, the DMA clock enabled. - * Trying to allocate a channel already allocated is an illegal - * operation and is trapped if assertions are enabled. - * @pre The channel must not be already in use. - * @post The channel is allocated and the default ISR handler redirected - * to the specified function. - * @post The channel must be freed using @p dmaRelease() before it can - * be reused with another peripheral. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dma DMA controller id - * @param[in] channel requested channel id - * @param[in] func handling function pointer, can be @p NULL - * @param[in] param a parameter to be passed to the handling function - * @return The operation status. - * @retval FALSE operation successfully allocated. - * @retval TRUE the channel was already in use. - * - * @special - */ -void dmaAllocate(uint32_t dma, uint32_t channel, - stm32_dmaisr_t func, void *param) { - - chDbgCheck(func != NULL, "dmaAllocate"); - -#if STM32_HAS_DMA2 - switch (dma) { - case STM32_DMA1_ID: -#else - (void)dma; -#endif - /* Check if the channel is already taken.*/ - chDbgAssert((dmamsk1 & (1 << channel)) == 0, - "dmaAllocate(), #1", "already allocated"); - - /* If the DMA unit was idle then the clock is enabled.*/ - if (dmamsk1 == 0) { - RCC->AHBENR |= RCC_AHBENR_DMA1EN; - DMA1->IFCR = 0x0FFFFFFF; - } - - dmamsk1 |= 1 << channel; - dma1[channel].dmaisrfunc = func; - dma1[channel].dmaisrparam = param; -#if STM32_HAS_DMA2 - break; - case STM32_DMA2_ID: - /* Check if the channel is already taken.*/ - chDbgAssert((dmamsk2 & (1 << channel)) == 0, - "dmaAllocate(), #2", "already allocated"); - - /* If the DMA unit was idle then the clock is enabled.*/ - if (dmamsk2 == 0) { - RCC->AHBENR |= RCC_AHBENR_DMA2EN; - DMA2->IFCR = 0x0FFFFFFF; - } - - dmamsk2 |= 1 << channel; - dma2[channel].dmaisrfunc = func; - dma2[channel].dmaisrparam = param; - break; - } -#endif -} - -/** - * @brief Releases a DMA channel. - * @details The channel is freed and, if required, the DMA clock disabled. - * Trying to release a unallocated channel is an illegal operation - * and is trapped if assertions are enabled. - * @pre The channel must have been allocated using @p dmaRequest(). - * @post The channel is again available. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dma DMA controller id - * @param[in] channel requested channel id - * - * @special - */ -void dmaRelease(uint32_t dma, uint32_t channel) { - -#if STM32_HAS_DMA2 - switch (dma) { - case STM32_DMA1_ID: -#else - (void)dma; -#endif - /* Check if the channel is not taken.*/ - chDbgAssert((dmamsk1 & (1 << channel)) != 0, - "dmaRelease(), #1", "not allocated"); - - dma1[channel].dmaisrfunc = NULL; - dmamsk1 &= ~(1 << channel); - if (dmamsk1 == 0) - RCC->AHBENR &= ~RCC_AHBENR_DMA1EN; -#if STM32_HAS_DMA2 - break; - case STM32_DMA2_ID: - /* Check if the channel is not taken.*/ - chDbgAssert((dmamsk2 & (1 << channel)) != 0, - "dmaRelease(), #2", "not allocated"); - - dma2[channel].dmaisrfunc = NULL; - dmamsk2 &= ~(1 << channel); - if (dmamsk2 == 0) - RCC->AHBENR &= ~RCC_AHBENR_DMA2EN; - break; - } -#endif -} - -#endif /* STM32_DMA_REQUIRED */ - -/** @} */ diff --git a/os/hal/platforms/STM32/stm32_dma.h b/os/hal/platforms/STM32/stm32_dma.h deleted file mode 100644 index 66a2f8c69..000000000 --- a/os/hal/platforms/STM32/stm32_dma.h +++ /dev/null @@ -1,280 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file stm32_dma.h - * @brief STM32 DMA helper driver header. - * @note This file requires definitions from the ST STM32 header file - * stm3232f10x.h. - * - * @addtogroup STM32_DMA - * @{ - */ - -#ifndef _STM32_DMA_H_ -#define _STM32_DMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** @brief DMA1 identifier.*/ -#define STM32_DMA1_ID 0 - -/** @brief DMA2 identifier.*/ -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) -#define STM32_DMA2_ID 1 -#endif - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief STM32 DMA channel memory structure type. - */ -typedef struct { - volatile uint32_t CCR; - volatile uint32_t CNDTR; - volatile uint32_t CPAR; - volatile uint32_t CMAR; - volatile uint32_t dummy; -} stm32_dma_channel_t; - -/** - * @brief STM32 DMA subsystem memory structure type. - * @note This structure has been redefined here because it is convenient to - * have the channels organized as an array, the ST header does not - * do that. - */ -typedef struct { - volatile uint32_t ISR; - volatile uint32_t IFCR; - stm32_dma_channel_t channels[7]; -} stm32_dma_t; - -/** - * @brief STM32 DMA ISR function type. - * - * @param[in] p parameter for the registered function - * @param[in] flags pre-shifted content of the ISR register - */ -typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** DMA1 registers block numeric address.*/ -#define STM32_DMA1_BASE (AHBPERIPH_BASE + 0x0000) -/** Pointer to the DMA1 registers block.*/ -#define STM32_DMA1 ((stm32_dma_t *)STM32_DMA1_BASE) -/** Pointer to the DMA1 channel 1 registers block.*/ -#define STM32_DMA1_CH1 (&STM32_DMA1->channels[0]) -/** Pointer to the DMA1 channel 2 registers block.*/ -#define STM32_DMA1_CH2 (&STM32_DMA1->channels[1]) -/** Pointer to the DMA1 channel 3 registers block.*/ -#define STM32_DMA1_CH3 (&STM32_DMA1->channels[2]) -/** Pointer to the DMA1 channel 4 registers block.*/ -#define STM32_DMA1_CH4 (&STM32_DMA1->channels[3]) -/** Pointer to the DMA1 channel 5 registers block.*/ -#define STM32_DMA1_CH5 (&STM32_DMA1->channels[4]) -/** Pointer to the DMA1 channel 6 registers block.*/ -#define STM32_DMA1_CH6 (&STM32_DMA1->channels[5]) -/** Pointer to the DMA1 channel 7 registers block.*/ -#define STM32_DMA1_CH7 (&STM32_DMA1->channels[6]) - -#if STM32_HAS_DMA2 || defined(__DOXYGEN__) -/** DMA2 registers block numeric address.*/ -#define STM32_DMA2_BASE (AHBPERIPH_BASE + 0x0400) -/** Pointer to the DMA2 registers block.*/ -#define STM32_DMA2 ((stm32_dma_t *)STM32_DMA2_BASE) -/** Pointer to the DMA2 channel 1 registers block.*/ -#define STM32_DMA2_CH1 (&STM32_DMA2->channels[0]) -/** Pointer to the DMA2 channel 2 registers block.*/ -#define STM32_DMA2_CH2 (&STM32_DMA2->channels[1]) -/** Pointer to the DMA2 channel 3 registers block.*/ -#define STM32_DMA2_CH3 (&STM32_DMA2->channels[2]) -/** Pointer to the DMA2 channel 4 registers block.*/ -#define STM32_DMA2_CH4 (&STM32_DMA2->channels[3]) -/** Pointer to the DMA2 channel 5 registers block.*/ -#define STM32_DMA2_CH5 (&STM32_DMA2->channels[4]) -#endif - -#define STM32_DMA_CHANNEL_1 0 /**< @brief DMA channel 1. */ -#define STM32_DMA_CHANNEL_2 1 /**< @brief DMA channel 2. */ -#define STM32_DMA_CHANNEL_3 2 /**< @brief DMA channel 3. */ -#define STM32_DMA_CHANNEL_4 3 /**< @brief DMA channel 4. */ -#define STM32_DMA_CHANNEL_5 4 /**< @brief DMA channel 5. */ -#define STM32_DMA_CHANNEL_6 5 /**< @brief DMA channel 6. */ -#define STM32_DMA_CHANNEL_7 6 /**< @brief DMA channel 7. */ - -/** - * @brief Associates a peripheral data register to a DMA channel. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmachp dmachp to a stm32_dma_channel_t structure - * @param[in] cpar value to be written in the CPAR register - * - * @special - */ -#define dmaChannelSetPeripheral(dmachp, cpar) { \ - (dmachp)->CPAR = (uint32_t)(cpar); \ -} - -/** - * @brief DMA channel setup by channel pointer. - * @note This macro does not change the CPAR register because that register - * value does not change frequently, it usually points to a peripheral - * data register. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmachp dmachp to a stm32_dma_channel_t structure - * @param[in] cndtr value to be written in the CNDTR register - * @param[in] cmar value to be written in the CMAR register - * @param[in] ccr value to be written in the CCR register - * - * @special - */ -#define dmaChannelSetup(dmachp, cndtr, cmar, ccr) { \ - (dmachp)->CNDTR = (uint32_t)(cndtr); \ - (dmachp)->CMAR = (uint32_t)(cmar); \ - (dmachp)->CCR = (uint32_t)(ccr); \ -} - -/** - * @brief DMA channel enable by channel pointer. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmachp dmachp to a stm32_dma_channel_t structure - * - * @special - */ -#define dmaChannelEnable(dmachp) { \ - (dmachp)->CCR |= DMA_CCR1_EN; \ -} - - -/** - * @brief DMA channel disable by channel pointer. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmachp dmachp to a stm32_dma_channel_t structure - * - * @special - */ -#define dmaChannelDisable(dmachp) { \ - (dmachp)->CCR = 0; \ -} - -/** - * @brief DMA channel setup by channel ID. - * @note This macro does not change the CPAR register because that register - * value does not change frequently, it usually points to a peripheral - * data register. - * @note Channels are numbered from 0 to 6, use the appropriate macro - * as parameter. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmap pointer to a stm32_dma_t structure - * @param[in] ch channel number - * @param[in] cndtr value to be written in the CNDTR register - * @param[in] cmar value to be written in the CMAR register - * @param[in] ccr value to be written in the CCR register - * - * @special - */ -#define dmaSetupChannel(dmap, ch, cndtr, cmar, ccr) { \ - dmaChannelSetup(&(dmap)->channels[ch], (cndtr), (cmar), (ccr)); \ -} - -/** - * @brief DMA channel enable by channel ID. - * @note Channels are numbered from 0 to 6, use the appropriate macro - * as parameter. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmap pointer to a stm32_dma_t structure - * @param[in] ch channel number - * - * @special - */ -#define dmaEnableChannel(dmap, ch) { \ - dmaChannelEnable(&(dmap)->channels[ch]); \ -} - -/** - * @brief DMA channel disable by channel ID. - * @note Channels are numbered from 0 to 6, use the appropriate macro - * as parameter. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmap pointer to a stm32_dma_t structure - * @param[in] ch channel number - * - * @special - */ -#define dmaDisableChannel(dmap, ch) { \ - dmaChannelDisable(&(dmap)->channels[ch]); \ -} - -/** - * @brief DMA channel interrupt sources clear. - * @details Sets the appropriate CGIF bit into the IFCR register in order to - * withdraw all the pending interrupt bits from the ISR register. - * @note Channels are numbered from 0 to 6, use the appropriate macro - * as parameter. - * @note This function can be invoked in both ISR or thread context. - * - * @param[in] dmap pointer to a stm32_dma_t structure - * @param[in] ch channel number - * - * @special - */ -#define dmaClearChannel(dmap, ch){ \ - (dmap)->IFCR = 1 << ((ch) * 4); \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void dmaInit(void); - void dmaAllocate(uint32_t dma, uint32_t channel, - stm32_dmaisr_t func, void *param); - void dmaRelease(uint32_t dma, uint32_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* _STM32_DMA_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM32/uart_lld.c b/os/hal/platforms/STM32/uart_lld.c deleted file mode 100644 index e2f306302..000000000 --- a/os/hal/platforms/STM32/uart_lld.c +++ /dev/null @@ -1,559 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/uart_lld.c - * @brief STM32 low level UART driver code. - * - * @addtogroup UART - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** @brief USART1 UART driver identifier.*/ -#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) -UARTDriver UARTD1; -#endif - -/** @brief USART2 UART driver identifier.*/ -#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) -UARTDriver UARTD2; -#endif - -/** @brief USART3 UART driver identifier.*/ -#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) -UARTDriver UARTD3; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Status bits translation. - * - * @param[in] sr USART SR register value - * - * @return The error flags. - */ -static uartflags_t translate_errors(uint16_t sr) { - uartflags_t sts = 0; - - if (sr & USART_SR_ORE) - sts |= UART_OVERRUN_ERROR; - if (sr & USART_SR_PE) - sts |= UART_PARITY_ERROR; - if (sr & USART_SR_FE) - sts |= UART_FRAMING_ERROR; - if (sr & USART_SR_NE) - sts |= UART_NOISE_ERROR; - if (sr & USART_SR_LBD) - sts |= UART_BREAK_DETECTED; - return sts; -} - -/** - * @brief Puts the receiver in the UART_RX_IDLE state. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void set_rx_idle_loop(UARTDriver *uartp) { - uint32_t ccr; - - /* RX DMA channel preparation, if the char callback is defined then the - TCIE interrupt is enabled too.*/ - if (uartp->config->rxchar_cb == NULL) - ccr = DMA_CCR1_CIRC | DMA_CCR1_TEIE; - else - ccr = DMA_CCR1_CIRC | DMA_CCR1_TEIE | DMA_CCR1_TCIE; - dmaSetupChannel(uartp->dmap, uartp->dmarx, 1, - &uartp->rxbuf, uartp->dmaccr | ccr); - dmaEnableChannel(uartp->dmap, uartp->dmarx); -} - -/** - * @brief USART de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void usart_stop(UARTDriver *uartp) { - - /* Stops RX and TX DMA channels.*/ - dmaDisableChannel(uartp->dmap, uartp->dmarx); - dmaDisableChannel(uartp->dmap, uartp->dmatx); - dmaClearChannel(uartp->dmap, uartp->dmarx); - dmaClearChannel(uartp->dmap, uartp->dmatx); - - /* Stops USART operations.*/ - uartp->usart->CR1 = 0; - uartp->usart->CR2 = 0; - uartp->usart->CR3 = 0; -} - -/** - * @brief USART initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void usart_start(UARTDriver *uartp) { - uint16_t cr1; - USART_TypeDef *u = uartp->usart; - - /* Defensive programming, starting from a clean state.*/ - usart_stop(uartp); - - /* Baud rate setting.*/ - if (uartp->usart == USART1) - u->BRR = STM32_PCLK2 / uartp->config->speed; - else - u->BRR = STM32_PCLK1 / uartp->config->speed; - - /* Resetting eventual pending status flags.*/ - (void)u->SR; /* SR reset step 1.*/ - (void)u->DR; /* SR reset step 2.*/ - u->SR = 0; - - /* Note that some bits are enforced because required for correct driver - operations.*/ - if (uartp->config->txend2_cb == NULL) - cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE; - else - cr1 = USART_CR1_UE | USART_CR1_PEIE | USART_CR1_TE | USART_CR1_RE | - USART_CR1_TCIE; - u->CR1 = uartp->config->cr1 | cr1; - u->CR2 = uartp->config->cr2 | USART_CR2_LBDIE; - u->CR3 = uartp->config->cr3 | USART_CR3_DMAT | USART_CR3_DMAR | - USART_CR3_EIE; - - /* Starting the receiver idle loop.*/ - set_rx_idle_loop(uartp); -} - -/** - * @brief RX DMA common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void uart_lld_serve_rx_end_irq(UARTDriver *uartp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & DMA_ISR_TEIF1) != 0) { - STM32_UART_DMA_ERROR_HOOK(uartp); - } -#else - (void)flags; -#endif - - if (uartp->rxstate == UART_RX_IDLE) { - /* Receiver in idle state, a callback is generated, if enabled, for each - received character and then the driver stays in the same state.*/ - if (uartp->config->rxchar_cb != NULL) - uartp->config->rxchar_cb(uartp, uartp->rxbuf); - } - else { - /* Receiver in active state, a callback is generated, if enabled, after - a completed transfer.*/ - dmaDisableChannel(uartp->dmap, uartp->dmarx); - uartp->rxstate = UART_RX_COMPLETE; - if (uartp->config->rxend_cb != NULL) - uartp->config->rxend_cb(uartp); - /* If the callback didn't explicitly change state then the receiver - automatically returns to the idle state.*/ - if (uartp->rxstate == UART_RX_COMPLETE) { - uartp->rxstate = UART_RX_IDLE; - set_rx_idle_loop(uartp); - } - } -} - -/** - * @brief TX DMA common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] flags pre-shifted content of the ISR register - */ -static void uart_lld_serve_tx_end_irq(UARTDriver *uartp, uint32_t flags) { - - /* DMA errors handling.*/ -#if defined(STM32_UART_DMA_ERROR_HOOK) - if ((flags & DMA_ISR_TEIF1) != 0) { - STM32_UART_DMA_ERROR_HOOK(uartp); - } -#else - (void)flags; -#endif - - dmaDisableChannel(uartp->dmap, uartp->dmatx); - /* A callback is generated, if enabled, after a completed transfer.*/ - uartp->txstate = UART_TX_COMPLETE; - if (uartp->config->txend1_cb != NULL) - uartp->config->txend1_cb(uartp); - /* If the callback didn't explicitly change state then the transmitter - automatically returns to the idle state.*/ - if (uartp->txstate == UART_TX_COMPLETE) - uartp->txstate = UART_TX_IDLE; -} - -/** - * @brief USART common service routine. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -static void serve_usart_irq(UARTDriver *uartp) { - uint16_t sr; - USART_TypeDef *u = uartp->usart; - - sr = u->SR; /* SR reset step 1.*/ - (void)u->DR; /* SR reset step 2.*/ - if (sr & (USART_SR_LBD | USART_SR_ORE | USART_SR_NE | - USART_SR_FE | USART_SR_PE)) { - u->SR = ~USART_SR_LBD; - if (uartp->config->rxerr_cb != NULL) - uartp->config->rxerr_cb(uartp, translate_errors(sr)); - } - if (sr & USART_SR_TC) { - u->SR = ~USART_SR_TC; - /* End of transmission, a callback is generated.*/ - if (uartp->config->txend2_cb != NULL) - uartp->config->txend2_cb(uartp); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 || defined(__DOXYGEN__) -/** - * @brief USART1 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(USART1_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD1); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART1 */ - -#if STM32_UART_USE_USART2 || defined(__DOXYGEN__) -/** - * @brief USART2 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(USART2_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD2); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART2 */ - -#if STM32_UART_USE_USART3 || defined(__DOXYGEN__) -/** - * @brief USART3 IRQ handler. - * - * @isr - */ -CH_IRQ_HANDLER(USART3_IRQHandler) { - - CH_IRQ_PROLOGUE(); - - serve_usart_irq(&UARTD3); - - CH_IRQ_EPILOGUE(); -} -#endif /* STM32_UART_USE_USART3 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level UART driver initialization. - * - * @notapi - */ -void uart_lld_init(void) { - -#if STM32_UART_USE_USART1 - uartObjectInit(&UARTD1); - UARTD1.usart = USART1; - UARTD1.dmap = STM32_DMA1; - UARTD1.dmarx = STM32_DMA_CHANNEL_5; - UARTD1.dmatx = STM32_DMA_CHANNEL_4; - UARTD1.dmaccr = 0; -#endif - -#if STM32_UART_USE_USART2 - uartObjectInit(&UARTD2); - UARTD2.usart = USART2; - UARTD2.dmap = STM32_DMA1; - UARTD2.dmarx = STM32_DMA_CHANNEL_6; - UARTD2.dmatx = STM32_DMA_CHANNEL_7; - UARTD2.dmaccr = 0; -#endif - -#if STM32_UART_USE_USART3 - uartObjectInit(&UARTD3); - UARTD3.usart = USART3; - UARTD3.dmap = STM32_DMA1; - UARTD3.dmarx = STM32_DMA_CHANNEL_3; - UARTD3.dmatx = STM32_DMA_CHANNEL_2; - UARTD3.dmaccr = 0; -#endif -} - -/** - * @brief Configures and activates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_start(UARTDriver *uartp) { - - if (uartp->state == UART_STOP) { -#if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { - /* Note, the DMA must be enabled before the IRQs.*/ - dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_4, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); - dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_5, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); - NVICEnableVector(USART1_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); - NVICEnableVector(DMA1_Channel4_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); - NVICEnableVector(DMA1_Channel5_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); - RCC->APB2ENR |= RCC_APB2ENR_USART1EN; - } -#endif - -#if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { - /* Note, the DMA must be enabled before the IRQs.*/ - dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_6, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); - dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_7, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); - NVICEnableVector(USART2_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); - NVICEnableVector(DMA1_Channel6_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); - NVICEnableVector(DMA1_Channel7_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); - RCC->APB1ENR |= RCC_APB1ENR_USART2EN; - } -#endif - -#if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { - /* Note, the DMA must be enabled before the IRQs.*/ - dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_2, - (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); - dmaAllocate(STM32_DMA1_ID, STM32_DMA_CHANNEL_3, - (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); - NVICEnableVector(USART3_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); - NVICEnableVector(DMA1_Channel2_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); - NVICEnableVector(DMA1_Channel3_IRQn, - CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); - RCC->APB1ENR |= RCC_APB1ENR_USART3EN; - } -#endif - - /* Static DMA setup, the transfer size depends on the USART settings, - it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ - uartp->dmaccr = STM32_UART_USART1_DMA_PRIORITY << 12; - if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) - uartp->dmaccr |= DMA_CCR1_MSIZE_0 | DMA_CCR1_PSIZE_0; - dmaChannelSetPeripheral(&uartp->dmap->channels[uartp->dmarx], - &uartp->usart->DR); - dmaChannelSetPeripheral(&uartp->dmap->channels[uartp->dmatx], - &uartp->usart->DR); - uartp->rxbuf = 0; - } - - uartp->rxstate = UART_RX_IDLE; - uartp->txstate = UART_TX_IDLE; - usart_start(uartp); -} - -/** - * @brief Deactivates the UART peripheral. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @notapi - */ -void uart_lld_stop(UARTDriver *uartp) { - - if (uartp->state == UART_READY) { - usart_stop(uartp); - -#if STM32_UART_USE_USART1 - if (&UARTD1 == uartp) { - NVICDisableVector(USART1_IRQn); - NVICDisableVector(DMA1_Channel4_IRQn); - NVICDisableVector(DMA1_Channel5_IRQn); - dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_4); - dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_5); - RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN; - return; - } -#endif - -#if STM32_UART_USE_USART2 - if (&UARTD2 == uartp) { - NVICDisableVector(USART2_IRQn); - NVICDisableVector(DMA1_Channel6_IRQn); - NVICDisableVector(DMA1_Channel7_IRQn); - dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_6); - dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_7); - RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN; - return; - } -#endif - -#if STM32_UART_USE_USART3 - if (&UARTD3 == uartp) { - NVICDisableVector(USART3_IRQn); - NVICDisableVector(DMA1_Channel2_IRQn); - NVICDisableVector(DMA1_Channel3_IRQn); - dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_2); - dmaRelease(STM32_DMA1_ID, STM32_DMA_CHANNEL_3); - RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN; - return; - } -#endif - } -} - -/** - * @brief Starts a transmission on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { - - /* TX DMA channel preparation and start.*/ - dmaSetupChannel(uartp->dmap, uartp->dmatx, n, txbuf, - uartp->dmaccr | DMA_CCR1_DIR | DMA_CCR1_MINC | - DMA_CCR1_TEIE | DMA_CCR1_TCIE); - dmaEnableChannel(uartp->dmap, uartp->dmatx); -} - -/** - * @brief Stops any ongoing transmission. - * @note Stopping a transmission also suppresses the transmission callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not transmitted by the - * stopped transmit operation. - * - * @notapi - */ -size_t uart_lld_stop_send(UARTDriver *uartp) { - - dmaDisableChannel(uartp->dmap, uartp->dmatx); - dmaClearChannel(uartp->dmap, uartp->dmatx); - return (size_t)uartp->dmap->channels[uartp->dmatx].CNDTR; -} - -/** - * @brief Starts a receive operation on the UART peripheral. - * @note The buffers are organized as uint8_t arrays for data sizes below - * or equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] n number of data frames to send - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { - - /* Stopping previous activity (idle state).*/ - dmaDisableChannel(uartp->dmap, uartp->dmarx); - dmaClearChannel(uartp->dmap, uartp->dmarx); - - /* RX DMA channel preparation and start.*/ - dmaSetupChannel(uartp->dmap, uartp->dmarx, n, rxbuf, - uartp->dmaccr | DMA_CCR1_MINC | - DMA_CCR1_TEIE | DMA_CCR1_TCIE); - dmaEnableChannel(uartp->dmap, uartp->dmarx); -} - -/** - * @brief Stops any ongoing receive operation. - * @note Stopping a receive operation also suppresses the receive callbacks. - * - * @param[in] uartp pointer to the @p UARTDriver object - * - * @return The number of data frames not received by the - * stopped receive operation. - * - * @notapi - */ -size_t uart_lld_stop_receive(UARTDriver *uartp) { - size_t n; - - dmaDisableChannel(uartp->dmap, uartp->dmarx); - dmaClearChannel(uartp->dmap, uartp->dmarx); - n = (size_t)uartp->dmap->channels[uartp->dmarx].CNDTR; - set_rx_idle_loop(uartp); - return n; -} - -#endif /* HAL_USE_UART */ - -/** @} */ diff --git a/os/hal/platforms/STM32/uart_lld.h b/os/hal/platforms/STM32/uart_lld.h deleted file mode 100644 index 9321df85c..000000000 --- a/os/hal/platforms/STM32/uart_lld.h +++ /dev/null @@ -1,322 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file STM32/uart_lld.h - * @brief STM32 low level UART driver header. - * - * @addtogroup UART - * @{ - */ - -#ifndef _UART_LLD_H_ -#define _UART_LLD_H_ - -#if HAL_USE_UART || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief UART driver on USART1 enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART1 TRUE -#endif - -/** - * @brief UART driver on USART2 enable switch. - * @details If set to @p TRUE the support for USART2 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART2 TRUE -#endif - -/** - * @brief UART driver on USART3 enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p FALSE. - */ -#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__) -#define STM32_UART_USE_USART3 TRUE -#endif - -/** - * @brief USART1 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART2 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART3 interrupt priority level setting. - */ -#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#endif - -/** - * @brief USART1 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART1_DMA_PRIORITY 0 -#endif - -/** - * @brief USART2 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART2_DMA_PRIORITY 0 -#endif -/** - * @brief USART3 DMA priority (0..3|lowest..highest). - * @note The priority level is used for both the TX and RX DMA channels but - * because of the channels ordering the RX channel has always priority - * over the TX channel. - */ -#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_UART_USART3_DMA_PRIORITY 0 -#endif - -/** - * @brief USART1 DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt() -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 && !STM32_HAS_USART1 -#error "USART1 not present in the selected device" -#endif - -#if STM32_UART_USE_USART2 && !STM32_HAS_USART2 -#error "USART2 not present in the selected device" -#endif - -#if STM32_UART_USE_USART3 && !STM32_HAS_USART3 -#error "USART3 not present in the selected device" -#endif - -#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \ - !STM32_UART_USE_USART3 -#error "UART driver activated but no USART/UART peripheral assigned" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief UART driver condition flags type. - */ -typedef uint32_t uartflags_t; - -/** - * @brief Structure representing an UART driver. - */ -typedef struct UARTDriver UARTDriver; - -/** - * @brief Generic UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - */ -typedef void (*uartcb_t)(UARTDriver *uartp); - -/** - * @brief Character received UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] c received character - */ -typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c); - -/** - * @brief Receive error UART notification callback type. - * - * @param[in] uartp pointer to the @p UARTDriver object - * @param[in] e receive error mask - */ -typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief End of transmission buffer callback. - */ - uartcb_t txend1_cb; - /** - * @brief Physical end of transmission callback. - */ - uartcb_t txend2_cb; - /** - * @brief Receive buffer filled callback. - */ - uartcb_t rxend_cb; - /** - * @brief Character received while out if the @p UART_RECEIVE state. - */ - uartccb_t rxchar_cb; - /** - * @brief Receive error callback. - */ - uartecb_t rxerr_cb; - /* End of the mandatory fields.*/ - /** - * @brief Bit rate. - */ - uint32_t speed; - /** - * @brief Initialization value for the CR1 register. - */ - uint16_t cr1; - /** - * @brief Initialization value for the CR2 register. - */ - uint16_t cr2; - /** - * @brief Initialization value for the CR3 register. - */ - uint16_t cr3; -} UARTConfig; - -/** - * @brief Structure representing an UART driver. - */ -struct UARTDriver { - /** - * @brief Driver state. - */ - uartstate_t state; - /** - * @brief Transmitter state. - */ - uarttxstate_t txstate; - /** - * @brief Receiver state. - */ - uartrxstate_t rxstate; - /** - * @brief Current configuration data. - */ - const UARTConfig *config; -#if defined(UART_DRIVER_EXT_FIELDS) - UART_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the USART registers block. - */ - USART_TypeDef *usart; - /** - * @brief Pointer to the DMA registers block. - */ - stm32_dma_t *dmap; - /** - * @brief DMA priority bit mask. - */ - uint32_t dmaccr; - /** - * @brief Receive DMA channel. - */ - uint8_t dmarx; - /** - * @brief Transmit DMA channel. - */ - uint8_t dmatx; - /** - * @brief Default receive buffer while into @p UART_RX_IDLE state. - */ - volatile uint16_t rxbuf; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__) -extern UARTDriver UARTD1; -#endif - -#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__) -extern UARTDriver UARTD2; -#endif - -#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__) -extern UARTDriver UARTD3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void uart_lld_init(void); - void uart_lld_start(UARTDriver *uartp); - void uart_lld_stop(UARTDriver *uartp); - void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf); - size_t uart_lld_stop_send(UARTDriver *uartp); - void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf); - size_t uart_lld_stop_receive(UARTDriver *uartp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_UART */ - -#endif /* _UART_LLD_H_ */ - -/** @} */ -- cgit v1.2.3