From d090b9342ed8f246d01a0c4466f09281ddeb3cd8 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 19 Nov 2012 12:47:33 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4832
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/SPC560BCxx/hal_lld.c | 18 +++++++++---------
 os/hal/platforms/SPC560Pxx/hal_lld.c  | 18 +++++++++---------
 os/hal/platforms/SPC560Pxx/hal_lld.h  |  6 +++---
 3 files changed, 21 insertions(+), 21 deletions(-)

(limited to 'os/hal/platforms')

diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.c b/os/hal/platforms/SPC560BCxx/hal_lld.c
index 4f7ef3db7..1f714bef0 100644
--- a/os/hal/platforms/SPC560BCxx/hal_lld.c
+++ b/os/hal/platforms/SPC560BCxx/hal_lld.c
@@ -50,7 +50,7 @@
  *
  * @isr
  */
-CH_IRQ_HANDLER(vector127) {
+CH_IRQ_HANDLER(vector59) {
 
   CH_IRQ_PROLOGUE();
 
@@ -59,7 +59,7 @@ CH_IRQ_HANDLER(vector127) {
   chSysUnlockFromIsr();
 
   /* Resets the PIT channel 3 IRQ flag.*/
-  PIT.CH[3].TFLG.R = 1;
+  PIT.CH[0].TFLG.R = 1;
 
   CH_IRQ_EPILOGUE();
 }
@@ -88,18 +88,18 @@ void hal_lld_init(void) {
   INTC.CPR.R        = 0;
   INTC.IACKR.R      = (uint32_t)_vectors;
 
-  /* PIT channel 3 initialization for Kernel ticks, the PIT is configured
+  /* PIT channel 0 initialization for Kernel ticks, the PIT is configured
      to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
      modes.*/
-  INTC.PSR[127].R   = SPC5_PIT0_IRQ_PRIORITY;
+  INTC.PSR[59].R    = SPC5_PIT0_IRQ_PRIORITY;
   halSPCSetPeripheralClockMode(92,
-                                   SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
+                               SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
   reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
   PIT.PITMCR.R      = 1;        /* PIT clock enabled, stop while debugging. */
-  PIT.CH[3].LDVAL.R = reg;
-  PIT.CH[3].CVAL.R  = reg;
-  PIT.CH[3].TFLG.R  = 1;        /* Interrupt flag cleared.                  */
-  PIT.CH[3].TCTRL.R = 3;        /* Timer active, interrupt enabled.         */
+  PIT.CH[0].LDVAL.R = reg;
+  PIT.CH[0].CVAL.R  = reg;
+  PIT.CH[0].TFLG.R  = 1;        /* Interrupt flag cleared.                  */
+  PIT.CH[0].TCTRL.R = 3;        /* Timer active, interrupt enabled.         */
 }
 
 /**
diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.c b/os/hal/platforms/SPC560Pxx/hal_lld.c
index 5d3402703..433a9f429 100644
--- a/os/hal/platforms/SPC560Pxx/hal_lld.c
+++ b/os/hal/platforms/SPC560Pxx/hal_lld.c
@@ -50,7 +50,7 @@
  *
  * @isr
  */
-CH_IRQ_HANDLER(vector127) {
+CH_IRQ_HANDLER(vector59) {
 
   CH_IRQ_PROLOGUE();
 
@@ -59,7 +59,7 @@ CH_IRQ_HANDLER(vector127) {
   chSysUnlockFromIsr();
 
   /* Resets the PIT channel 3 IRQ flag.*/
-  PIT.CH[3].TFLG.R = 1;
+  PIT.CH[0].TFLG.R = 1;
 
   CH_IRQ_EPILOGUE();
 }
@@ -88,18 +88,18 @@ void hal_lld_init(void) {
   INTC.CPR.R        = 0;
   INTC.IACKR.R      = (uint32_t)_vectors;
 
-  /* PIT channel 3 initialization for Kernel ticks, the PIT is configured
+  /* PIT channel 0 initialization for Kernel ticks, the PIT is configured
      to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other
      modes.*/
-  INTC.PSR[127].R   = SPC5_PIT3_IRQ_PRIORITY;
+  INTC.PSR[59].R    = SPC5_PIT0_IRQ_PRIORITY;
   halSPCSetPeripheralClockMode(92,
-                                   SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
+                               SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
   reg = halSPCGetSystemClock() / CH_FREQUENCY - 1;
   PIT.PITMCR.R      = 1;        /* PIT clock enabled, stop while debugging. */
-  PIT.CH[3].LDVAL.R = reg;
-  PIT.CH[3].CVAL.R  = reg;
-  PIT.CH[3].TFLG.R  = 1;        /* Interrupt flag cleared.                  */
-  PIT.CH[3].TCTRL.R = 3;        /* Timer active, interrupt enabled.         */
+  PIT.CH[0].LDVAL.R = reg;
+  PIT.CH[0].CVAL.R  = reg;
+  PIT.CH[0].TFLG.R  = 1;        /* Interrupt flag cleared.                  */
+  PIT.CH[0].TCTRL.R = 3;        /* Timer active, interrupt enabled.         */
 }
 
 /**
diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.h b/os/hal/platforms/SPC560Pxx/hal_lld.h
index 7095cf0c4..b1066ce9d 100644
--- a/os/hal/platforms/SPC560Pxx/hal_lld.h
+++ b/os/hal/platforms/SPC560Pxx/hal_lld.h
@@ -582,12 +582,12 @@
 #endif
 
 /**
- * @brief   PIT channel 3 IRQ priority.
+ * @brief   PIT channel 0 IRQ priority.
  * @note    This PIT channel is allocated permanently for system tick
  *          generation.
  */
-#if !defined(SPC5_PIT3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define SPC5_PIT3_IRQ_PRIORITY              4
+#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define SPC5_PIT0_IRQ_PRIORITY              4
 #endif
 
 /*===========================================================================*/
-- 
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