From 78e38625943412e0849142b757ced4aa99b9d7d9 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 12 Dec 2012 09:41:58 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4905 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/SPC560BCxx/spc560bc_registry.h | 15 +- os/hal/platforms/SPC560Pxx/spc560p_registry.h | 11 +- os/hal/platforms/SPC563Mxx/platform.mk | 6 +- os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c | 16 +- os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h | 9 +- os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c | 171 ++++++++++ os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h | 411 ++++++++++++++++++++++++ 7 files changed, 609 insertions(+), 30 deletions(-) create mode 100644 os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c create mode 100644 os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h (limited to 'os/hal/platforms') diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h index ab78c3bf9..85ad4adc4 100644 --- a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h +++ b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h @@ -68,14 +68,13 @@ #define SPC5_LINFLEX3_TXI_NUMBER 123 #define SPC5_LINFLEX3_ERR_NUMBER 124 -/* SIU/SIUL attributes.*/ -#define SPC5_HAS_SIU TRUE -#define SPC5_SIU_PCTL 68 -#define SPC5_SIU_SUPPORTS_PORTS TRUE -#define SPC5_SIU_NUM_PORTS 8 -#define SPC5_SIU_NUM_PCRS 123 -#define SPC5_SIU_NUM_PADSELS 32 -#define SPC5_SIU_SYSTEM_PINS 32,33,121,122 +/* SIUL attributes.*/ +#define SPC5_HAS_SIUL TRUE +#define SPC5_SIUL_PCTL 68 +#define SPC5_SIUL_NUM_PORTS 8 +#define SPC5_SIUL_NUM_PCRS 123 +#define SPC5_SIUL_NUM_PADSELS 32 +#define SPC5_SIUL_SYSTEM_PINS 32,33,121,122 /** @} */ #endif /* _SPC560BC_REGISTRY_H_ */ diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h index 86536e11a..a4c962879 100644 --- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h +++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h @@ -54,12 +54,11 @@ #define SPC5_HAS_LINFLEX3 FALSE -/* SIU/SIUL attributes.*/ -#define SPC5_HAS_SIU TRUE -#define SPC5_SIU_SUPPORTS_PORTS TRUE -#define SPC5_SIU_NUM_PORTS 8 -#define SPC5_SIU_NUM_PCRS 108 -#define SPC5_SIU_NUM_PADSELS 36 +/* SIUL attributes.*/ +#define SPC5_HAS_SIUL TRUE +#define SPC5_SIUL_NUM_PORTS 8 +#define SPC5_SIUL_NUM_PCRS 108 +#define SPC5_SIUL_NUM_PADSELS 36 /** @} */ #endif /* _SPC560P_REGISTRY_H_ */ diff --git a/os/hal/platforms/SPC563Mxx/platform.mk b/os/hal/platforms/SPC563Mxx/platform.mk index a5ae689fe..d70bad232 100644 --- a/os/hal/platforms/SPC563Mxx/platform.mk +++ b/os/hal/platforms/SPC563Mxx/platform.mk @@ -1,7 +1,9 @@ # List of all the SPC56x platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC563Mxx/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c + ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c # Required include directories PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC563Mxx \ - ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1 + ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCI_v1 \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 diff --git a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c index 8cd8b2bd3..a5354f431 100644 --- a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c +++ b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c @@ -14,7 +14,7 @@ /** * @file SPC5xx/SIUL_v1/pal_lld.c - * @brief SPC5xx SIU/SIUL low level driver code. + * @brief SPC5xx SIUL low level driver code. * * @addtogroup PAL * @{ @@ -37,8 +37,8 @@ /* Driver local variables. */ /*===========================================================================*/ -#if defined(SPC5_SIU_SYSTEM_PINS) -static const unsigned system_pins[] = {SPC5_SIU_SYSTEM_PINS}; +#if defined(SPC5_SIUL_SYSTEM_PINS) +static const unsigned system_pins[] = {SPC5_SIUL_SYSTEM_PINS}; #endif /*===========================================================================*/ @@ -63,15 +63,15 @@ static const unsigned system_pins[] = {SPC5_SIU_SYSTEM_PINS}; void _pal_lld_init(const PALConfig *config) { unsigned i; -#if defined(SPC5_SIU_PCTL) +#if defined(SPC5_SIUL_PCTL) /* SIUL clock gating if present.*/ - halSPCSetPeripheralClockMode(SPC5_SIU_PCTL, + halSPCSetPeripheralClockMode(SPC5_SIUL_PCTL, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); #endif /* Initialize PCR registers for undefined pads.*/ - for (i = 0; i < SPC5_SIU_NUM_PCRS; i++) { -#if defined(SPC5_SIU_SYSTEM_PINS) + for (i = 0; i < SPC5_SIUL_NUM_PCRS; i++) { +#if defined(SPC5_SIUL_SYSTEM_PINS) /* Handling the case where some SIU pins are not meant to be reprogrammed, for example JTAG pins.*/ unsigned j; @@ -88,7 +88,7 @@ skip: } /* Initialize PADSEL registers.*/ - for (i = 0; i < SPC5_SIU_NUM_PADSELS; i++) + for (i = 0; i < SPC5_SIUL_NUM_PADSELS; i++) SIU.PSMI[i].R = config->padsels[i]; /* Initialize PCR registers for defined pads.*/ diff --git a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h index 32b54d260..6eb250249 100644 --- a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h +++ b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h @@ -14,7 +14,7 @@ /** * @file SPC5xx/SIUL_v1/pal_lld.h - * @brief SPC5xx SIU/SIUL low level driver header. + * @brief SPC5xx SIUL low level driver header. * * @addtogroup PAL * @{ @@ -39,7 +39,7 @@ #undef PAL_MODE_OUTPUT_OPENDRAIN /** - * @name SIU/SIUL-specific PAL modes + * @name SIUL-specific PAL modes * @{ */ #define PAL_SPC5_SMC (1U << 14) @@ -141,7 +141,7 @@ typedef uint16_t iomode_t; typedef uint32_t ioportid_t; /** - * @brief SIU/SIUL register initializer type. + * @brief SIUL register initializer type. */ typedef struct { uint8_t pcr_index; @@ -232,7 +232,6 @@ typedef struct { */ #define pal_lld_init(config) _pal_lld_init(config) -#if SPC5_SIU_SUPPORTS_PORTS || defined(__DOXYGEN__) /** * @brief Reads the physical I/O port states. * @@ -293,8 +292,6 @@ typedef struct { #define pal_lld_writegroup(port, mask, offset, bits) \ _pal_lld_writegroup(port, mask, offset, bits) -#endif /* SPC5_SIU_SUPPORTS_PORTS */ - /** * @brief Pads group mode setup. * @details This function programs a pads group belonging to the same port diff --git a/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c b/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c new file mode 100644 index 000000000..8cd8b2bd3 --- /dev/null +++ b/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.c @@ -0,0 +1,171 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file SPC5xx/SIUL_v1/pal_lld.c + * @brief SPC5xx SIU/SIUL low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +#if defined(SPC5_SIU_SYSTEM_PINS) +static const unsigned system_pins[] = {SPC5_SIU_SYSTEM_PINS}; +#endif + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief SPC5xx I/O ports configuration. + * + * @param[in] config the STM32 ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + unsigned i; + +#if defined(SPC5_SIU_PCTL) + /* SIUL clock gating if present.*/ + halSPCSetPeripheralClockMode(SPC5_SIU_PCTL, + SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); +#endif + + /* Initialize PCR registers for undefined pads.*/ + for (i = 0; i < SPC5_SIU_NUM_PCRS; i++) { +#if defined(SPC5_SIU_SYSTEM_PINS) + /* Handling the case where some SIU pins are not meant to be reprogrammed, + for example JTAG pins.*/ + unsigned j; + for (j = 0; j < sizeof system_pins; j++) { + if (i == system_pins[j]) + goto skip; + } + SIU.PCR[i].R = config->default_mode; +skip: + ; +#else + SIU.PCR[i].R = config->default_mode; +#endif + } + + /* Initialize PADSEL registers.*/ + for (i = 0; i < SPC5_SIU_NUM_PADSELS; i++) + SIU.PSMI[i].R = config->padsels[i]; + + /* Initialize PCR registers for defined pads.*/ + i = 0; + while (config->inits[i].pcr_value != 0) { + SIU.GPDO[config->inits[i].pcr_index].R = config->inits[i].gpdo_value; + SIU.PCR[config->inits[i].pcr_index].R = config->inits[i].pcr_value; + i++; + } +} + +/** + * @brief Reads a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +ioportmask_t _pal_lld_readgroup(ioportid_t port, + ioportmask_t mask, + uint_fast8_t offset) { + + (void)port; + (void)mask; + (void)offset; + return 0; +} + +/** + * @brief Writes a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +void _pal_lld_writegroup(ioportid_t port, + ioportmask_t mask, + uint_fast8_t offset, + ioportmask_t bits) { + + (void)port; + (void)mask; + (void)offset; + (void)bits; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + unsigned pcr_index = (unsigned)(port * PAL_IOPORTS_WIDTH); + ioportmask_t m1 = 0x8000; + while (m1) { + if (mask & m1) + SIU.PCR[pcr_index].R = mode; + m1 >>= 1; + ++pcr_index; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h b/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h new file mode 100644 index 000000000..32b54d260 --- /dev/null +++ b/os/hal/platforms/SPC5xx/SIU_v1/pal_lld.h @@ -0,0 +1,411 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file SPC5xx/SIUL_v1/pal_lld.h + * @brief SPC5xx SIU/SIUL low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name SIU/SIUL-specific PAL modes + * @{ + */ +#define PAL_SPC5_SMC (1U << 14) +#define PAL_SPC5_APC (1U << 13) +#define PAL_SPC5_PA_MASK (3U << 10) +#define PAL_SPC5_PA(n) ((n) << 10) +#define PAL_SPC5_OBE (1U << 9) +#define PAL_SPC5_IBE (1U << 8) +#define PAL_SPC5_ODE (1U << 5) +#define PAL_SPC5_SRC (1U << 2) +#define PAL_SPC5_WPE (1U << 1) +#define PAL_SPC5_WPS (1U << 0) +/** @} */ + +/** + * @name Pads mode constants + * @{ + */ +/** + * @brief After reset state. + */ +#define PAL_MODE_RESET 0 + +/** + * @brief Safe state for unconnected pads. + */ +#define PAL_MODE_UNCONNECTED (PAL_SPC5_WPE | PAL_SPC5_WPS) + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT (PAL_SPC5_IBE) + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_SPC5_IBE |PAL_SPC5_WPE | \ + PAL_SPC5_WPS) + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_SPC5_IBE |PAL_SPC5_WPE) + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG PAL_SPC5_APC + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_SPC5_IBE | PAL_SPC5_OBE) + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_SPC5_IBE | PAL_SPC5_OBE | \ + PAL_SPC5_ODE) + +/** + * @brief Alternate "n" output pad. + */ +#define PAL_MODE_OUTPUT_ALTERNATE(n) (PAL_SPC5_IBE | PAL_SPC5_OBE | \ + PAL_SPC5_PA(n)) +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint16_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint16_t iomode_t; + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ +typedef uint32_t ioportid_t; + +/** + * @brief SIU/SIUL register initializer type. + */ +typedef struct { + uint8_t pcr_index; + uint8_t gpdo_value; + iomode_t pcr_value; +} spc_siu_init_t; + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note Implementations may extend this structure to contain more, + * architecture dependent, fields. + */ +typedef struct { + iomode_t default_mode; + const spc_siu_init_t *inits; + const uint8_t *padsels; +} PALConfig; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief I/O port A identifier. + */ +#define PA 0 + +/** + * @brief I/O port B identifier. + */ +#define PB 1 + +/** + * @brief I/O port C identifier. + */ +#define PC 2 + +/** + * @brief I/O port D identifier. + */ +#define PD 3 + +/** + * @brief I/O port E identifier. + */ +#define PE 4 + +/** + * @brief I/O port F identifier. + */ +#define PF 5 + +/** + * @brief I/O port G identifier. + */ +#define PG 6 + +/** + * @brief I/O port H identifier. + */ +#define PH 7 + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Port bit helper macro. + * @note Overrides the one in @p pal.h. + * + * @param[in] n bit position within the port + * + * @return The bit mask. + */ +#define PAL_PORT_BIT(n) ((ioportmask_t)(0x8000U >> (n))) + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +#if SPC5_SIU_SUPPORTS_PORTS || defined(__DOXYGEN__) +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) (((volatile uint16_t *)SIU.PGPDI)[port]) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) (((volatile uint16_t *)SIU.PGPDO)[port]) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) \ + (((volatile uint16_t *)SIU.PGPDO)[port] = (bits)) + +/** + * @brief Reads a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) \ + _pal_lld_readgroup(port, mask, offset) + +/** + * @brief Writes a group of bits. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + _pal_lld_writegroup(port, mask, offset, bits) + +#endif /* SPC5_SIU_SUPPORTS_PORTS */ + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) \ + (SIU.GPDI[((port) * 16) + (pad)].R) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + (SIU.GPDO[((port) * 16) + (pad)].R = (bit)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + (SIU.GPDO[((port) * 16) + (pad)].R = 1) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + (SIU.GPDO[((port) * 16) + (pad)].R = 0) + +/** + * @brief Pad mode setup. + * @details This function programs a pad with the specified mode. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad mode + * + * @notapi + */ +#define pal_lld_setpadmode(port, pad, mode) + +extern const PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + ioportmask_t _pal_lld_readgroup(ioportid_t port, + ioportmask_t mask, + uint_fast8_t offset); + void _pal_lld_writegroup(ioportid_t port, + ioportmask_t mask, + uint_fast8_t offset, + ioportmask_t bits); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ -- cgit v1.2.3