From 690fd6364bd682ade14f27e86cb3821c84524d78 Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 5 Mar 2012 16:44:56 +0000
Subject: SDC. Code merged to fresh branch.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/sdc_dev2@4021 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32/sdc_lld.c       | 647 +++++++++++++++++----------------
 os/hal/platforms/STM32/sdc_lld.h       |  85 ++++-
 os/hal/platforms/STM32F4xx/hal_lld.h   |   4 +
 os/hal/platforms/STM32F4xx/platform.mk |   5 +-
 os/hal/platforms/STM32F4xx/stm32_rcc.h |  33 ++
 5 files changed, 444 insertions(+), 330 deletions(-)

(limited to 'os/hal/platforms')

diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c
index 42883e3b0..f74d06c9e 100644
--- a/os/hal/platforms/STM32/sdc_lld.c
+++ b/os/hal/platforms/STM32/sdc_lld.c
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
@@ -26,6 +26,10 @@
  * @{
  */
 
+/*
+ TODO: Try preerase blocks before writing (ACMD23).
+ */
+
 #include <string.h>
 
 #include "ch.h"
@@ -33,6 +37,14 @@
 
 #if HAL_USE_SDC || defined(__DOXYGEN__)
 
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define DMA_CHANNEL                                                           \
+  STM32_DMA_GETCHANNEL(STM32_SDC_SDIO_DMA_STREAM,                             \
+                       STM32_SDC_SDIO_DMA_CHN)
+
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
@@ -59,330 +71,193 @@ static union {
 /*===========================================================================*/
 
 /**
- * @brief   Reads one or more blocks.
+ * @brief   Prepares card to handle read transaction.
  *
  * @param[in] sdcp      pointer to the @p SDCDriver object
  * @param[in] startblk  first block to read
- * @param[out] buf      pointer to the read buffer, it must be aligned to
- *                      four bytes boundary
  * @param[in] n         number of blocks to read
+ * @param[in] resp      pointer to the response buffer
+ *
  * @return              The operation status.
- * @retval FALSE        operation succeeded, the requested blocks have been
- *                      read.
- * @retval TRUE         operation failed, the state of the buffer is uncertain.
+ * @retval SDC_SUCCESS  operation succeeded.
+ * @retval SDC_FAILED   operation failed.
  *
  * @notapi
  */
-static bool_t sdc_lld_read_multiple(SDCDriver *sdcp, uint32_t startblk,
-                                    uint8_t *buf, uint32_t n) {
-  uint32_t resp[1];
-
-  /* Checks for errors and waits for the card to be ready for reading.*/
-  if (_sdc_wait_for_transfer_state(sdcp))
-    return TRUE;
-
-  /* Prepares the DMA channel for reading.*/
-  dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf);
-  dmaStreamSetTransactionSize(STM32_DMA2_STREAM4,
-                              (n * SDC_BLOCK_SIZE) / sizeof (uint32_t));
-  dmaStreamSetMode(STM32_DMA2_STREAM4,
-                   STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) |
-                   STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_PSIZE_WORD |
-                   STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC);
-
-  /* Setting up data transfer.
-     Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/
-  SDIO->ICR   = 0xFFFFFFFF;
-  SDIO->MASK  = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE |
-                SDIO_MASK_DATAENDIE | SDIO_MASK_STBITERRIE;
-  SDIO->DLEN  = n * SDC_BLOCK_SIZE;
-  SDIO->DCTRL = SDIO_DCTRL_DTDIR |
-                SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 |
-                SDIO_DCTRL_DMAEN |
-                SDIO_DCTRL_DTEN;
-
-  /* DMA channel activation.*/
-  dmaStreamEnable(STM32_DMA2_STREAM4);
+static bool_t sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk,
+                                   uint32_t n, uint32_t *resp){
 
-  /* Read multiple blocks command.*/
-  if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0)
+  /* Driver handles data in 512 bytes blocks (just like HC cards). But if we
+     have not HC card than we must convert address from blocks to bytes.*/
+  if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY))
     startblk *= SDC_BLOCK_SIZE;
-  if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_MULTIPLE_BLOCK,
-                                 startblk, resp) ||
-      SDC_R1_ERROR(resp[0]))
-    goto error;
 
-  chSysLock();
-  if (SDIO->MASK != 0) {
-    chDbgAssert(sdcp->thread == NULL,
-                "sdc_lld_read_multiple(), #1", "not NULL");
-    sdcp->thread = chThdSelf();
-    chSchGoSleepS(THD_STATE_SUSPENDED);
-    chDbgAssert(sdcp->thread == NULL,
-                "sdc_lld_read_multiple(), #2", "not NULL");
+  if (n > 1){
+    /* Send read multiple blocks command to card.*/
+    if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_MULTIPLE_BLOCK,
+                                   startblk, resp) || SDC_R1_ERROR(resp[0]))
+      return SDC_FAILED;
   }
-  if ((SDIO->STA & SDIO_STA_DATAEND) == 0) {
-    chSysUnlock();
-    goto error;
+  else{
+    /* Send read single block command.*/
+    if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_SINGLE_BLOCK,
+                                   startblk, resp) || SDC_R1_ERROR(resp[0]))
+      return SDC_FAILED;
   }
-  dmaStreamDisable(STM32_DMA2_STREAM4);
-  SDIO->ICR   = 0xFFFFFFFF;
-  SDIO->DCTRL = 0;
-  chSysUnlock();
 
-  return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp);
-error:
-  dmaStreamDisable(STM32_DMA2_STREAM4);
-  SDIO->ICR   = 0xFFFFFFFF;
-  SDIO->MASK  = 0;
-  SDIO->DCTRL = 0;
-  return TRUE;
+  return SDC_SUCCESS;
 }
 
 /**
- * @brief   Reads one block.
+ * @brief   Prepares card to handle write transaction.
  *
  * @param[in] sdcp      pointer to the @p SDCDriver object
  * @param[in] startblk  first block to read
- * @param[out] buf      pointer to the read buffer, it must be aligned to
- *                      four bytes boundary
+ * @param[in] n         number of blocks to write
+ * @param[in] resp      pointer to the response buffer
+ *
  * @return              The operation status.
- * @retval FALSE        operation succeeded, the requested blocks have been
- *                      read.
- * @retval TRUE         operation failed, the state of the buffer is uncertain.
+ * @retval SDC_SUCCESS  operation succeeded.
+ * @retval SDC_FAILED   operation failed.
  *
  * @notapi
  */
-static bool_t sdc_lld_read_single(SDCDriver *sdcp, uint32_t startblk,
-                                  uint8_t *buf) {
-  uint32_t resp[1];
+static bool_t sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk,
+                                    uint32_t n, uint32_t *resp){
 
-  /* Checks for errors and waits for the card to be ready for reading.*/
-  if (_sdc_wait_for_transfer_state(sdcp))
-    return TRUE;
-
-  /* Prepares the DMA channel for reading.*/
-  dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf);
-  dmaStreamSetTransactionSize(STM32_DMA2_STREAM4,
-                              SDC_BLOCK_SIZE / sizeof (uint32_t));
-  dmaStreamSetMode(STM32_DMA2_STREAM4,
-                   STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) |
-                   STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_PSIZE_WORD |
-                   STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC);
-
-  /* Setting up data transfer.
-     Options: Card to Controller, Block mode, DMA mode, 512 bytes blocks.*/
-  SDIO->ICR   = 0xFFFFFFFF;
-  SDIO->MASK  = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE |
-                SDIO_MASK_DATAENDIE | SDIO_MASK_STBITERRIE;
-  SDIO->DLEN  = SDC_BLOCK_SIZE;
-  SDIO->DCTRL = SDIO_DCTRL_DTDIR |
-                SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 |
-                SDIO_DCTRL_DMAEN |
-                SDIO_DCTRL_DTEN;
-
-  /* DMA channel activation.*/
-  dmaStreamEnable(STM32_DMA2_STREAM4);
-
-  /* Read single block command.*/
-  if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0)
+  /* Driver handles data in 512 bytes blocks (just like HC cards). But if we
+     have not HC card than we must convert address from blocks to bytes.*/
+  if (!(sdcp->cardmode & SDC_MODE_HIGH_CAPACITY))
     startblk *= SDC_BLOCK_SIZE;
-  if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_SINGLE_BLOCK,
-                                 startblk, resp) ||
-      SDC_R1_ERROR(resp[0]))
-    goto error;
 
-  chSysLock();
-  if (SDIO->MASK != 0) {
-    chDbgAssert(sdcp->thread == NULL,
-                "sdc_lld_read_single(), #1", "not NULL");
-    sdcp->thread = chThdSelf();
-    chSchGoSleepS(THD_STATE_SUSPENDED);
-    chDbgAssert(sdcp->thread == NULL,
-                "sdc_lld_read_single(), #2", "not NULL");
+  if (n > 1){
+    /* Write multiple blocks command.*/
+    if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_MULTIPLE_BLOCK,
+                                   startblk, resp) || SDC_R1_ERROR(resp[0]))
+      return SDC_FAILED;
   }
-  if ((SDIO->STA & SDIO_STA_DATAEND) == 0) {
-    chSysUnlock();
-    goto error;
+  else{
+    /* Write single block command.*/
+    if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_BLOCK,
+                                   startblk, resp) || SDC_R1_ERROR(resp[0]))
+      return SDC_FAILED;
   }
-  dmaStreamDisable(STM32_DMA2_STREAM4);
-  SDIO->ICR   = 0xFFFFFFFF;
-  SDIO->DCTRL = 0;
-  chSysUnlock();
 
-  return FALSE;
-error:
-  dmaStreamDisable(STM32_DMA2_STREAM4);
-  SDIO->ICR   = 0xFFFFFFFF;
-  SDIO->MASK  = 0;
-  SDIO->DCTRL = 0;
-  return TRUE;
+  return SDC_SUCCESS;
 }
 
 /**
- * @brief   Writes one or more blocks.
+ * @brief   Wait end of data transaction and performs finalizations.
  *
  * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] startblk  first block to write
- * @param[out] buf      pointer to the write buffer, it must be aligned to
- *                      four bytes boundary
- * @param[in] n         number of blocks to write
- * @return              The operation status.
- * @retval FALSE        operation succeeded, the requested blocks have been
- *                      written.
- * @retval TRUE         operation failed.
+ * @param[in] n         number of blocks in transaction
+ * @param[in] resp      pointer to the response buffer
  *
- * @notapi
+ * @return              The operation status.
+ * @retval SDC_SUCCESS  operation succeeded.
+ * @retval SDC_FAILED   operation failed.
  */
-static bool_t sdc_lld_write_multiple(SDCDriver *sdcp, uint32_t startblk,
-                              const uint8_t *buf, uint32_t n) {
-  uint32_t resp[1];
-
-  /* Checks for errors and waits for the card to be ready for writing.*/
-  if (_sdc_wait_for_transfer_state(sdcp))
-    return TRUE;
-
-  /* Prepares the DMA channel for writing.*/
-  dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf);
-  dmaStreamSetTransactionSize(STM32_DMA2_STREAM4,
-                              (n * SDC_BLOCK_SIZE) / sizeof (uint32_t));
-  dmaStreamSetMode(STM32_DMA2_STREAM4,
-                   STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) |
-                   STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_PSIZE_WORD |
-                   STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC);
-
-  /* Write multiple blocks command.*/
-  if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0)
-    startblk *= SDC_BLOCK_SIZE;
-  if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_MULTIPLE_BLOCK,
-                                 startblk, resp) ||
-      SDC_R1_ERROR(resp[0]))
-    return TRUE;
-
-  /* Setting up data transfer.
-     Options: Controller to Card, Block mode, DMA mode, 512 bytes blocks.*/
-  SDIO->ICR   = 0xFFFFFFFF;
-  SDIO->MASK  = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE |
-                SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE |
-                SDIO_MASK_STBITERRIE;
-  SDIO->DLEN  = n * SDC_BLOCK_SIZE;
-  SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 |
-                SDIO_DCTRL_DMAEN |
-                SDIO_DCTRL_DTEN;
-
-  /* DMA channel activation.*/
-  dmaStreamEnable(STM32_DMA2_STREAM4);
+static bool_t sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n,
+                                           uint32_t *resp){
 
   /* Note the mask is checked before going to sleep because the interrupt
      may have occurred before reaching the critical zone.*/
   chSysLock();
   if (SDIO->MASK != 0) {
     chDbgAssert(sdcp->thread == NULL,
-                "sdc_lld_write_multiple(), #1", "not NULL");
+                "sdc_lld_start_data_transaction(), #1", "not NULL");
     sdcp->thread = chThdSelf();
     chSchGoSleepS(THD_STATE_SUSPENDED);
     chDbgAssert(sdcp->thread == NULL,
-                "sdc_lld_write_multiple(), #2", "not NULL");
+                "sdc_lld_start_data_transaction(), #2", "not NULL");
   }
   if ((SDIO->STA & SDIO_STA_DATAEND) == 0) {
     chSysUnlock();
-    goto error;
+    return SDC_FAILED;
   }
-  dmaStreamDisable(STM32_DMA2_STREAM4);
-  SDIO->ICR   = 0xFFFFFFFF;
+
+  /* Wait until DMA channel enabled to be sure that all data transferred.*/
+  while (sdcp->dma->stream->CR & STM32_DMA_CR_EN)
+    ;
+
+  /* DMA event flags must be manually cleared.*/
+  dmaStreamClearInterrupt(sdcp->dma);
+
+  SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS;
   SDIO->DCTRL = 0;
   chSysUnlock();
 
-  return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp);
-error:
-  dmaStreamDisable(STM32_DMA2_STREAM4);
-  SDIO->ICR   = 0xFFFFFFFF;
-  SDIO->MASK  = 0;
-  SDIO->DCTRL = 0;
-  return TRUE;
+  /* Wait until interrupt flags to be cleared.*/
+  while (((DMA2->LISR) >> (sdcp->dma->ishift)) & STM32_DMA_ISR_TCIF)
+    dmaStreamClearInterrupt(sdcp->dma);
+
+  /* Finalize transaction.*/
+  if (n > 1)
+    return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp);
+  else
+    return SDC_SUCCESS;
 }
 
 /**
- * @brief   Writes one block.
+ * @brief   Gets SDC errors.
  *
  * @param[in] sdcp      pointer to the @p SDCDriver object
- * @param[in] startblk  first block to write
- * @param[out] buf      pointer to the write buffer, it must be aligned to
- *                      four bytes boundary
- * @param[in] n         number of blocks to write
- * @return              The operation status.
- * @retval FALSE        operation succeeded, the requested blocks have been
- *                      written.
- * @retval TRUE         operation failed.
  *
  * @notapi
  */
-static bool_t sdc_lld_write_single(SDCDriver *sdcp, uint32_t startblk,
-                            const uint8_t *buf) {
-  uint32_t resp[1];
+static void sdc_lld_collect_errors(SDCDriver *sdcp) {
+  uint32_t errors = SDC_NO_ERROR;
 
-  /* Checks for errors and waits for the card to be ready for writing.*/
-  if (_sdc_wait_for_transfer_state(sdcp))
-    return TRUE;
-
-  /* Prepares the DMA channel for writing.*/
-  dmaStreamSetMemory0(STM32_DMA2_STREAM4, buf);
-  dmaStreamSetTransactionSize(STM32_DMA2_STREAM4,
-                              SDC_BLOCK_SIZE / sizeof (uint32_t));
-  dmaStreamSetMode(STM32_DMA2_STREAM4,
-                   STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) |
-                   STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_PSIZE_WORD |
-                   STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC);
-
-  /* Write single block command.*/
-  if ((sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) == 0)
-    startblk *= SDC_BLOCK_SIZE;
-  if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_BLOCK,
-                                 startblk, resp) ||
-      SDC_R1_ERROR(resp[0]))
-    return TRUE;
-
-  /* Setting up data transfer.
-     Options: Controller to Card, Block mode, DMA mode, 512 bytes blocks.*/
-  SDIO->ICR   = 0xFFFFFFFF;
-  SDIO->MASK  = SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE |
-                SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE |
-                SDIO_MASK_STBITERRIE;
-  SDIO->DLEN  = SDC_BLOCK_SIZE;
-  SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 | SDIO_DCTRL_DBLOCKSIZE_0 |
-                SDIO_DCTRL_DMAEN |
-                SDIO_DCTRL_DTEN;
-
-  /* DMA channel activation.*/
-  dmaStreamEnable(STM32_DMA2_STREAM4);
-
-  /* Note the mask is checked before going to sleep because the interrupt
-     may have occurred before reaching the critical zone.*/
-  chSysLock();
-  if (SDIO->MASK != 0) {
-    chDbgAssert(sdcp->thread == NULL,
-                "sdc_lld_write_single(), #1", "not NULL");
-    sdcp->thread = chThdSelf();
-    chSchGoSleepS(THD_STATE_SUSPENDED);
-    chDbgAssert(sdcp->thread == NULL,
-                "sdc_lld_write_single(), #2", "not NULL");
+  if (SDIO->STA & SDIO_STA_CCRCFAIL){
+    SDIO->ICR |= SDIO_ICR_CCRCFAILC;
+    errors |= SDC_CMD_CRC_ERROR;
   }
-  if ((SDIO->STA & SDIO_STA_DATAEND) == 0) {
-    chSysUnlock();
-    goto error;
+  if (SDIO->STA & SDIO_STA_DCRCFAIL){
+    SDIO->ICR |= SDIO_ICR_DCRCFAILC;
+    errors |= SDC_DATA_CRC_ERROR;
+  }
+  if (SDIO->STA & SDIO_STA_CTIMEOUT){
+    SDIO->ICR |= SDIO_ICR_CTIMEOUTC;
+    errors |= SDC_COMMAND_TIMEOUT;
+  }
+  if (SDIO->STA & SDIO_STA_DTIMEOUT){
+    SDIO->ICR |= SDIO_ICR_CTIMEOUTC;
+    errors |= SDC_DATA_TIMEOUT;
+  }
+  if (SDIO->STA & SDIO_STA_TXUNDERR){
+    SDIO->ICR |= SDIO_ICR_TXUNDERRC;
+    errors |= SDC_TX_UNDERRUN;
+  }
+  if (SDIO->STA & SDIO_STA_RXOVERR){
+    SDIO->ICR |= SDIO_ICR_RXOVERRC;
+    errors |= SDC_RX_OVERRUN;
+  }
+  if (SDIO->STA & SDIO_STA_STBITERR){
+    SDIO->ICR |= SDIO_ICR_STBITERRC;
+    errors |= SDC_STARTBIT_ERROR;
   }
-  dmaStreamDisable(STM32_DMA2_STREAM4);
-  SDIO->ICR   = 0xFFFFFFFF;
-  SDIO->DCTRL = 0;
-  chSysUnlock();
 
-  return FALSE;
-error:
-  dmaStreamDisable(STM32_DMA2_STREAM4);
-  SDIO->ICR   = 0xFFFFFFFF;
+  sdcp->errors |= errors;
+}
+
+/**
+ * @brief   Performs clean transaction stopping in case of errors.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] n         number of blocks in transaction
+ * @param[in] resp      pointer to the response buffer
+ *
+ * @notapi
+ */
+static void sdc_lld_error_cleanup(SDCDriver *sdcp, uint32_t n, uint32_t *resp){
+  dmaStreamClearInterrupt(sdcp->dma);
+  dmaStreamDisable(sdcp->dma);
+  SDIO->ICR   = STM32_SDIO_ICR_ALL_FLAGS;
   SDIO->MASK  = 0;
   SDIO->DCTRL = 0;
-  return TRUE;
+  sdc_lld_collect_errors(sdcp);
+  if (n > 1)
+    sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp);
 }
 
 /*===========================================================================*/
@@ -391,6 +266,8 @@ error:
 
 /**
  * @brief   SDIO IRQ handler.
+ * @details It just wakes transaction thread. All error  handling performs in
+ *          that thread.
  *
  * @isr
  */
@@ -398,17 +275,18 @@ CH_IRQ_HANDLER(SDIO_IRQHandler) {
 
   CH_IRQ_PROLOGUE();
 
-  chSysLockFromIsr();
-  if (SDCD1.thread != NULL) {
-    chSchReadyI(SDCD1.thread);
-    SDCD1.thread = NULL;
-  }
-  chSysUnlockFromIsr();
+  chSysLockFromIsr()
 
   /* Disables the source but the status flags are not reset because the
-     read/write functions need to check them.*/
+     read/write functions needs to check them.*/
   SDIO->MASK = 0;
 
+  if (SDCD1.thread != NULL) {
+    chSchReadyI(SDCD1.thread);
+    SDCD1.thread = NULL;
  }
+
+  chSysUnlockFromIsr();
+
   CH_IRQ_EPILOGUE();
 }
 
@@ -425,31 +303,52 @@ void sdc_lld_init(void) {
 
   sdcObjectInit(&SDCD1);
   SDCD1.thread = NULL;
+  SDCD1.dma    = STM32_DMA_STREAM(STM32_SDC_SDIO_DMA_STREAM);
+#if CH_DBG_ENABLE_ASSERTS
+  SDCD1.sdio   = SDIO;
+#endif
 }
 
 /**
  * @brief   Configures and activates the SDC peripheral.
  *
- * @param[in] sdcp      pointer to the @p SDCDriver object, must be @p NULL,
- *                      this driver does not require any configuration
+ * @param[in] sdcp      pointer to the @p SDCDriver object
  *
  * @notapi
  */
 void sdc_lld_start(SDCDriver *sdcp) {
 
+  sdcp->dmamode = STM32_DMA_CR_CHSEL(DMA_CHANNEL) |
+                  STM32_DMA_CR_PL(STM32_SDC_SDIO_DMA_PRIORITY) |
+                  STM32_DMA_CR_PSIZE_WORD |
+                  STM32_DMA_CR_MSIZE_WORD |
+                  STM32_DMA_CR_MINC;
+
+  #if (defined(STM32F4XX) || defined(STM32F2XX))
+    sdcp->dmamode |= STM32_DMA_CR_PFCTRL |
+                     STM32_DMA_CR_PBURST_INCR4 |
+                     STM32_DMA_CR_MBURST_INCR4;
+  #endif
+
   if (sdcp->state == SDC_STOP) {
     /* Note, the DMA must be enabled before the IRQs.*/
-    dmaStreamAllocate(STM32_DMA2_STREAM4, 0, NULL, NULL);
-    dmaStreamSetPeripheral(STM32_DMA2_STREAM4, &SDIO->FIFO);
+    bool_t b;
+    b = dmaStreamAllocate(sdcp->dma, STM32_SDC_SDIO_IRQ_PRIORITY, NULL, NULL);
+    chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated");
+    dmaStreamSetPeripheral(sdcp->dma, &SDIO->FIFO);
+    #if (defined(STM32F4XX) || defined(STM32F2XX))
+      dmaStreamSetFIFO(sdcp->dma, STM32_DMA_FCR_DMDIS | STM32_DMA_FCR_FTH_FULL);
+    #endif
     nvicEnableVector(SDIO_IRQn,
                      CORTEX_PRIORITY_MASK(STM32_SDC_SDIO_IRQ_PRIORITY));
     rccEnableSDIO(FALSE);
   }
+
   /* Configuration, card clock is initially stopped.*/
   SDIO->POWER  = 0;
   SDIO->CLKCR  = 0;
   SDIO->DCTRL  = 0;
-  SDIO->DTIMER = STM32_SDC_DATATIMEOUT;
+  SDIO->DTIMER = 0;
 }
 
 /**
@@ -469,7 +368,7 @@ void sdc_lld_stop(SDCDriver *sdcp) {
 
     /* Clock deactivation.*/
     nvicDisableVector(SDIO_IRQn);
-    dmaStreamRelease(STM32_DMA2_STREAM4);
+    dmaStreamRelease(sdcp->dma);
     rccDisableSDIO(FALSE);
   }
 }
@@ -538,6 +437,7 @@ void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {
     break;
   case SDC_MODE_8BIT:
     SDIO->CLKCR = clk | SDIO_CLKCR_WIDBUS_1;
+    break;
   }
 }
 
@@ -568,10 +468,10 @@ void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
  * @param[in] cmd       card command
  * @param[in] arg       command argument
  * @param[out] resp     pointer to the response buffer (one word)
+ *
  * @return              The operation status.
- * @retval FALSE        the operation succeeded.
- * @retval TRUE         the operation failed because timeout, CRC check or
- *                      other errors.
+ * @retval SDC_SUCCESS  operation succeeded.
+ * @retval SDC_FAILED   operation failed.
  *
  * @notapi
  */
@@ -586,10 +486,12 @@ bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
                                SDIO_STA_CCRCFAIL)) == 0)
     ;
   SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC;
-  if ((sta & (SDIO_STA_CTIMEOUT)) != 0)
-    return TRUE;
+  if ((sta & (SDIO_STA_CTIMEOUT)) != 0){
+    sdc_lld_collect_errors(sdcp);
+    return SDC_FAILED;
+  }
   *resp = SDIO->RESP1;
-  return FALSE;
+  return SDC_SUCCESS;
 }
 
 /**
@@ -599,10 +501,10 @@ bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
  * @param[in] cmd       card command
  * @param[in] arg       command argument
  * @param[out] resp     pointer to the response buffer (one word)
+ *
  * @return              The operation status.
- * @retval FALSE        the operation succeeded.
- * @retval TRUE         the operation failed because timeout, CRC check or
- *                      other errors.
+ * @retval SDC_SUCCESS  operation succeeded.
+ * @retval SDC_FAILED   operation failed.
  *
  * @notapi
  */
@@ -617,10 +519,12 @@ bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
                                SDIO_STA_CCRCFAIL)) == 0)
     ;
   SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC;
-  if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0)
-    return TRUE;
+  if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0){
+    sdc_lld_collect_errors(sdcp);
+    return SDC_FAILED;
+  }
   *resp = SDIO->RESP1;
-  return FALSE;
+  return SDC_SUCCESS;
 }
 
 /**
@@ -630,10 +534,10 @@ bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
  * @param[in] cmd       card command
  * @param[in] arg       command argument
  * @param[out] resp     pointer to the response buffer (four words)
+ *
  * @return              The operation status.
- * @retval FALSE        the operation succeeded.
- * @retval TRUE         the operation failed because timeout, CRC check or
- *                      other errors.
+ * @retval SDC_SUCCESS  operation succeeded.
+ * @retval SDC_FAILED   operation failed.
  *
  * @notapi
  */
@@ -650,10 +554,16 @@ bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
                                SDIO_STA_CCRCFAIL)) == 0)
     ;
   SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC;
-  if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0)
-    return TRUE;
-  *resp = SDIO->RESP1;
-  return FALSE;
+  if ((sta & (STM32_SDIO_STA_ERROR_MASK)) != 0){
+    sdc_lld_collect_errors(sdcp);
+    return SDC_FAILED;
+  }
+  /* save bytes in reverse order because MSB in response comes first */
+  *resp++ = SDIO->RESP4;
+  *resp++ = SDIO->RESP3;
+  *resp++ = SDIO->RESP2;
+  *resp   = SDIO->RESP1;
+  return SDC_SUCCESS;
 }
 
 /**
@@ -663,10 +573,133 @@ bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
  * @param[in] startblk  first block to read
  * @param[out] buf      pointer to the read buffer
  * @param[in] n         number of blocks to read
+ *
  * @return              The operation status.
- * @retval FALSE        operation succeeded, the requested blocks have been
- *                      read.
- * @retval TRUE         operation failed, the state of the buffer is uncertain.
+ * @retval SDC_SUCCESS  operation succeeded.
+ * @retval SDC_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool_t sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
+                            uint8_t *buf, uint32_t n) {
+  uint32_t resp[1];
+
+  chDbgCheck((n < (0x1000000 / SDC_BLOCK_SIZE)), "max transaction size");
+
+  SDIO->DTIMER = STM32_SDC_READ_TIMEOUT;
+
+  /* Checks for errors and waits for the card to be ready for reading.*/
+  if (_sdc_wait_for_transfer_state(sdcp))
+    return SDC_FAILED;
+
+  /* Prepares the DMA channel for writing.*/
+  dmaStreamSetMemory0(sdcp->dma, buf);
+  dmaStreamSetTransactionSize(sdcp->dma,
+                              (n * SDC_BLOCK_SIZE) / sizeof (uint32_t));
+  dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_P2M);
+  dmaStreamEnable(sdcp->dma);
+
+  /* Setting up data transfer.*/
+  SDIO->ICR   = STM32_SDIO_ICR_ALL_FLAGS;
+  SDIO->MASK  = SDIO_MASK_DCRCFAILIE |
+                SDIO_MASK_DTIMEOUTIE |
+                SDIO_MASK_STBITERRIE |
+                SDIO_MASK_RXOVERRIE |
+                SDIO_MASK_DATAENDIE;
+  SDIO->DLEN  = n * SDC_BLOCK_SIZE;
+
+  /* Talk to card what we want from it.*/
+  if (sdc_lld_prepare_read(sdcp, startblk, n, resp) == SDC_FAILED)
+    goto error;
+
+  /* Transaction starts just after DTEN bit setting.*/
+  SDIO->DCTRL = SDIO_DCTRL_DTDIR |
+                SDIO_DCTRL_DBLOCKSIZE_3 |
+                SDIO_DCTRL_DBLOCKSIZE_0 |
+                SDIO_DCTRL_DMAEN |
+                SDIO_DCTRL_DTEN;
+  if (sdc_lld_wait_transaction_end(sdcp, n, resp) == SDC_FAILED)
+    goto error;
+  else
+    return SDC_SUCCESS;
+
+error:
+  sdc_lld_error_cleanup(sdcp, n, resp);
+  return SDC_FAILED;
+}
+
+/**
+ * @brief   Writes one or more blocks.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] startblk  first block to write
+ * @param[out] buf      pointer to the write buffer
+ * @param[in] n         number of blocks to write
+ *
+ * @return              The operation status.
+ * @retval SDC_SUCCESS  operation succeeded.
+ * @retval SDC_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool_t sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk,
+                             const uint8_t *buf, uint32_t n) {
+  uint32_t resp[1];
+
+  chDbgCheck((n < (0x1000000 / SDC_BLOCK_SIZE)), "max transaction size");
+
+  SDIO->DTIMER = STM32_SDC_WRITE_TIMEOUT;
+
+  /* Checks for errors and waits for the card to be ready for writing.*/
+  if (_sdc_wait_for_transfer_state(sdcp))
+    return SDC_FAILED;
+
+  /* Prepares the DMA channel for writing.*/
+  dmaStreamSetMemory0(sdcp->dma, buf);
+  dmaStreamSetTransactionSize(sdcp->dma,
+                              (n * SDC_BLOCK_SIZE) / sizeof (uint32_t));
+  dmaStreamSetMode(sdcp->dma, sdcp->dmamode | STM32_DMA_CR_DIR_M2P);
+  dmaStreamEnable(sdcp->dma);
+
+  /* Setting up data transfer.*/
+  SDIO->ICR   = STM32_SDIO_ICR_ALL_FLAGS;
+  SDIO->MASK  = SDIO_MASK_DCRCFAILIE |
+                SDIO_MASK_DTIMEOUTIE |
+                SDIO_MASK_STBITERRIE |
+                SDIO_MASK_TXUNDERRIE |
+                SDIO_MASK_DATAENDIE;
+  SDIO->DLEN  = n * SDC_BLOCK_SIZE;
+
+  /* Talk to card what we want from it.*/
+  if (sdc_lld_prepare_write(sdcp, startblk, n, resp) == SDC_FAILED)
+    goto error;
+
+  /* Transaction starts just after DTEN bit setting.*/
+  SDIO->DCTRL = SDIO_DCTRL_DBLOCKSIZE_3 |
+                SDIO_DCTRL_DBLOCKSIZE_0 |
+                SDIO_DCTRL_DMAEN |
+                SDIO_DCTRL_DTEN;
+  if (sdc_lld_wait_transaction_end(sdcp, n, resp) == SDC_FAILED)
+    goto error;
+  else
+    return SDC_SUCCESS;
+
+error:
+  sdc_lld_error_cleanup(sdcp, n, resp);
+  return SDC_FAILED;
+}
+
+/**
+ * @brief   Reads one or more blocks.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] startblk  first block to read
+ * @param[out] buf      pointer to the read buffer
+ * @param[in] n         number of blocks to read
+ *
+ * @return              The operation status.
+ * @retval SDC_SUCCESS  operation succeeded.
+ * @retval SDC_FAILED   operation failed.
  *
  * @notapi
  */
@@ -677,18 +710,16 @@ bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
   if (((unsigned)buf & 3) != 0) {
     uint32_t i;
     for (i = 0; i < n; i++) {
-      if (sdc_lld_read_single(sdcp, startblk, u.buf))
-        return TRUE;
+      if (sdc_lld_read_aligned(sdcp, startblk, u.buf, 1))
+        return SDC_FAILED;
       memcpy(buf, u.buf, SDC_BLOCK_SIZE);
       buf += SDC_BLOCK_SIZE;
       startblk++;
     }
-    return FALSE;
+    return SDC_SUCCESS;
   }
 #endif
-  if (n == 1)
-    return sdc_lld_read_single(sdcp, startblk, buf);
-  return sdc_lld_read_multiple(sdcp, startblk, buf, n);
+  return sdc_lld_read_aligned(sdcp, startblk, buf, n);
 }
 
 /**
@@ -698,32 +729,30 @@ bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
  * @param[in] startblk  first block to write
  * @param[out] buf      pointer to the write buffer
  * @param[in] n         number of blocks to write
+ *
  * @return              The operation status.
- * @retval FALSE        operation succeeded, the requested blocks have been
- *                      written.
- * @retval TRUE         operation failed.
+ * @retval SDC_SUCCESS  operation succeeded.
+ * @retval SDC_FAILED   operation failed.
  *
  * @notapi
  */
 bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
                      const uint8_t *buf, uint32_t n) {
 
-#if STM32_SDC_UNALIGNED_SUPPORT
+  #if STM32_SDC_UNALIGNED_SUPPORT
   if (((unsigned)buf & 3) != 0) {
     uint32_t i;
     for (i = 0; i < n; i++) {
       memcpy(u.buf, buf, SDC_BLOCK_SIZE);
       buf += SDC_BLOCK_SIZE;
-      if (sdc_lld_write_single(sdcp, startblk, u.buf))
-        return TRUE;
+      if (sdc_lld_write_aligned(sdcp, startblk, u.buf, 1))
+        return SDC_FAILED;
       startblk++;
     }
-    return FALSE;
+    return SDC_SUCCESS;
   }
 #endif
-  if (n == 1)
-    return sdc_lld_write_single(sdcp, startblk, buf);
-  return sdc_lld_write_multiple(sdcp, startblk, buf, n);
+  return sdc_lld_write_aligned(sdcp, startblk, buf, n);
 }
 
 #endif /* HAL_USE_SDC */
diff --git a/os/hal/platforms/STM32/sdc_lld.h b/os/hal/platforms/STM32/sdc_lld.h
index 1d4f21034..51db5b2aa 100644
--- a/os/hal/platforms/STM32/sdc_lld.h
+++ b/os/hal/platforms/STM32/sdc_lld.h
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
@@ -35,6 +35,23 @@
 /* Driver constants.                                                         */
 /*===========================================================================*/
 
+/**
+ * @brief Value to clear all interrupts flag at once.
+ */
+#define STM32_SDIO_ICR_ALL_FLAGS (SDIO_ICR_CCRCFAILC | SDIO_ICR_DCRCFAILC |   \
+                                  SDIO_ICR_CTIMEOUTC | SDIO_ICR_DTIMEOUTC |   \
+                                  SDIO_ICR_TXUNDERRC | SDIO_ICR_RXOVERRC |    \
+                                  SDIO_ICR_CMDRENDC  | SDIO_ICR_CMDSENTC |    \
+                                  SDIO_ICR_DATAENDC  | SDIO_ICR_STBITERRC |   \
+                                  SDIO_ICR_DBCKENDC  | SDIO_ICR_SDIOITC |     \
+                                  SDIO_ICR_CEATAENDC)
+
+/**
+ * @brief Mask of error flags in STA register.
+ */
+#define STM32_SDIO_STA_ERROR_MASK (SDIO_STA_CCRCFAIL | SDIO_STA_DCRCFAIL |    \
+                                   SDIO_STA_CTIMEOUT | SDIO_STA_DTIMEOUT |    \
+                                   SDIO_STA_TXUNDERR | SDIO_STA_RXOVERR)
 
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
@@ -44,13 +61,6 @@
  * @name    Configuration options
  * @{
  */
-/**
- * @brief   SDIO data timeout in SDIO clock cycles.
- */
-#if !defined(STM32_SDC_DATATIMEOUT) || defined(__DOXYGEN__)
-#define STM32_SDC_DATATIMEOUT               0x000FFFFF
-#endif
-
 /**
  * @brief   SDIO DMA priority (0..3|lowest..highest).
  */
@@ -65,12 +75,6 @@
 #define STM32_SDC_SDIO_IRQ_PRIORITY         9
 #endif
 
-/**
- * @brief   SDIO support for unaligned transfers.
- */
-#if !defined(STM32_SDC_UNALIGNED_SUPPORT) || defined(__DOXYGEN__)
-#define STM32_SDC_UNALIGNED_SUPPORT         TRUE
-#endif
 /** @} */
 
 /*===========================================================================*/
@@ -88,14 +92,34 @@
 /*
  * SDIO clock divider.
  */
-#if STM32_HCLK > 48000000
-#define STM32_SDIO_DIV_HS                   0x01
-#define STM32_SDIO_DIV_LS                   0xB2
+#if (defined(STM32F4XX) || defined(STM32F2XX))
+  #define STM32_SDIO_DIV_HS                   0
+  #define STM32_SDIO_DIV_LS                   120
+#elif STM32_HCLK > 48000000
+  #define STM32_SDIO_DIV_HS                   1
+  #define STM32_SDIO_DIV_LS                   178
+#else
+  #define STM32_SDIO_DIV_HS                   0
+  #define STM32_SDIO_DIV_LS                   118
+#endif
+
+/**
+ * @brief   SDIO data timeouts in SDIO clock cycles.
+ */
+#if (defined(STM32F4XX) || defined(STM32F2XX))
+  #define STM32_SDC_WRITE_TIMEOUT \
+    (((48000000 / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_WRITE_TIMEOUT_MS)
+  #define STM32_SDC_READ_TIMEOUT \
+    (((48000000 / (STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_READ_TIMEOUT_MS)
 #else
-#define STM32_SDIO_DIV_HS                   0x00
-#define STM32_SDIO_DIV_LS                   0x76
+  #define STM32_SDC_WRITE_TIMEOUT  \
+    (((STM32_HCLK /((STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_WRITE_TIMEOUT_MS)
+  #define STM32_SDC_READ_TIMEOUT  \
+    (((STM32_HCLK /((STM32_SDIO_DIV_HS + 2)) / 1000) * SDC_READ_TIMEOUT_MS)
 #endif
 
+
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
@@ -143,6 +167,10 @@ struct SDCDriver {
    * @brief Various flags regarding the mounted card.
    */
   sdcmode_t                 cardmode;
+  /**
+   * @brief Errors flags.
+   */
+  uint32_t                  errors;
   /**
    * @brief Card CID.
    */
@@ -155,11 +183,30 @@ struct SDCDriver {
    * @brief Card RCA.
    */
   uint32_t                  rca;
+  /**
+   * @brief Total number of blocks in card.
+   */
+  uint32_t                  capacity;
   /* End of the mandatory fields.*/
   /**
    * @brief Thread waiting for I/O completion IRQ.
    */
   Thread                    *thread;
+  /**
+   * @brief     DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+  /**
+   * @brief     Transmit DMA channel.
+   */
+  const stm32_dma_stream_t  *dma;
+  /**
+   * @brief     Pointer to the SDIO registers block.
+   * @note      Used only for dubugging purpose.
+   */
+#if CH_DBG_ENABLE_ASSERTS
+  SDIO_TypeDef              *sdio;
+#endif
 };
 
 /*===========================================================================*/
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index c88ac3a96..a058e848a 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -339,6 +339,9 @@
 
 /* SDIO attributes.*/
 #define STM32_HAS_SDIO          TRUE
+#define STM32_SDC_SDIO_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3) |            \
+                                 STM32_DMA_STREAM_ID_MSK(2, 6))
+#define STM32_SDC_SDIO_DMA_CHN  0x04004000
 
 /* SPI attributes.*/
 #define STM32_HAS_SPI1          TRUE
@@ -492,6 +495,7 @@
 #define TIM8_CC_IRQHandler      VectorF8    /**< TIM8 Capture Compare.      */
 #define DMA1_Stream7_IRQHandler VectorFC    /**< DMA1 Stream 7.             */
 #define FSMC_IRQHandler         Vector100   /**< FSMC.                      */
+#define SDIO_IRQHandler         Vector104   /**< SDIO.                      */
 #define TIM5_IRQHandler         Vector108   /**< TIM5.                      */
 #define SPI3_IRQHandler         Vector10C   /**< SPI3.                      */
 #define UART4_IRQHandler        Vector110   /**< UART4.                     */
diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk
index 475a5b35c..fa9caef41 100644
--- a/os/hal/platforms/STM32F4xx/platform.mk
+++ b/os/hal/platforms/STM32F4xx/platform.mk
@@ -11,10 +11,11 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c
+              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/sdc_lld.c
 
 # Required include directories
 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F4xx \
               ${CHIBIOS}/os/hal/platforms/STM32 \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2
\ No newline at end of file
+              ${CHIBIOS}/os/hal/platforms/STM32/RTCv2
diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h
index c7f5c8a51..181a2547c 100644
--- a/os/hal/platforms/STM32F4xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h
@@ -502,6 +502,39 @@
 #define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST)
 /** @} */
 
+/**
+ * @name    SDIO peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the SDIO peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSDIO(lp) rccEnableAPB2(RCC_APB2ENR_SDIOEN, lp)
+
+/**
+ * @brief   Disables the SDIO peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSDIO(lp) rccDisableAPB2(RCC_APB2ENR_SDIOEN, lp)
+
+/**
+ * @brief   Resets the SDIO peripheral.
+ * @note    Not supported in this family, does nothing.
+ *
+ * @api
+ */
+#define rccResetSDIO() rccResetAPB2(RCC_APB2RSTR_SDIORST)
+/** @} */
+
 /**
  * @name    SPI peripherals specific RCC operations
  * @{
-- 
cgit v1.2.3


From 2b35b5a2a5a9484332edebaca861a87910cf6715 Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 8 Mar 2012 19:52:44 +0000
Subject: SDC. Added RTC support. Improved testhal.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/sdc_dev2@4031 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32/RTCv1/rtc_lld.c         | 24 ++++++++++++++++++++++++
 os/hal/platforms/STM32/RTCv1/rtc_lld.h         |  1 +
 os/hal/platforms/STM32/RTCv2/rtc_lld.c         | 23 +++++++++++++++++++++++
 os/hal/platforms/STM32/RTCv2/rtc_lld.h         |  1 +
 os/hal/platforms/STM32/sdc_lld.c               | 12 ++++++------
 os/hal/platforms/STM32F1xx/hal_lld.h           | 14 ++++++++++++++
 os/hal/platforms/STM32F1xx/hal_lld_f100.h      |  3 ---
 os/hal/platforms/STM32F1xx/hal_lld_f103.h      |  4 ----
 os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h |  4 ----
 os/hal/platforms/STM32F2xx/hal_lld.h           |  1 +
 os/hal/platforms/STM32F4xx/hal_lld.h           |  1 +
 os/hal/platforms/STM32L1xx/hal_lld.h           |  1 +
 12 files changed, 72 insertions(+), 17 deletions(-)

(limited to 'os/hal/platforms')

diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
index 066e0f659..6496cfae9 100644
--- a/os/hal/platforms/STM32/RTCv1/rtc_lld.c
+++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
@@ -30,6 +30,8 @@
  * @{
  */
 
+#include <time.h>
+
 #include "ch.h"
 #include "hal.h"
 
@@ -290,6 +292,28 @@ void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
   }
 }
 
+/**
+ * @brief   Get current time in format suitable for usage in FatFS.
+ *
+ * @param[in] timespec  pointer to RTCTime structure
+ * @return              FAT time value.
+ *
+ * @api
+ */
+uint32_t rtc_lld_calc_fat_time(RTCTime *timespec){
+  uint32_t fattime = 0;
+  struct tm *timp;
+
+  timp = localtime((time_t *)(timespec->tv_sec));
+
+  fattime |= (timp->tm_sec / 2);
+  fattime |= (timp->tm_min) << 5;
+  fattime |= (timp->tm_hour) << 11;
+  fattime |= (timp->tm_mday) << 16;
+  fattime |= (timp->tm_mon + 1) << 21;
+  fattime |= (timp->tm_year - 80) << 25;
+  return fattime;
+}
 #endif /* HAL_USE_RTC */
 
 /** @} */
diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.h b/os/hal/platforms/STM32/RTCv1/rtc_lld.h
index 4944ff735..64287d978 100644
--- a/os/hal/platforms/STM32/RTCv1/rtc_lld.h
+++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.h
@@ -178,6 +178,7 @@ extern "C" {
                          rtcalarm_t alarm,
                          RTCAlarm *alarmspec);
   void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback);
+  uint32_t rtc_lld_calc_fat_time(RTCTime *timespec);
 #ifdef __cplusplus
 }
 #endif
diff --git a/os/hal/platforms/STM32/RTCv2/rtc_lld.c b/os/hal/platforms/STM32/RTCv2/rtc_lld.c
index cae3f812b..c2268fd82 100644
--- a/os/hal/platforms/STM32/RTCv2/rtc_lld.c
+++ b/os/hal/platforms/STM32/RTCv2/rtc_lld.c
@@ -264,6 +264,29 @@ void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec){
   wakeupspec->wakeup |= (((uint32_t)rtcp->id_rtc->CR) & 0x7) << 16;
 }
 
+/**
+ * @brief   Get current time in format suitable for usage in FatFS.
+ *
+ * @param[in] timespec  pointer to RTCTime structure
+ * @return              FAT time value.
+ *
+ * @api
+ */
+uint32_t rtc_lld_calc_fat_time(RTCTime *timespec){
+  uint32_t fattime = 0;
+  struct tm timp;
+
+  stm32_rtc_bcd2tm(&timp, timespec);
+
+  fattime |= (timp.tm_sec / 2);
+  fattime |= (timp.tm_min) << 5;
+  fattime |= (timp.tm_hour) << 11;
+  fattime |= (timp.tm_mday) << 16;
+  fattime |= (timp.tm_mon + 1) << 21;
+  fattime |= (timp.tm_year - 80) << 25;
+  return fattime;
+}
+
 /**
  * @brief     Converts from STM32 BCD to canonicalized time format.
  *
diff --git a/os/hal/platforms/STM32/RTCv2/rtc_lld.h b/os/hal/platforms/STM32/RTCv2/rtc_lld.h
index 3f0139f00..88959294c 100644
--- a/os/hal/platforms/STM32/RTCv2/rtc_lld.h
+++ b/os/hal/platforms/STM32/RTCv2/rtc_lld.h
@@ -200,6 +200,7 @@ extern "C" {
                          RTCAlarm *alarmspec);
   void rtcSetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec);
   void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec);
+  uint32_t rtc_lld_calc_fat_time(RTCTime *timespec);
   void stm32_rtc_bcd2tm(struct tm *timp, RTCTime *timespec);
   void stm32_rtc_tm2bcd(struct tm *timp, RTCTime *timespec);
 #ifdef __cplusplus
diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c
index f74d06c9e..c42867ffe 100644
--- a/os/hal/platforms/STM32/sdc_lld.c
+++ b/os/hal/platforms/STM32/sdc_lld.c
@@ -56,7 +56,7 @@ SDCDriver SDCD1;
 /* Driver local variables.                                                   */
 /*===========================================================================*/
 
-#if STM32_SDC_UNALIGNED_SUPPORT
+#if STM32_SDC_SDIO_UNALIGNED_SUPPORT
 /**
  * @brief   Buffer for temporary storage during unaligned transfers.
  */
@@ -64,7 +64,7 @@ static union {
   uint32_t  alignment;
   uint8_t   buf[SDC_BLOCK_SIZE];
 } u;
-#endif
+#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
 
 /*===========================================================================*/
 /* Driver local functions.                                                   */
@@ -706,7 +706,7 @@ error:
 bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
                     uint8_t *buf, uint32_t n) {
 
-#if STM32_SDC_UNALIGNED_SUPPORT
+#if STM32_SDC_SDIO_UNALIGNED_SUPPORT
   if (((unsigned)buf & 3) != 0) {
     uint32_t i;
     for (i = 0; i < n; i++) {
@@ -718,7 +718,7 @@ bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
     }
     return SDC_SUCCESS;
   }
-#endif
+#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
   return sdc_lld_read_aligned(sdcp, startblk, buf, n);
 }
 
@@ -739,7 +739,7 @@ bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
 bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
                      const uint8_t *buf, uint32_t n) {
 
-  #if STM32_SDC_UNALIGNED_SUPPORT
+#if STM32_SDC_SDIO_UNALIGNED_SUPPORT
   if (((unsigned)buf & 3) != 0) {
     uint32_t i;
     for (i = 0; i < n; i++) {
@@ -751,7 +751,7 @@ bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
     }
     return SDC_SUCCESS;
   }
-#endif
+#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
   return sdc_lld_write_aligned(sdcp, startblk, buf, n);
 }
 
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h
index c79769e80..4a375ab4e 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld.h
@@ -77,6 +77,20 @@
 #define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
 /** @} */
 
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @name    STM32F1xx capabilities
+ * @{
+ */
+/* RTC attributes.*/
+#define STM32_HAS_RTC           TRUE
+#define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR   TRUE
+/** @} */
+
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
index 509b20054..25dd3a186 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
@@ -239,9 +239,6 @@
 #define STM32_SPI3_TX_DMA_MSK   0
 #define STM32_SPI3_TX_DMA_CHN   0x00000000
 
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTCSEL_HAS_SUBSECONDS TRUE
-
 /* SDIO attributes.*/
 #define STM32_HAS_SDIO          FALSE
 
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h
index 7bcbb3043..deda9f67a 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h
@@ -249,10 +249,6 @@
 #define STM32_SPI3_TX_DMA_MSK   0
 #define STM32_SPI3_TX_DMA_CHN   0x00000000
 
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTCSEL_HAS_SUBSECONDS TRUE
-
 /* SDIO attributes.*/
 #define STM32_HAS_SDIO          FALSE
 
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
index 88193fa8a..57b47f003 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
@@ -266,10 +266,6 @@
 #define STM32_I2C3_TX_DMA_MSK   0
 #define STM32_I2C3_TX_DMA_CHN   0x00000000
 
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTCSEL_HAS_SUBSECONDS TRUE
-
 /* SDIO attributes.*/
 #define STM32_HAS_SDIO          FALSE
 
diff --git a/os/hal/platforms/STM32F2xx/hal_lld.h b/os/hal/platforms/STM32F2xx/hal_lld.h
index ae60b7806..165a10448 100644
--- a/os/hal/platforms/STM32F2xx/hal_lld.h
+++ b/os/hal/platforms/STM32F2xx/hal_lld.h
@@ -337,6 +337,7 @@
 /* RTC attributes.*/
 #define STM32_HAS_RTC           TRUE
 #define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR   TRUE
 
 /* SDIO attributes.*/
 #define STM32_HAS_SDIO          TRUE
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index a058e848a..3585379e4 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -336,6 +336,7 @@
 /* RTC attributes.*/
 #define STM32_HAS_RTC           TRUE
 #define STM32_RTC_HAS_SUBSECONDS TRUE
+#define STM32_RTC_IS_CALENDAR   TRUE
 
 /* SDIO attributes.*/
 #define STM32_HAS_SDIO          TRUE
diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h
index 9f47c4da5..f7402dfe6 100644
--- a/os/hal/platforms/STM32L1xx/hal_lld.h
+++ b/os/hal/platforms/STM32L1xx/hal_lld.h
@@ -233,6 +233,7 @@
 /* RTC attributes.*/
 #define STM32_HAS_RTC           TRUE
 #define STM32_RTC_HAS_SUBSECONDS FALSE
+#define STM32_RTC_IS_CALENDAR   TRUE
 
 /* SDIO attributes.*/
 #define STM32_HAS_SDIO          FALSE
-- 
cgit v1.2.3


From 3c311dfe589b6a6b1fd46af2e3138512fe2135fa Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 9 Mar 2012 18:33:26 +0000
Subject: RTC. High level staff moved to chrtclib.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/sdc_dev2@4032 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32/RTCv1/rtc_lld.c |  23 -------
 os/hal/platforms/STM32/RTCv1/rtc_lld.h |   1 -
 os/hal/platforms/STM32/RTCv2/rtc_lld.c | 120 ---------------------------------
 os/hal/platforms/STM32/RTCv2/rtc_lld.h |   5 --
 os/hal/platforms/STM32F1xx/hal_lld.h   |   2 +-
 5 files changed, 1 insertion(+), 150 deletions(-)

(limited to 'os/hal/platforms')

diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
index 6496cfae9..a417194b1 100644
--- a/os/hal/platforms/STM32/RTCv1/rtc_lld.c
+++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
@@ -291,29 +291,6 @@ void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) {
     rtcp->callback = NULL;
   }
 }
-
-/**
- * @brief   Get current time in format suitable for usage in FatFS.
- *
- * @param[in] timespec  pointer to RTCTime structure
- * @return              FAT time value.
- *
- * @api
- */
-uint32_t rtc_lld_calc_fat_time(RTCTime *timespec){
-  uint32_t fattime = 0;
-  struct tm *timp;
-
-  timp = localtime((time_t *)(timespec->tv_sec));
-
-  fattime |= (timp->tm_sec / 2);
-  fattime |= (timp->tm_min) << 5;
-  fattime |= (timp->tm_hour) << 11;
-  fattime |= (timp->tm_mday) << 16;
-  fattime |= (timp->tm_mon + 1) << 21;
-  fattime |= (timp->tm_year - 80) << 25;
-  return fattime;
-}
 #endif /* HAL_USE_RTC */
 
 /** @} */
diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.h b/os/hal/platforms/STM32/RTCv1/rtc_lld.h
index 64287d978..4944ff735 100644
--- a/os/hal/platforms/STM32/RTCv1/rtc_lld.h
+++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.h
@@ -178,7 +178,6 @@ extern "C" {
                          rtcalarm_t alarm,
                          RTCAlarm *alarmspec);
   void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback);
-  uint32_t rtc_lld_calc_fat_time(RTCTime *timespec);
 #ifdef __cplusplus
 }
 #endif
diff --git a/os/hal/platforms/STM32/RTCv2/rtc_lld.c b/os/hal/platforms/STM32/RTCv2/rtc_lld.c
index c2268fd82..870734fba 100644
--- a/os/hal/platforms/STM32/RTCv2/rtc_lld.c
+++ b/os/hal/platforms/STM32/RTCv2/rtc_lld.c
@@ -264,126 +264,6 @@ void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec){
   wakeupspec->wakeup |= (((uint32_t)rtcp->id_rtc->CR) & 0x7) << 16;
 }
 
-/**
- * @brief   Get current time in format suitable for usage in FatFS.
- *
- * @param[in] timespec  pointer to RTCTime structure
- * @return              FAT time value.
- *
- * @api
- */
-uint32_t rtc_lld_calc_fat_time(RTCTime *timespec){
-  uint32_t fattime = 0;
-  struct tm timp;
-
-  stm32_rtc_bcd2tm(&timp, timespec);
-
-  fattime |= (timp.tm_sec / 2);
-  fattime |= (timp.tm_min) << 5;
-  fattime |= (timp.tm_hour) << 11;
-  fattime |= (timp.tm_mday) << 16;
-  fattime |= (timp.tm_mon + 1) << 21;
-  fattime |= (timp.tm_year - 80) << 25;
-  return fattime;
-}
-
-/**
- * @brief     Converts from STM32 BCD to canonicalized time format.
- *
- * @param[out] timp     pointer to a @p tm structure defined in time.h
- * @param[in]  timespec pointer to a @p RTCTime structure
- *
- * @api
- */
-void stm32_rtc_bcd2tm(struct tm *timp, RTCTime *timespec){
-  uint32_t tv_time = timespec->tv_time;
-  uint32_t tv_date = timespec->tv_date;
-
-#if CH_DBG_ENABLE_CHECKS
-  timp->tm_isdst = 0;
-  timp->tm_wday  = 0;
-  timp->tm_mday  = 0;
-  timp->tm_yday  = 0;
-  timp->tm_mon   = 0;
-  timp->tm_year  = 0;
-  timp->tm_sec   = 0;
-  timp->tm_min   = 0;
-  timp->tm_hour  = 0;
-#endif
-
-  timp->tm_isdst = -1;
-
-  timp->tm_wday = (tv_date & RTC_DR_WDU) >> RTC_DR_WDU_OFFSET;
-  if(timp->tm_wday == 7)
-    timp->tm_wday = 0;
-
-  timp->tm_mday =  (tv_date & RTC_DR_DU) >> RTC_DR_DU_OFFSET;
-  timp->tm_mday += ((tv_date & RTC_DR_DT) >> RTC_DR_DT_OFFSET) * 10;
-
-  timp->tm_mon  =  (tv_date & RTC_DR_MU) >> RTC_DR_MU_OFFSET;
-  timp->tm_mon  += ((tv_date & RTC_DR_MT) >> RTC_DR_MT_OFFSET) * 10;
-  timp->tm_mon  -= 1;
-
-  timp->tm_year =  (tv_date & RTC_DR_YU) >> RTC_DR_YU_OFFSET;
-  timp->tm_year += ((tv_date & RTC_DR_YT) >> RTC_DR_YT_OFFSET) * 10;
-  timp->tm_year += 2000 - 1900;
-
-  timp->tm_sec  =  (tv_time & RTC_TR_SU) >> RTC_TR_SU_OFFSET;
-  timp->tm_sec  += ((tv_time & RTC_TR_ST) >> RTC_TR_ST_OFFSET) * 10;
-
-  timp->tm_min  =  (tv_time & RTC_TR_MNU) >> RTC_TR_MNU_OFFSET;
-  timp->tm_min  += ((tv_time & RTC_TR_MNT) >> RTC_TR_MNT_OFFSET) * 10;
-
-  timp->tm_hour =  (tv_time & RTC_TR_HU) >> RTC_TR_HU_OFFSET;
-  timp->tm_hour += ((tv_time & RTC_TR_HT) >> RTC_TR_HT_OFFSET) * 10;
-  timp->tm_hour += 12 * ((tv_time & RTC_TR_PM) >> RTC_TR_PM_OFFSET);
-}
-
-/**
- * @brief     Converts from canonicalized to STM32 BCD time format.
- *
- * @param[in]  timp     pointer to a @p tm structure defined in time.h
- * @param[out] timespec pointer to a @p RTCTime structure
- *
- * @api
- */
-void stm32_rtc_tm2bcd(struct tm *timp, RTCTime *timespec){
-  uint32_t v = 0;
-
-  timespec->tv_date = 0;
-  timespec->tv_time = 0;
-
-  v = timp->tm_year - 100;
-  timespec->tv_date |= ((v / 10) << RTC_DR_YT_OFFSET) & RTC_DR_YT;
-  timespec->tv_date |= (v % 10) << RTC_DR_YU_OFFSET;
-
-  if (timp->tm_wday == 0)
-    v = 7;
-  else
-    v = timp->tm_wday;
-  timespec->tv_date |= (v << RTC_DR_WDU_OFFSET) & RTC_DR_WDU;
-
-  v = timp->tm_mon + 1;
-  timespec->tv_date |= ((v / 10) << RTC_DR_MT_OFFSET) & RTC_DR_MT;
-  timespec->tv_date |= (v % 10) << RTC_DR_MU_OFFSET;
-
-  v = timp->tm_mday;
-  timespec->tv_date |= ((v / 10) << RTC_DR_DT_OFFSET) & RTC_DR_DT;
-  timespec->tv_date |= (v % 10) << RTC_DR_DU_OFFSET;
-
-  v = timp->tm_hour;
-  timespec->tv_time |= ((v / 10) << RTC_TR_HT_OFFSET) & RTC_TR_HT;
-  timespec->tv_time |= (v % 10) << RTC_TR_HU_OFFSET;
-
-  v = timp->tm_min;
-  timespec->tv_time |= ((v / 10) << RTC_TR_MNT_OFFSET) & RTC_TR_MNT;
-  timespec->tv_time |= (v % 10) << RTC_TR_MNU_OFFSET;
-
-  v = timp->tm_sec;
-  timespec->tv_time |= ((v / 10) << RTC_TR_ST_OFFSET) & RTC_TR_ST;
-  timespec->tv_time |= (v % 10) << RTC_TR_SU_OFFSET;
-}
-
 #endif /* HAL_USE_RTC */
 
 /** @} */
diff --git a/os/hal/platforms/STM32/RTCv2/rtc_lld.h b/os/hal/platforms/STM32/RTCv2/rtc_lld.h
index 88959294c..4cae5744d 100644
--- a/os/hal/platforms/STM32/RTCv2/rtc_lld.h
+++ b/os/hal/platforms/STM32/RTCv2/rtc_lld.h
@@ -35,8 +35,6 @@
 
 #if HAL_USE_RTC || defined(__DOXYGEN__)
 
-#include <time.h>
-
 /*===========================================================================*/
 /* Driver constants.                                                         */
 /*===========================================================================*/
@@ -200,9 +198,6 @@ extern "C" {
                          RTCAlarm *alarmspec);
   void rtcSetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec);
   void rtcGetPeriodicWakeup_v2(RTCDriver *rtcp, RTCWakeup *wakeupspec);
-  uint32_t rtc_lld_calc_fat_time(RTCTime *timespec);
-  void stm32_rtc_bcd2tm(struct tm *timp, RTCTime *timespec);
-  void stm32_rtc_tm2bcd(struct tm *timp, RTCTime *timespec);
 #ifdef __cplusplus
 }
 #endif
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h
index 4a375ab4e..c8d87b7c5 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld.h
@@ -88,7 +88,7 @@
 /* RTC attributes.*/
 #define STM32_HAS_RTC           TRUE
 #define STM32_RTC_HAS_SUBSECONDS TRUE
-#define STM32_RTC_IS_CALENDAR   TRUE
+#define STM32_RTC_IS_CALENDAR   FALSE
 /** @} */
 
 /*===========================================================================*/
-- 
cgit v1.2.3


From 973d8da5eabeead58445937e5be4c740ffaf2c56 Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 16 Apr 2012 18:19:34 +0000
Subject: SDC. Added function sdcGetAndClearErrors.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/sdc_dev2@4099 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32/sdc_lld.c | 13 +++++++++++++
 os/hal/platforms/STM32/sdc_lld.h |  9 +++++++--
 2 files changed, 20 insertions(+), 2 deletions(-)

(limited to 'os/hal/platforms')

diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c
index c42867ffe..0c535e2dc 100644
--- a/os/hal/platforms/STM32/sdc_lld.c
+++ b/os/hal/platforms/STM32/sdc_lld.c
@@ -755,6 +755,19 @@ bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
   return sdc_lld_write_aligned(sdcp, startblk, buf, n);
 }
 
+/**
+ * @brief   Get errors from SDC driver and clear error field.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+sdcflags_t sdc_lld_get_and_clear_errors(SDCDriver *sdcp) {
+  sdcflags_t flags = sdcp->errors;
+  sdcp->errors = SDC_NO_ERROR;
+  return flags;
+}
+
 #endif /* HAL_USE_SDC */
 
 /** @} */
diff --git a/os/hal/platforms/STM32/sdc_lld.h b/os/hal/platforms/STM32/sdc_lld.h
index 51db5b2aa..000100396 100644
--- a/os/hal/platforms/STM32/sdc_lld.h
+++ b/os/hal/platforms/STM32/sdc_lld.h
@@ -119,7 +119,6 @@
 #endif
 
 
-
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
@@ -138,6 +137,11 @@ typedef enum {
  */
 typedef uint32_t sdcmode_t;
 
+/**
+ * @brief   SDC Driver condition flags type.
+ */
+typedef uint32_t sdcflags_t;
+
 /**
  * @brief   Type of a structure representing an SDC driver.
  */
@@ -170,7 +174,7 @@ struct SDCDriver {
   /**
    * @brief Errors flags.
    */
-  uint32_t                  errors;
+  sdcflags_t                errors;
   /**
    * @brief Card CID.
    */
@@ -242,6 +246,7 @@ extern "C" {
                       uint8_t *buf, uint32_t n);
   bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
                        const uint8_t *buf, uint32_t n);
+  sdcflags_t sdc_lld_get_and_clear_errors(SDCDriver *sdcp);
   bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp);
   bool_t sdc_lld_is_write_protected(SDCDriver *sdcp);
 #ifdef __cplusplus
-- 
cgit v1.2.3


From 6206a3c5a5a019bffd2db6fe6e9b3e7aca535fa7 Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 16 Apr 2012 19:18:14 +0000
Subject: SDC. sdcGetAndClearErrors() now reside in HL driver.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/sdc_dev2@4100 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32/sdc_lld.c | 13 -------------
 os/hal/platforms/STM32/sdc_lld.h |  1 -
 2 files changed, 14 deletions(-)

(limited to 'os/hal/platforms')

diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c
index 0c535e2dc..c42867ffe 100644
--- a/os/hal/platforms/STM32/sdc_lld.c
+++ b/os/hal/platforms/STM32/sdc_lld.c
@@ -755,19 +755,6 @@ bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
   return sdc_lld_write_aligned(sdcp, startblk, buf, n);
 }
 
-/**
- * @brief   Get errors from SDC driver and clear error field.
- *
- * @param[in] sdcp      pointer to the @p SDCDriver object
- *
- * @notapi
- */
-sdcflags_t sdc_lld_get_and_clear_errors(SDCDriver *sdcp) {
-  sdcflags_t flags = sdcp->errors;
-  sdcp->errors = SDC_NO_ERROR;
-  return flags;
-}
-
 #endif /* HAL_USE_SDC */
 
 /** @} */
diff --git a/os/hal/platforms/STM32/sdc_lld.h b/os/hal/platforms/STM32/sdc_lld.h
index 000100396..437ca9c1d 100644
--- a/os/hal/platforms/STM32/sdc_lld.h
+++ b/os/hal/platforms/STM32/sdc_lld.h
@@ -246,7 +246,6 @@ extern "C" {
                       uint8_t *buf, uint32_t n);
   bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
                        const uint8_t *buf, uint32_t n);
-  sdcflags_t sdc_lld_get_and_clear_errors(SDCDriver *sdcp);
   bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp);
   bool_t sdc_lld_is_write_protected(SDCDriver *sdcp);
 #ifdef __cplusplus
-- 
cgit v1.2.3


From 671cb8ab9dbbfaf9832f7529fc8966a5d042b6f4 Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 16 Apr 2012 20:12:16 +0000
Subject: SDC. Reverted from SDC_SUCCESS/SDC_FAILED to boolean values.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/sdc_dev2@4103 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32/sdc_lld.c | 96 ++++++++++++++++++++--------------------
 1 file changed, 48 insertions(+), 48 deletions(-)

(limited to 'os/hal/platforms')

diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c
index c42867ffe..61d91b044 100644
--- a/os/hal/platforms/STM32/sdc_lld.c
+++ b/os/hal/platforms/STM32/sdc_lld.c
@@ -79,8 +79,8 @@ static union {
  * @param[in] resp      pointer to the response buffer
  *
  * @return              The operation status.
- * @retval SDC_SUCCESS  operation succeeded.
- * @retval SDC_FAILED   operation failed.
+ * @retval FALSE  operation succeeded.
+ * @retval TRUE   operation failed.
  *
  * @notapi
  */
@@ -96,16 +96,16 @@ static bool_t sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk,
     /* Send read multiple blocks command to card.*/
     if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_MULTIPLE_BLOCK,
                                    startblk, resp) || SDC_R1_ERROR(resp[0]))
-      return SDC_FAILED;
+      return TRUE;
   }
   else{
     /* Send read single block command.*/
     if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_READ_SINGLE_BLOCK,
                                    startblk, resp) || SDC_R1_ERROR(resp[0]))
-      return SDC_FAILED;
+      return TRUE;
   }
 
-  return SDC_SUCCESS;
+  return FALSE;
 }
 
 /**
@@ -117,8 +117,8 @@ static bool_t sdc_lld_prepare_read(SDCDriver *sdcp, uint32_t startblk,
  * @param[in] resp      pointer to the response buffer
  *
  * @return              The operation status.
- * @retval SDC_SUCCESS  operation succeeded.
- * @retval SDC_FAILED   operation failed.
+ * @retval FALSE  operation succeeded.
+ * @retval TRUE   operation failed.
  *
  * @notapi
  */
@@ -134,16 +134,16 @@ static bool_t sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk,
     /* Write multiple blocks command.*/
     if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_MULTIPLE_BLOCK,
                                    startblk, resp) || SDC_R1_ERROR(resp[0]))
-      return SDC_FAILED;
+      return TRUE;
   }
   else{
     /* Write single block command.*/
     if (sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_WRITE_BLOCK,
                                    startblk, resp) || SDC_R1_ERROR(resp[0]))
-      return SDC_FAILED;
+      return TRUE;
   }
 
-  return SDC_SUCCESS;
+  return FALSE;
 }
 
 /**
@@ -154,8 +154,8 @@ static bool_t sdc_lld_prepare_write(SDCDriver *sdcp, uint32_t startblk,
  * @param[in] resp      pointer to the response buffer
  *
  * @return              The operation status.
- * @retval SDC_SUCCESS  operation succeeded.
- * @retval SDC_FAILED   operation failed.
+ * @retval FALSE  operation succeeded.
+ * @retval TRUE   operation failed.
  */
 static bool_t sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n,
                                            uint32_t *resp){
@@ -173,7 +173,7 @@ static bool_t sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n,
   }
   if ((SDIO->STA & SDIO_STA_DATAEND) == 0) {
     chSysUnlock();
-    return SDC_FAILED;
+    return TRUE;
   }
 
   /* Wait until DMA channel enabled to be sure that all data transferred.*/
@@ -195,7 +195,7 @@ static bool_t sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n,
   if (n > 1)
     return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp);
   else
-    return SDC_SUCCESS;
+    return FALSE;
 }
 
 /**
@@ -470,8 +470,8 @@ void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
  * @param[out] resp     pointer to the response buffer (one word)
  *
  * @return              The operation status.
- * @retval SDC_SUCCESS  operation succeeded.
- * @retval SDC_FAILED   operation failed.
+ * @retval FALSE  operation succeeded.
+ * @retval TRUE   operation failed.
  *
  * @notapi
  */
@@ -488,10 +488,10 @@ bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
   SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC;
   if ((sta & (SDIO_STA_CTIMEOUT)) != 0){
     sdc_lld_collect_errors(sdcp);
-    return SDC_FAILED;
+    return TRUE;
   }
   *resp = SDIO->RESP1;
-  return SDC_SUCCESS;
+  return FALSE;
 }
 
 /**
@@ -503,8 +503,8 @@ bool_t sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
  * @param[out] resp     pointer to the response buffer (one word)
  *
  * @return              The operation status.
- * @retval SDC_SUCCESS  operation succeeded.
- * @retval SDC_FAILED   operation failed.
+ * @retval FALSE  operation succeeded.
+ * @retval TRUE   operation failed.
  *
  * @notapi
  */
@@ -521,10 +521,10 @@ bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
   SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC;
   if ((sta & (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)) != 0){
     sdc_lld_collect_errors(sdcp);
-    return SDC_FAILED;
+    return TRUE;
   }
   *resp = SDIO->RESP1;
-  return SDC_SUCCESS;
+  return FALSE;
 }
 
 /**
@@ -536,8 +536,8 @@ bool_t sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
  * @param[out] resp     pointer to the response buffer (four words)
  *
  * @return              The operation status.
- * @retval SDC_SUCCESS  operation succeeded.
- * @retval SDC_FAILED   operation failed.
+ * @retval FALSE  operation succeeded.
+ * @retval TRUE   operation failed.
  *
  * @notapi
  */
@@ -556,14 +556,14 @@ bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
   SDIO->ICR = SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC;
   if ((sta & (STM32_SDIO_STA_ERROR_MASK)) != 0){
     sdc_lld_collect_errors(sdcp);
-    return SDC_FAILED;
+    return TRUE;
   }
   /* save bytes in reverse order because MSB in response comes first */
   *resp++ = SDIO->RESP4;
   *resp++ = SDIO->RESP3;
   *resp++ = SDIO->RESP2;
   *resp   = SDIO->RESP1;
-  return SDC_SUCCESS;
+  return FALSE;
 }
 
 /**
@@ -575,8 +575,8 @@ bool_t sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
  * @param[in] n         number of blocks to read
  *
  * @return              The operation status.
- * @retval SDC_SUCCESS  operation succeeded.
- * @retval SDC_FAILED   operation failed.
+ * @retval FALSE  operation succeeded.
+ * @retval TRUE   operation failed.
  *
  * @notapi
  */
@@ -590,7 +590,7 @@ bool_t sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
 
   /* Checks for errors and waits for the card to be ready for reading.*/
   if (_sdc_wait_for_transfer_state(sdcp))
-    return SDC_FAILED;
+    return TRUE;
 
   /* Prepares the DMA channel for writing.*/
   dmaStreamSetMemory0(sdcp->dma, buf);
@@ -609,7 +609,7 @@ bool_t sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
   SDIO->DLEN  = n * SDC_BLOCK_SIZE;
 
   /* Talk to card what we want from it.*/
-  if (sdc_lld_prepare_read(sdcp, startblk, n, resp) == SDC_FAILED)
+  if (sdc_lld_prepare_read(sdcp, startblk, n, resp) == TRUE)
     goto error;
 
   /* Transaction starts just after DTEN bit setting.*/
@@ -618,14 +618,14 @@ bool_t sdc_lld_read_aligned(SDCDriver *sdcp, uint32_t startblk,
                 SDIO_DCTRL_DBLOCKSIZE_0 |
                 SDIO_DCTRL_DMAEN |
                 SDIO_DCTRL_DTEN;
-  if (sdc_lld_wait_transaction_end(sdcp, n, resp) == SDC_FAILED)
+  if (sdc_lld_wait_transaction_end(sdcp, n, resp) == TRUE)
     goto error;
   else
-    return SDC_SUCCESS;
+    return FALSE;
 
 error:
   sdc_lld_error_cleanup(sdcp, n, resp);
-  return SDC_FAILED;
+  return TRUE;
 }
 
 /**
@@ -637,8 +637,8 @@ error:
  * @param[in] n         number of blocks to write
  *
  * @return              The operation status.
- * @retval SDC_SUCCESS  operation succeeded.
- * @retval SDC_FAILED   operation failed.
+ * @retval FALSE  operation succeeded.
+ * @retval TRUE   operation failed.
  *
  * @notapi
  */
@@ -652,7 +652,7 @@ bool_t sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk,
 
   /* Checks for errors and waits for the card to be ready for writing.*/
   if (_sdc_wait_for_transfer_state(sdcp))
-    return SDC_FAILED;
+    return TRUE;
 
   /* Prepares the DMA channel for writing.*/
   dmaStreamSetMemory0(sdcp->dma, buf);
@@ -671,7 +671,7 @@ bool_t sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk,
   SDIO->DLEN  = n * SDC_BLOCK_SIZE;
 
   /* Talk to card what we want from it.*/
-  if (sdc_lld_prepare_write(sdcp, startblk, n, resp) == SDC_FAILED)
+  if (sdc_lld_prepare_write(sdcp, startblk, n, resp) == TRUE)
     goto error;
 
   /* Transaction starts just after DTEN bit setting.*/
@@ -679,14 +679,14 @@ bool_t sdc_lld_write_aligned(SDCDriver *sdcp, uint32_t startblk,
                 SDIO_DCTRL_DBLOCKSIZE_0 |
                 SDIO_DCTRL_DMAEN |
                 SDIO_DCTRL_DTEN;
-  if (sdc_lld_wait_transaction_end(sdcp, n, resp) == SDC_FAILED)
+  if (sdc_lld_wait_transaction_end(sdcp, n, resp) == TRUE)
     goto error;
   else
-    return SDC_SUCCESS;
+    return FALSE;
 
 error:
   sdc_lld_error_cleanup(sdcp, n, resp);
-  return SDC_FAILED;
+  return TRUE;
 }
 
 /**
@@ -698,8 +698,8 @@ error:
  * @param[in] n         number of blocks to read
  *
  * @return              The operation status.
- * @retval SDC_SUCCESS  operation succeeded.
- * @retval SDC_FAILED   operation failed.
+ * @retval FALSE  operation succeeded.
+ * @retval TRUE   operation failed.
  *
  * @notapi
  */
@@ -711,12 +711,12 @@ bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
     uint32_t i;
     for (i = 0; i < n; i++) {
       if (sdc_lld_read_aligned(sdcp, startblk, u.buf, 1))
-        return SDC_FAILED;
+        return TRUE;
       memcpy(buf, u.buf, SDC_BLOCK_SIZE);
       buf += SDC_BLOCK_SIZE;
       startblk++;
     }
-    return SDC_SUCCESS;
+    return FALSE;
   }
 #endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
   return sdc_lld_read_aligned(sdcp, startblk, buf, n);
@@ -731,8 +731,8 @@ bool_t sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
  * @param[in] n         number of blocks to write
  *
  * @return              The operation status.
- * @retval SDC_SUCCESS  operation succeeded.
- * @retval SDC_FAILED   operation failed.
+ * @retval FALSE  operation succeeded.
+ * @retval TRUE   operation failed.
  *
  * @notapi
  */
@@ -746,10 +746,10 @@ bool_t sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
       memcpy(u.buf, buf, SDC_BLOCK_SIZE);
       buf += SDC_BLOCK_SIZE;
       if (sdc_lld_write_aligned(sdcp, startblk, u.buf, 1))
-        return SDC_FAILED;
+        return TRUE;
       startblk++;
     }
-    return SDC_SUCCESS;
+    return FALSE;
   }
 #endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
   return sdc_lld_write_aligned(sdcp, startblk, buf, n);
-- 
cgit v1.2.3