From 72858cb49d82d0e04de168f2348c4243c4f50c69 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 19 Feb 2013 11:38:40 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5265
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/SPC560BCxx/hal_lld.h | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

(limited to 'os/hal/platforms')

diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h
index a0294a731..8c4a9a3b4 100644
--- a/os/hal/platforms/SPC560BCxx/hal_lld.h
+++ b/os/hal/platforms/SPC560BCxx/hal_lld.h
@@ -243,22 +243,6 @@
 #define SPC5_DISABLE_WATCHDOG               TRUE
 #endif
 
-/**
- * @brief   XOSC divider value.
- * @note    The allowed range is 1...32.
- */
-#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_XOSCDIV_VALUE                  1
-#endif
-
-/**
- * @brief   Fast IRC divider value.
- * @note    The allowed range is 1...32.
- */
-#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
-#define SPC5_IRCDIV_VALUE                   1
-#endif
-
 /**
  * @brief   FMPLL0 IDF divider value.
  * @note    The default value is calculated for XOSC=8MHz and PHI=64MHz.
@@ -283,6 +267,22 @@
 #define SPC5_FMPLL0_ODF                     SPC5_FMPLL_ODF_DIV4
 #endif
 
+/**
+ * @brief   XOSC divider value.
+ * @note    The allowed range is 1...32.
+ */
+#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_XOSCDIV_VALUE                  1
+#endif
+
+/**
+ * @brief   Fast IRC divider value.
+ * @note    The allowed range is 1...32.
+ */
+#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_IRCDIV_VALUE                   1
+#endif
+
 /**
  * @brief   Peripherals Set 1 clock divider value.
  * @note    Zero means disabled clock.
-- 
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