From 456ddf784d7bc6fe7c88446faa8bac759078d019 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 11 Dec 2012 10:27:10 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4900 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/SPC560BCxx/hal_lld.h | 7 + os/hal/platforms/SPC560Pxx/hal_lld.h | 7 + os/hal/platforms/SPC563Mxx/hal_lld.c | 127 + os/hal/platforms/SPC563Mxx/hal_lld.h | 241 ++ os/hal/platforms/SPC563Mxx/mpc563m.h | 4123 +++++++++++++++++++++++ os/hal/platforms/SPC563Mxx/platform.dox | 70 + os/hal/platforms/SPC563Mxx/platform.mk | 6 + os/hal/platforms/SPC563Mxx/serial_lld.c | 294 ++ os/hal/platforms/SPC563Mxx/serial_lld.h | 157 + os/hal/platforms/SPC563Mxx/typedefs.h | 25 + os/hal/platforms/SPC56x/hal_lld.c | 131 - os/hal/platforms/SPC56x/hal_lld.h | 230 -- os/hal/platforms/SPC56x/mpc563m.h | 4123 ----------------------- os/hal/platforms/SPC56x/platform.dox | 70 - os/hal/platforms/SPC56x/platform.mk | 6 - os/hal/platforms/SPC56x/serial_lld.c | 294 -- os/hal/platforms/SPC56x/serial_lld.h | 157 - os/hal/platforms/SPC56x/typedefs.h | 31 - os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c | 288 ++ os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h | 156 + os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c | 2 +- os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h | 2 +- os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c | 2 +- os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h | 2 +- 24 files changed, 5505 insertions(+), 5046 deletions(-) create mode 100644 os/hal/platforms/SPC563Mxx/hal_lld.c create mode 100644 os/hal/platforms/SPC563Mxx/hal_lld.h create mode 100644 os/hal/platforms/SPC563Mxx/mpc563m.h create mode 100644 os/hal/platforms/SPC563Mxx/platform.dox create mode 100644 os/hal/platforms/SPC563Mxx/platform.mk create mode 100644 os/hal/platforms/SPC563Mxx/serial_lld.c create mode 100644 os/hal/platforms/SPC563Mxx/serial_lld.h create mode 100644 os/hal/platforms/SPC563Mxx/typedefs.h delete mode 100644 os/hal/platforms/SPC56x/hal_lld.c delete mode 100644 os/hal/platforms/SPC56x/hal_lld.h delete mode 100644 os/hal/platforms/SPC56x/mpc563m.h delete mode 100644 os/hal/platforms/SPC56x/platform.dox delete mode 100644 os/hal/platforms/SPC56x/platform.mk delete mode 100644 os/hal/platforms/SPC56x/serial_lld.c delete mode 100644 os/hal/platforms/SPC56x/serial_lld.h delete mode 100644 os/hal/platforms/SPC56x/typedefs.h create mode 100644 os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c create mode 100644 os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h (limited to 'os/hal/platforms') diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h index 27103dfef..6cc920c6e 100644 --- a/os/hal/platforms/SPC560BCxx/hal_lld.h +++ b/os/hal/platforms/SPC560BCxx/hal_lld.h @@ -593,6 +593,13 @@ /* Derived constants and error checks. */ /*===========================================================================*/ +/* + * Configuration-related checks. + */ +#if !defined(SPC560BCxx_MCUCONF) +#error "Using a wrong mcuconf.h file, SPC560BCxx_MCUCONF not defined" +#endif + /* Check on the XOSC frequency.*/ #if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \ (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX) diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.h b/os/hal/platforms/SPC560Pxx/hal_lld.h index 97baf86d4..e015d5d09 100644 --- a/os/hal/platforms/SPC560Pxx/hal_lld.h +++ b/os/hal/platforms/SPC560Pxx/hal_lld.h @@ -588,6 +588,13 @@ /* Derived constants and error checks. */ /*===========================================================================*/ +/* + * Configuration-related checks. + */ +#if !defined(SPC560Pxx_MCUCONF) +#error "Using a wrong mcuconf.h file, SPC560Pxx_MCUCONF not defined" +#endif + /* Check on the XOSC frequency.*/ #if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \ (SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX) diff --git a/os/hal/platforms/SPC563Mxx/hal_lld.c b/os/hal/platforms/SPC563Mxx/hal_lld.c new file mode 100644 index 000000000..89a5d9e45 --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/hal_lld.c @@ -0,0 +1,127 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file SPC563Mxx/hal_lld.c + * @brief SPC563Mxx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + extern void _vectors(void); + uint32_t n; + + /* Enables the branch prediction, clears and enables the BTB into the + BUCSR special register (1013).*/ + asm volatile ("li %%r3, 0x0201 \t\n" + "mtspr 1013, %%r3": : : "r3"); + + /* FLASH wait states and prefetching setup.*/ + CFLASH0.BIUCR.R = SPC_FLASH_BIUCR | SPC_FLASH_WS; + CFLASH0.BIUCR2.R = 0; + CFLASH0.PFCR3.R = 0; + + /* Optimal crossbar settings. The DMA priority is placed above the CPU + priority in order to not starve I/O activities while the CPU is + executing tight loops (FLASH and SRAM slave ports only). + The SRAM is parked on the load/store port, for some unknown reason it + is defaulted on the instructions port and this kills performance.*/ + XBAR.SGPCR3.B.PARK = 4; /* RAM slave on load/store port.*/ + XBAR.MPR0.R = 0x00030201; /* Flash slave port priorities: + eDMA (1): 0 (highest) + Core Instructions (0): 1 + Undocumented (2): 2 + Core Data (4): 3 */ + XBAR.MPR3.R = 0x00030201; /* SRAM slave port priorities: + eDMA (1): 0 (highest) + Core Instructions (0): 1 + Undocumented (2): 2 + Core Data (4): 3 */ + + /* Downcounter timer initialized for system tick use, TB enabled for debug + and measurements.*/ + n = SPC_SYSCLK / CH_FREQUENCY; + asm volatile ("li %%r3, 0 \t\n" + "mtspr 284, %%r3 \t\n" /* Clear TBL register. */ + "mtspr 285, %%r3 \t\n" /* Clear TBU register. */ + "mtspr 22, %[n] \t\n" /* Init. DEC register. */ + "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/ + "li %%r3, 0x4000 \t\n" /* TBEN bit. */ + "mtspr 1008, %%r3 \t\n" /* HID0 register. */ + "lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */ + "mtspr 340, %%r3" /* TCR register. */ + : : [n] "r" (n) : "r3"); + + /* INTC initialization, software vector mode, 4 bytes vectors, starting + at priority 0.*/ + INTC.MCR.R = 0; + INTC.CPR.R = 0; + INTC.IACKR.R = (uint32_t)_vectors; +} + +/** + * @brief SPC563 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h and + * @p hal_lld.h + * @note This function must be invoked only after the system reset. + * + * @special + */ +void spc_clock_init(void) { + +#if !SPC_NO_INIT + /* PLL activation.*/ + FMPLL.ESYNCR1.B.EMODE = 1; + FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/ + FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */ + FMPLL.ESYNCR1.B.EPREDIV = SPC_CLK_PREDIV; + FMPLL.ESYNCR1.B.EMFD = SPC_CLK_MFD; + FMPLL.ESYNCR2.B.ERFD = SPC_CLK_RFD; + while (!FMPLL.SYNSR.B.LOCK) + ; + FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */ +#endif /* !SPC_NO_INIT */ +} + +/** @} */ diff --git a/os/hal/platforms/SPC563Mxx/hal_lld.h b/os/hal/platforms/SPC563Mxx/hal_lld.h new file mode 100644 index 000000000..afb4a459f --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/hal_lld.h @@ -0,0 +1,241 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file SPC563Mxx/hal_lld.h + * @brief SPC563Mxx HAL subsystem low level driver header. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "mpc563m.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "SPC563M64" + +#define RFD_DIV2 0 /**< Divide VCO frequency by 2. */ +#define RFD_DIV4 1 /**< Divide VCO frequency by 4. */ +#define RFD_DIV8 2 /**< Divide VCO frequency by 8. */ +#define RFD_DIV16 3 /**< Divide VCO frequency by 16.*/ + +/** + * @name BIUCR register definitions + * @{ + */ +#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/ +#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */ +#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */ +#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */ +#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */ +#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */ +#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */ +#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */ +#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */ +#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */ +#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */ +#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */ +#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */ +#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */ +#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */ +#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */ +#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */ +#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */ +#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */ +#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */ +#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */ +#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */ +#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */ +#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */ +#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */ +#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */ +#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */ +#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */ +#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */ +#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */ +#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */ +#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */ +#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */ +#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */ +#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */ +#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */ +#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */ +#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the clocks initialization in the HAL. + */ +#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__) +#define SPC_NO_INIT FALSE +#endif + +/** + * @brief Clock bypass. + * @note If set to @p TRUE then the PLL is not started and initialized, the + * external clock is used as-is and the other clock-related settings + * are ignored. + */ +#if !defined(SPC_CLK_BYPASS) || defined(__DOXYGEN__) +#define SPC_CLK_BYPASS FALSE +#endif + +/** + * @brief Disables the overclock checks. + */ +#if !defined(SPC_ALLOW_OVERCLOCK) || defined(__DOXYGEN__) +#define SPC_ALLOW_OVERCLOCK FALSE +#endif + +/** + * @brief External clock pre-divider. + * @note Must be in range 0...14. + * @note The effective divider factor is this value plus one. + */ +#if !defined(SPC_CLK_PREDIV) || defined(__DOXYGEN__) +#define SPC_CLK_PREDIV 1 +#endif + +/** + * @brief Multiplication factor divider. + * @note Must be in range 32...96. + */ +#if !defined(SPC_CLK_MFD) || defined(__DOXYGEN__) +#define SPC_CLK_MFD 80 +#endif + +/** + * @brief Reduced frequency divider. + */ +#if !defined(SPC_CLK_RFD) || defined(__DOXYGEN__) +#define SPC_CLK_RFD RFD_DIV4 +#endif + +/** + * @brief Flash buffer and prefetching settings. + * @note Please refer to the SPC563M64 reference manual about the meaning + * of the following bits, if in doubt DO NOT MODIFY IT. + * @note Do not specify the APC, WWSC, RWSC bits in this value because + * those are calculated from the system clock and ORed with this + * value. + */ +#if !defined(SPC_FLASH_BIUCR) || defined(__DOXYGEN__) +#define SPC_FLASH_BIUCR (BIUCR_BANK1_TOO | \ + BIUCR_MASTER4_PREFETCH | \ + BIUCR_MASTER0_PREFETCH | \ + BIUCR_DPFEN | \ + BIUCR_IPFEN | \ + BIUCR_PFLIM_ON_MISS | \ + BIUCR_BFEN) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(SPC563Mxx_MCUCONF) +#error "Using a wrong mcuconf.h file, SPC563Mxx_MCUCONF not defined" +#endif + +#if (SPC_CLK_PREDIV < 0) || (SPC_CLK_PREDIV > 14) +#error "invalid SPC_CLK_PREDIV value specified" +#endif + +#if (SPC_CLK_MFD < 32) || (SPC_CLK_MFD > 96) +#error "invalid SPC_CLK_MFD value specified" +#endif + +#if (SPC_CLK_RFD != RFD_DIV2) && (SPC_CLK_RFD != RFD_DIV4) && \ + (SPC_CLK_RFD != RFD_DIV8) && (SPC_CLK_RFD != RFD_DIV16) +#error "invalid SPC_CLK_RFD value specified" +#endif + +/** + * @brief PLL output clock. + */ +#define SPC_PLLCLK ((EXTCLK / (SPC_CLK_PREDIV + 1)) * SPC_CLK_MFD) + +#if (SPC_PLLCLK < 256000000) || (SPC_PLLCLK > 512000000) +#error "VCO frequency out of the acceptable range (256...512)" +#endif + +/** + * @brief PLL output clock. + */ +#if !SPC_CLK_BYPASS || defined(__DOXYGEN__) +#define SPC_SYSCLK (SPC_PLLCLK / (1 << (SPC_CLK_RFD + 1))) +#else +#define SPC_SYSCLK EXTCLK +#endif + +#if (SPC_SYSCLK > 80000000) && !SPC_ALLOW_OVERCLOCK +#error "System clock above maximum rated frequency (80MHz)" +#endif + +/** + * @brief Flash wait states are a function of the system clock. + */ +#if (SPC_SYSCLK <= 30000000) || defined(__DOXYGEN__) +#define SPC_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_1) +#elif SPC_SYSCLK <= 60000000 +#define SPC_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_1) +#else +#define SPC_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_1) +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void spc_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC563Mxx/mpc563m.h b/os/hal/platforms/SPC563Mxx/mpc563m.h new file mode 100644 index 000000000..8ee2b5787 --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/mpc563m.h @@ -0,0 +1,4123 @@ +/**************************************************************************/ + +/* FILE NAME: mpc563xm.h COPYRIGHT (c) Freescale 2008,2009 */ +/* VERSION: 2.0 All Rights Reserved */ +/* */ +/* DESCRIPTION: */ +/* This file contain all of the register and bit field definitions for */ +/* MPC563xM. This version supports revision 1.0 and later. */ +/*========================================================================*/ +/* UPDATE HISTORY */ +/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ +/* --- ----------- --------- --------------------- */ +/* 1.0 G. Emerson 31/OCT/07 Initial version. */ +/* 1.1 G. Emerson 20/DEC/07 Added SYSDIV HLT HLTACK */ +/* Added ESYNCR1 ESYNCR2 SYNFMMR */ +/* 1.2 G. Emerson 31/JAN/08 Change eMIOS channels so there are 24. */ +/* 8 channels in the middle of the range */ +/* do not exist */ +/* 1.3 G. Emerson 30/JUL/08 FLEXCAN - Supports FIFO and Buffer. */ +/* RXIMR added */ +/* FMPLL - Added FMPLL.SYNFMMR.B.BSY */ +/* SIU - Added SIU.ISEL0-3 */ +/* EMIOS - Added EMIOS.CH[x].ALTCADR.R */ +/* MCM - Replaced ECSM with MCM */ +/* removing SWT registers as defined at */ +/* seperate memory location. PFLASH */ +/* registers pre-fixed with P*. Added PCT,*/ +/* PLREV, PLAMC, PLASC, IOPMC, MRSR, MWCR.*/ +/* PBRIDGE - Removed as no PBRIDGE */ +/* registers. */ +/* INTC - Updated number of PSR from */ +/* 358 to 360. */ +/* mpc5500_spr.h - Added RI to MSR and NMI*/ +/* to MSCR. */ +/* 1.4 G. Emerson 30/SEP/08 Add SIU.MIDR2 */ +/* Changes to SIU.MIDR as per RM. */ +/* 1.5 May 2009 Changes to match documentation, removed*/ +/* Not released */ +/* 1.6 K. Odenthal 03/June/09 Update for 1.5M version of the MPC563xM*/ +/* & R. Dees */ +/* INTC - All Processor 0 regs matched to previous */ +/* version */ +/* INTC - BCR renamed to MCR to match previous */ +/* version */ +/* INTC - VTES_PRC1 and HVEN_PRC1 added to MCR */ +/* INTC - CPR_PRC1, IACKR_PRC1 and EOIR_PRC1 */ +/* registers added */ +/* INTC - 512 PSR registers instead of 364 */ +/* ECSM - (Internal - mcm -> ecsm in the source files*/ +/* for generating the header file */ +/* ECSM - All bits and regs got an additional "p" in */ +/* the name in the user manual for "Platform" */ +/* -> deleted to match */ +/* ECSM - SWTCR, SWTSR and SWTIR don't exist in */ +/* MPC563xM -> deleted */ +/* ECSM - PROTECTION in the URM is one bitfield, */ +/* in mop5534 this are four: PROT1-4 -> */ +/* changed to match */ +/* EMCM - removed undocumented registers */ +/* ECSM - RAM ECC Syndrome is new in MPC563xM -> added */ +/* XBAR - removed AMPR and ASGPCR registers */ +/* XBAR - removed HPE bits for nonexistant masters */ +/* EBI - added: D16_31, AD_MUX and SETA bits */ +/* EBI - Added reserved register at address 0x4. */ +/* EBI - Corrected number of chip selects in for both*/ +/* the EBI_CS and the CAL_EBI_CS */ +/* SIU - corrected number of GPDO registers and */ +/* allowed for maximum PCR registers. */ +/* SWT - add KEY bit to CR, correct WND (from WNO) */ +/* SWT - add SK register */ +/* PMC - moved bits from CFGR to Status Register (SR)*/ +/* PMC - Added SR */ +/* DECFIL - Added new bits DSEL, IBIE, OBIE, EDME, */ +/* TORE, & TRFE to MCR. Added IBIC, OBIC, */ +/* DIVRC, IBIF, OBIF, DIVR to MSR. */ +/* changed OUTTEG to OUTTAG in OB */ +/* Change COEF to TAG in TAG register */ +/* EQADC - removed REDLCCR - not supported */ +/* FLASH - Aligned register and bit names with legacy*/ +/* 1.7 K. Odenthal 10/November/09 */ +/* SIU - changed PCR[n].PA from 3 bit to 4 bit */ +/* eTPU - changed WDTR_A.WDM from 1 bit to 2 bits */ +/* DECFIL - changed COEF.R and TAP.R from 16 bit to */ +/* 32 bit */ +/* 2.0 K. Odenthal 12/February/2010 */ +/* TSENS - Temperature Sensor Module added to */ +/* header file */ +/* ANSI C Compliance - Register structures have a */ +/* Bitfield Tag ('B') tag only if there is */ +/* at least one Bitfiels defined. Empty */ +/* tags like 'vuint32_t:32;' are not */ +/* allowed. */ +/* DECFIL - removed MXCR register. This register is */ +/* not supported on this part */ +/* SIU - SWT_SEL bit added in SIU DIRER register */ +/* EDMA - removed HRSL, HRSH and GPOR registers. */ +/* Those registers are not supported in */ +/* that part. */ +/* ESCI - removed LDBG and DSF bits from LCR */ +/* registers. Those bits are not supported */ +/* in that part. */ +/* Those registers are not supported in */ +/* that part. */ +/**************************************************************************/ +/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ + +#ifndef _MPC563M_H_ +#define _MPC563M_H_ + +#include "typedefs.h" + +#ifdef __cplusplus +extern "C" { + +#endif /* + */ + +#ifdef __MWERKS__ +#pragma push +#pragma ANSI_strict off +#endif /* + */ + +/****************************************************************************/ +/* MODULE : FMPLL */ +/****************************************************************************/ + struct FMPLL_tag { + union { + vuint32_t R; + struct { + vuint32_t:1; + vuint32_t PREDIV:3; + vuint32_t MFD:5; + vuint32_t:1; + vuint32_t RFD:3; + vuint32_t LOCEN:1; + vuint32_t LOLRE:1; + vuint32_t LOCRE:1; + vuint32_t:1; /* Reserved in MPC563xM + + Deleted for legacy header version [mpc5534.h]: + + */ + vuint32_t LOLIRQ:1; + vuint32_t LOCIRQ:1; + vuint32_t:13; /* Reserved in MPC563xM + + Deleted for legacy header version [mpc5534.h]: + + + + + + */ + } B; + } SYNCR; + union { + vuint32_t R; + struct { + vuint32_t:22; + vuint32_t LOLF:1; + vuint32_t LOC:1; + vuint32_t MODE:1; + vuint32_t PLLSEL:1; + vuint32_t PLLREF:1; + vuint32_t LOCKS:1; + vuint32_t LOCK:1; + vuint32_t LOCF:1; + vuint32_t:2; /* Reserved in MPC563xM + + Deleted for legacy header version [mpc5534.h]: + + + + */ + } B; + } SYNSR; + union { + vuint32_t R; + struct { + vuint32_t EMODE:1; + vuint32_t CLKCFG:3; + vuint32_t:8; + vuint32_t EPREDIV:4; + vuint32_t:9; + vuint32_t EMFD:7; + } B; + } ESYNCR1; /* Enhanced Synthesizer Control Register 1 (ESYNCR1) (new in MPC563xM) Offset 0x0008 */ + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t LOCEN:1; + vuint32_t LOLRE:1; + vuint32_t LOCRE:1; + vuint32_t LOLIRQ:1; + vuint32_t LOCIRQ:1; + vuint32_t:17; + vuint32_t ERFD:2; + } B; + } ESYNCR2; /* Enhanced Synthesizer Control Register 2 (ESYNCR2) (new in MPC563xM) Offset 0x000C */ + int32_t FMPLL_reserved0[2]; + union { + vuint32_t R; + struct { + vuint32_t BSY:1; + vuint32_t MODEN:1; + vuint32_t MODSEL:1; + vuint32_t MODPERIOD:13; + vuint32_t:1; + vuint32_t INCSTEP:15; + } B; + } SYNFMMR; /* Synthesizer FM Modulation Register (SYNFMMR) (new in MPC563xM) Offset 0x0018 */ + }; +/****************************************************************************/ +/* MODULE : EBI */ +/****************************************************************************/ + struct CS_tag { + union { + vuint32_t R; + struct { + vuint32_t BA:17; /* */ + vuint32_t:3; /* */ + vuint32_t PS:1; /* */ + vuint32_t:3; /* */ + vuint32_t AD_MUX:1; /* new in MPC563xM */ + vuint32_t BL:1; /* */ + vuint32_t WEBS:1; /* */ + vuint32_t TBDIP:1; /* */ + vuint32_t:1; /* */ + vuint32_t SETA:1; /* new in MPC563xM */ + vuint32_t BI:1; /* */ + vuint32_t V:1; /* */ + } B; + } BR; /* EBI_BR */ + union { + vuint32_t R; + struct { + vuint32_t AM:17; /* */ + vuint32_t:7; /* */ + vuint32_t SCY:4; /* */ + vuint32_t:1; /* */ + vuint32_t BSCY:2; /* */ + vuint32_t:1; /* */ + } B; + } OR; /* EBI_OR */ + }; + struct CAL_CS_tag { + union { + vuint32_t R; + struct { + vuint32_t BA:17; /* */ + vuint32_t:3; /* */ + vuint32_t PS:1; /* */ + vuint32_t:3; /* */ + vuint32_t AD_MUX:1; /* new in MPC563xM */ + vuint32_t BL:1; /* */ + vuint32_t WEBS:1; /* */ + vuint32_t TBDIP:1; /* */ + vuint32_t:1; /* */ + vuint32_t SETA:1; /* new in MPC563xM */ + vuint32_t BI:1; /* */ + vuint32_t V:1; /* */ + } B; + } BR; /* EBI_CAL_BR */ + + union { + vuint32_t R; + struct { + vuint32_t AM:17; /* */ + vuint32_t:7; /* */ + vuint32_t SCY:4; /* */ + vuint32_t:1; /* */ + vuint32_t BSCY:2; /* */ + vuint32_t:1; /* */ + } B; + } OR; /* EBI_CAL_OR */ + + }; + + struct EBI_tag { + union { + vuint32_t R; + struct { + vuint32_t:5; /* */ + vuint32_t SIZEEN:1; /* SIZEN */ + vuint32_t SIZE:2; /* */ + vuint32_t:8; /* */ + vuint32_t ACGE:1; /* */ + vuint32_t EXTM:1; /* */ + vuint32_t EARB:1; /* */ + vuint32_t EARP:2; /* */ + vuint32_t:4; /* */ + vuint32_t MDIS:1; /* */ + vuint32_t:3; /* */ + vuint32_t D16_31:1; /* new in MPC563xM */ + vuint32_t AD_MUX:1; /* new in MPC563xM */ + vuint32_t DBM:1; /* */ + } B; + } MCR; /* EBI Module Configuration Register (MCR) EBI_MCR @baseaddress + 0x00 */ + + uint32_t EBI_reserved1[1]; + + union { + vuint32_t R; + struct { + vuint32_t:30; /* */ + vuint32_t TEAF:1; /* */ + vuint32_t BMTF:1; /* */ + } B; + } TESR; /* EBI Transfer Error Status Register (TESR) EBI_TESR @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; /* */ + vuint32_t BMT:8; /* */ + vuint32_t BME:1; /* */ + vuint32_t:7; /* */ + } B; + } BMCR; /* EBI_BMCR @baseaddress + 0x0C */ + + struct CS_tag CS[4]; + + uint32_t EBI_reserved2[4]; + + /* Calibration registers */ + struct CAL_CS_tag CAL_CS[4]; + + }; /* end of EBI_tag */ +/****************************************************************************/ +/* MODULE : FLASH */ +/****************************************************************************/ +/* 3 flash modules implemented. */ +/* HBL and HBS not used in Bank 0 / Array 0 */ +/* LML, SLL, LMS, PFCR1, PFAPR, PFCR2, and PFCR3 not used in */ +/* Bank 1 / Array 1 or Bank 1 / Array 3 */ +/****************************************************************************/ + struct FLASH_tag { + union { /* Module Configuration Register (MCR)@baseaddress + 0x00 */ + vuint32_t R; + struct { + vuint32_t EDC:1; /* ECC Data Correction (Read/Clear) */ + vuint32_t:4; /* Reserved */ + vuint32_t SIZE:3; /* Array Size (Read Only) */ + vuint32_t:1; /* Reserved */ + vuint32_t LAS:3; /* Low Address Space (Read Only) */ + vuint32_t:3; /* Reserved */ + vuint32_t MAS:1; /* Mid Address Space (Read Only) */ + vuint32_t EER:1; /* ECC Event Error (Read/Clear) *//* BBEPE and EPE */ + vuint32_t RWE:1; /* Read While Write Event Error (Read/Clear) */ + vuint32_t:2; /* Reserved */ + vuint32_t PEAS:1; /* Program/Erase Access Space (Read Only) */ + vuint32_t DONE:1; /* Status (Read Only) */ + vuint32_t PEG:1; /* Program/Erase Good (Read Only) */ + vuint32_t:4; /* Reserved *//* RSD PEG STOP RSVD */ + vuint32_t PGM:1; /* Program (Read/Write) */ + vuint32_t PSUS:1; /* Program Suspend (Read/Write) */ + vuint32_t ERS:1; /* Erase (Read/Write) */ + vuint32_t ESUS:1; /* Erase Suspend (Read/Write) */ + vuint32_t EHV:1; /* Enable High Voltage (Read/Write) */ + } B; + } MCR; + + union { /* Low/Mid-Address Space Block Locking Register (LML)@baseaddress + 0x04 */ + vuint32_t R; + struct { + vuint32_t LME:1; /* Low/Mid address space block enable (Read Only) */ + vuint32_t:10; /* Reserved */ + vuint32_t SLOCK:1; /*SLK *//* Shadow address space block lock (Read/Write) */ + vuint32_t:2; /* Reserved */ + vuint32_t MLOCK:2; /*MLK *//* Mid address space block lock (Read/Write) */ + vuint32_t:8; /* Reserved */ + vuint32_t LLOCK:8; /*LLK *//* Low address space block lock (Read/Write) */ + } B; + } LMLR; /*LML */ + + union { /* High-Address Space Block Locking Register (HBL) - @baseaddress + 0x08 */ + vuint32_t R; + struct { + vuint32_t HBE:1; /* High address space Block Enable (Read Only) */ + vuint32_t:27; /* Reserved */ + vuint32_t HBLOCK:4; /* High address space block lock (Read/Write) */ + } B; + } HLR; /*HBL */ + + union { /* Secondary Low/Mid-Address Space Block Locking Register (SLL)@baseaddress + 0x0C */ + vuint32_t R; + struct { + vuint32_t SLE:1; /* Secondary low/mid address space block enable (Read Only) */ + vuint32_t:10; /* Reserved */ + vuint32_t SSLOCK:1; /*SSLK *//* Secondary shadow address space block lock (Read/Write) */ + vuint32_t:2; /* Reserved */ + vuint32_t SMLOCK:2; /*SMK *//* Secondary mid address space block lock (Read/Write) */ + vuint32_t:8; /* Reserved */ + vuint32_t SLLOCK:8; /*SLK *//* Secondary low address space block lock (Read/Write) */ + } B; + } SLMLR; /*SLL */ + + union { /* Low/Mid-Address Space Block Select Register (LMS)@baseaddress + 0x10 */ + vuint32_t R; + struct { + vuint32_t:14; /* Reserved */ + vuint32_t MSEL:2; /*MSL *//* Mid address space block select (Read/Write) */ + vuint32_t:8; /* Reserved */ + vuint32_t LSEL:8; /*LSL *//* Low address space block select (Read/Write) */ + } B; + } LMSR; /*LMS */ + + union { /* High-Address Space Block Select Register (HBS) - not used@baseaddress + 0x14 */ + vuint32_t R; + struct { + vuint32_t:28; /* Reserved */ + vuint32_t HBSEL:4; /*HSL *//* High address space block select (Read/Write) */ + } B; + } HSR; /*HBS */ + + union { /* Address Register (ADR)@baseaddress + 0x18 */ + vuint32_t R; + struct { + vuint32_t SAD:1; /* Shadow address (Read Only) */ + vuint32_t:10; /* Reserved */ + vuint32_t ADDR:18; /*AD *//* Address 20-3 (Read Only) */ + vuint32_t:3; /* Reserved */ + } B; + } AR; /*ADR */ + + union { /* @baseaddress + 0x1C */ + vuint32_t R; + struct { + vuint32_t:7; /* Reserved */ + vuint32_t GCE:1; /* Global Configuration Enable (Read/Write) */ + vuint32_t:4; /* Reserved */ + vuint32_t M3PFE:1; /* Master 3 Prefetch Enable (Read/Write) */ + vuint32_t M2PFE:1; /* Master 2 Prefetch Enable (Read/Write) */ + vuint32_t M1PFE:1; /* Master 1 Prefetch Enable (Read/Write) */ + vuint32_t M0PFE:1; /* Master 0 Prefetch Enable (Read/Write) */ + vuint32_t APC:3; /* Address Pipelining Control (Read/Write) */ + vuint32_t WWSC:2; /* Write Wait State Control (Read/Write) */ + vuint32_t RWSC:3; /* Read Wait State Control (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t DPFEN:1; /*DPFE *//* Data Prefetch Enable (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t IPFEN:1; /*IPFE *//* Instruction Prefetch Enable (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t PFLIM:2; /* Prefetch Limit (Read/Write) */ + vuint32_t BFEN:1; /*BFE *//* Buffer Enable (Read/Write) */ + } B; + } BIUCR; /*PFCR1 */ + + union { /* @baseaddress + 0x20 */ + vuint32_t R; + struct { + vuint32_t:24; /* Reserved */ + vuint32_t M3AP:2; /* Master 3 Access Protection (Read/Write) */ + vuint32_t M2AP:2; /* Master 2 Access Protection (Read/Write) */ + vuint32_t M1AP:2; /* Master 1 Access Protection (Read/Write) */ + vuint32_t M0AP:2; /* Master 0 Access Protection (Read/Write) */ + } B; + } BIUAPR; /*PFAPR */ + + union { /* @baseaddress + 0x24 */ + vuint32_t R; + struct { + vuint32_t LBCFG:2; /* Line Buffer Configuration (Read/Write) */ + vuint32_t:30; /* Reserved */ + } B; + } BIUCR2; + + union { /* @baseaddress + 0x28 */ + vuint32_t R; + struct { + vuint32_t:25; /* Reserved */ + vuint32_t B1_DPFE:1; /* Bank1 Data Prefetch Enable (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t B1_IPFE:1; /* Bank1 Instruction Prefetch Enable (Read/Write) */ + vuint32_t:1; /* Reserved */ + vuint32_t B1_PFLIM:2; /* Bank1 Prefetch Limit (Read/Write) */ + vuint32_t B1_BFE:1; /* Bank1 Buffer Enable (Read/Write) */ + } B; + } PFCR3; + + int32_t FLASH_reserverd_89[4]; + + union { /* User Test 0 (UT0) register@baseaddress + 0x3c */ + vuint32_t R; + struct { + vuint32_t UTE:1; /* User test enable (Read/Clear) */ + vuint32_t SBCE:1; /* Single bit correction enable (Read/Clear) */ + vuint32_t:6; /* Reserved */ + vuint32_t DSI:8; /* Data syndrome input (Read/Write) */ + vuint32_t:9; /* Reserved */ + vuint32_t:1; /* Reserved (Read/Write) */ + vuint32_t MRE:1; /* Margin Read Enable (Read/Write) */ + vuint32_t MRV:1; /* Margin Read Value (Read/Write) */ + vuint32_t EIE:1; /* ECC data Input Enable (Read/Write) */ + vuint32_t AIS:1; /* Array Integrity Sequence (Read/Write) */ + vuint32_t AIE:1; /* Array Integrity Enable (Read/Write) */ + vuint32_t AID:1; /* Array Integrity Done (Read Only) */ + } B; + } UT0; + + union { /* User Test 1 (UT1) register@baseaddress + 0x40 */ + vuint32_t R; + struct { + vuint32_t DAI:32; /* Data Array Input (Read/Write) */ + } B; + } UT1; + + union { /* User Test 2 (UT2) register@baseaddress + 0x44 */ + vuint32_t R; + struct { + vuint32_t DAI:32; /* Data Array Input (Read/Write) */ + } B; + } UT2; + + union { /* User Multiple Input Signature Register 0-5 (UMISR[5])@baseaddress + 0x48 */ + vuint32_t R; + struct { + vuint32_t MS:32; /* Multiple input Signature (Read/Write) */ + } B; + } UMISR[5]; + + }; /* end of FLASH_tag */ +/****************************************************************************/ +/* MODULE : SIU */ +/****************************************************************************/ + struct SIU_tag { + union { + vuint32_t R; + struct { + vuint32_t S_F:1; /* Identifies the Manufacturer S/F */ + vuint32_t FLASH_SIZE_1:4; /* Define major Flash memory size (see Table 15-4 for details) Flash Size 1 */ + vuint32_t FLASH_SIZE_2:4; /* Define Flash memory size, small granularity (see Table 15-5 for details) Flash Size 1 */ + vuint32_t TEMP_RANGE:2; /* Define maximum operating range Temp Range */ + vuint32_t:1; /* Reserved for future enhancements */ + vuint32_t MAX_FREQ:2; /* Define maximum device speed Max Freq */ + vuint32_t:1; /* Reserved for future enhancements */ + vuint32_t SUPPLY:1; /* Defines if the part is 5V or 3V Supply */ + vuint32_t PART_NUMBER:8; /* Contain the ASCII representation of the character that indicates the product Part Number */ + vuint32_t TBD:1; /* 1-bit field defined by SoC to describe optional feature, e.g., additional SPI */ + vuint32_t:2; /* Reserved for future enhancements */ + vuint32_t EE:1; /* Indicates if Data Flash is present */ + vuint32_t:3; /* Reserved for future enhancements */ + vuint32_t FR:1; /* Indicates if Data FlexRay is present */ + } B; + } MIDR2; /* MCU ID Register 2 SIU_MIDR2 @baseaddress + 0x4 */ + + union { + vuint32_t R; + struct { + vuint32_t PARTNUM:16; /* Device part number: 0x5633 */ + vuint32_t CSP:1; /* CSP configuration (new in MPC563xM) */ + vuint32_t PKG:5; /* Indicate the package the die is mounted in. (new in MPC563xM) */ + vuint32_t:2; /* Reserved */ + vuint32_t MASKNUM:8; /* MCU major mask number; updated for each complete resynthesis. MCU minor mask number; updated for each mask revision */ + } B; + } MIDR; /* MCU ID Register (MIDR) SIU_MIDR @baseaddress + 0x8 */ + + union { + vuint32_t R; + } TST; /* SIU Test Register (SIU_TST) SIU_TST @baseaddress + 0xC */ + + union { + vuint32_t R; + struct { + vuint32_t PORS:1; /* Power-On Reset Status */ + vuint32_t ERS:1; /* External Reset Status */ + vuint32_t LLRS:1; /* Loss of Lock Reset Status */ + vuint32_t LCRS:1; /* Loss of Clock Reset Status */ + vuint32_t WDRS:1; /* Watchdog Timer/Debug Reset Status */ + vuint32_t CRS:1; /* Checkstop Reset Status */ + vuint32_t SWTRS:1; /* Software Watchdog Timer Reset Status (new in MPC563xM) */ + vuint32_t:7; /* */ + vuint32_t SSRS:1; /* Software System Reset Status */ + vuint32_t SERF:1; /* Software External Reset Flag */ + vuint32_t WKPCFG:1; /* Weak Pull Configuration Pin Status */ + vuint32_t:11; /* */ + vuint32_t ABR:1; /* Auto Baud Rate (new in MPC563xM) */ + vuint32_t BOOTCFG:2; /* Reset Configuration Pin Status */ + vuint32_t RGF:1; /* RESET Glitch Flag */ + } B; + } RSR; /* Reset Status Register (SIU_RSR) SIU_RSR @baseaddress + 0x10 */ + + union { + vuint32_t R; + struct { + vuint32_t SSR:1; /* Software System Reset */ + vuint32_t SER:1; /* Software External Reset */ + vuint32_t:14; /* */ + vuint32_t CRE:1; /* Checkstop Reset Enable */ + vuint32_t:15; /* */ + } B; + } SRCR; /* System Reset Control Register (SRCR) SIU_SRCR @baseaddress + 0x14 */ + + union { + vuint32_t R; + struct { + vuint32_t NMI:1; /* Non-Maskable Interrupt Flag (new in MPC563xM) */ + vuint32_t:7; /* */ + vuint32_t SWT:1; /* Software Watch Dog Timer Interrupt Flag, from platform (new in MPC563xM) */ + vuint32_t:7; /* */ + vuint32_t EIF15:1; /* External Interrupt Request Flag x */ + vuint32_t EIF14:1; /* External Interrupt Request Flag x */ + vuint32_t EIF13:1; /* External Interrupt Request Flag x */ + vuint32_t EIF12:1; /* External Interrupt Request Flag x */ + vuint32_t EIF11:1; /* External Interrupt Request Flag x */ + vuint32_t EIF10:1; /* External Interrupt Request Flag x */ + vuint32_t EIF9:1; /* External Interrupt Request Flag x */ + vuint32_t EIF8:1; /* External Interrupt Request Flag x */ + vuint32_t:3; /* (reserved in MPC563xM) */ + vuint32_t EIF4:1; /* External Interrupt Request Flag x */ + vuint32_t EIF3:1; /* External Interrupt Request Flag x */ + vuint32_t:2; /* (reserved in MPC563xM) */ + vuint32_t EIF0:1; /* External Interrupt Request Flag x */ + } B; + } EISR; /* SIU External Interrupt Status Register (EISR) SIU_EISR @baseaddress + 0x18 */ + + union { + vuint32_t R; + struct { + vuint32_t NMI_SEL:1; /* NMI Interrupt Platform Input Selection (new in MPC563xM) */ + vuint32_t:7; /* */ + vuint32_t SWT_SEL:1; + vuint32_t:7; + vuint32_t EIRE15:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE14:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE13:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE12:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE11:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE10:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE9:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE8:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE7:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE6:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE5:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE4:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE3:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE2:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE1:1; /* External DMA/Interrupt Request Enable x */ + vuint32_t EIRE0:1; /* External DMA/Interrupt Request Enable x */ + } B; + } DIRER; /* DMA/Interrupt Request Enable Register (DIRER) SIU_DIRER @baseaddress + 0x1C */ + + union { + vuint32_t R; + struct { + vuint32_t:28; /* */ + vuint32_t DIRS3:1; /* DMA/Interrupt Request Select x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t DIRS0:1; /* DMA/Interrupt Request Select x */ + } B; + } DIRSR; /* DMA/Interrupt Request Select Register (DIRSR) SIU_DIRSR @baseaddress + 0x20 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; /* */ + vuint32_t OVF15:1; /* Overrun Flag x */ + vuint32_t OVF14:1; /* Overrun Flag x */ + vuint32_t OVF13:1; /* Overrun Flag x */ + vuint32_t OVF12:1; /* Overrun Flag x */ + vuint32_t OVF11:1; /* Overrun Flag x */ + vuint32_t OVF10:1; /* Overrun Flag x */ + vuint32_t OVF9:1; /* Overrun Flag x */ + vuint32_t OVF8:1; /* Overrun Flag x */ + vuint32_t:3; /* reserved in MPC563xM */ + vuint32_t OVF4:1; /* Overrun Flag x */ + vuint32_t OVF3:1; /* Overrun Flag x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t OVF0:1; /* Overrun Flag x */ + } B; + } OSR; /* Overrun Status Register (OSR) SIU_OSR @baseaddress + 0x24 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; /* */ + vuint32_t ORE15:1; /* Overrun Request Enable x */ + vuint32_t ORE14:1; /* Overrun Request Enable x */ + vuint32_t ORE13:1; /* Overrun Request Enable x */ + vuint32_t ORE12:1; /* Overrun Request Enable x */ + vuint32_t ORE11:1; /* Overrun Request Enable x */ + vuint32_t ORE10:1; /* Overrun Request Enable x */ + vuint32_t ORE9:1; /* Overrun Request Enable x */ + vuint32_t ORE8:1; /* Overrun Request Enable x */ + vuint32_t:3; /* reserved in MPC563xM */ + vuint32_t ORE4:1; /* Overrun Request Enable x */ + vuint32_t ORE3:1; /* Overrun Request Enable x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t ORE0:1; /* Overrun Request Enable x */ + } B; + } ORER; /* Overrun Request Enable Register (ORER) SIU_ORER @baseaddress + 0x28 */ + + union { + vuint32_t R; + struct { + vuint32_t NMIRE:1; /* NMI Rising-Edge Event Enable x (new in MPC563xM) */ + vuint32_t:15; /* reserved in MPC563xM */ + vuint32_t IREE15:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE14:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE13:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE12:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE11:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE10:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE9:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE8:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t:3; /* reserved in MPC563xM */ + vuint32_t IREE4:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t IREE3:1; /* IRQ Rising-Edge Event Enable x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t IREE0:1; /* IRQ Rising-Edge Event Enable x */ + } B; + } IREER; /* External IRQ Rising-Edge Event Enable Register (IREER) SIU_IREER @baseaddress + 0x2C */ + + union { + vuint32_t R; + struct { + vuint32_t NMIFE:1; /* NMI Falling-Edge Event Enable x (new in MPC563xM) */ + vuint32_t Reserverd:15; /* */ + vuint32_t IFEE15:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE14:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE13:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE12:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE11:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE10:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE9:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE8:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t:3; /* reserved in MPC563xM */ + vuint32_t IFEE4:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t IFEE3:1; /* IRQ Falling-Edge Event Enable x */ + vuint32_t:2; /* reserved in MPC563xM */ + vuint32_t IFEE0:1; /* IRQ Falling-Edge Event Enable x */ + } B; + } IFEER; /* External IRQ Falling-Edge Event Enable Regi (IFEER) SIU_IFEER @baseaddress + 0x30 */ + + union { + vuint32_t R; + struct { + vuint32_t:28; /* */ + vuint32_t DFL:4; /* Digital Filter Length */ + } B; + } IDFR; /* External IRQ Digital Filter Register (IDFR) SIU_IDFR @baseaddress + 0x40 */ + + int32_t SIU_reserverd_153[3]; + + union { + vuint16_t R; + struct { + vuint16_t:2; /* */ + vuint16_t PA:4; /* */ + vuint16_t OBE:1; /* */ + vuint16_t IBE:1; /* */ + vuint16_t DSC:2; /* */ + vuint16_t ODE:1; /* */ + vuint16_t HYS:1; /* */ + vuint16_t SRC:2; /* */ + vuint16_t WPE:1; /* */ + vuint16_t WPS:1; /* */ + } B; + } PCR[512]; /* Pad Configuration Register (PCR) SIU_PCR @baseaddress + 0x600 */ + + int32_t SIU_reserverd_164[112]; + + union { + vuint8_t R; + struct { + vuint8_t:7; /* */ + vuint8_t PDO:1; /* */ + } B; + } GPDO[512]; /* GPIO Pin Data Output Register (GPDO) SIU_GDPO @baseaddress + 0x800 */ + + union { + vuint8_t R; + struct { + vuint8_t:7; /* */ + vuint8_t PDI:1; /* */ + } B; + } GPDI[256]; /* GPIO Pin Data Input Register (GDPI) SIU_GDPI @baseaddress + 0x900 */ + + union { + vuint32_t R; + struct { + vuint32_t TSEL5:2; /* eQADC Trigger 5 Input */ + vuint32_t TSEL4:2; /* eQADC Trigger 4 Input */ + vuint32_t TSEL3:2; /* eQADC Trigger 3 Input */ + vuint32_t TSEL2:2; /* eQADC Trigger 4 Input */ + vuint32_t TSEL1:2; /* eQADC Trigger 1 Input */ + vuint32_t TSEL0:2; /* eQADC Trigger 0 Input */ + vuint32_t:20; /* */ + } B; + } ETISR; /* eQADC Trigger Input Select Register (ETISR) SIU_ETISR @baseaddress + 0x904 */ + + union { + vuint32_t R; + struct { + vuint32_t ESEL15:2; /* External IRQ Input Select x */ + vuint32_t ESEL14:2; /* External IRQ Input Select x */ + vuint32_t ESEL13:2; /* External IRQ Input Select x */ + vuint32_t ESEL12:2; /* External IRQ Input Select x */ + vuint32_t ESEL11:2; /* External IRQ Input Select x */ + vuint32_t ESEL10:2; /* External IRQ Input Select x */ + vuint32_t ESEL9:2; /* External IRQ Input Select x */ + vuint32_t ESEL8:2; /* External IRQ Input Select x */ + vuint32_t ESEL7:2; /* External IRQ Input Select x */ + vuint32_t ESEL6:2; /* External IRQ Input Select x */ + vuint32_t ESEL5:2; /* External IRQ Input Select x */ + vuint32_t ESEL4:2; /* External IRQ Input Select x */ + vuint32_t ESEL3:2; /* External IRQ Input Select x */ + vuint32_t ESEL2:2; /* External IRQ Input Select x */ + vuint32_t ESEL1:2; /* External IRQ Input Select x */ + vuint32_t ESEL0:2; /* External IRQ Input Select x */ + } B; + } EIISR; /* External IRQ Input Select Register (EIISR) SIU_EIISR @baseaddress + 0x908 */ + + union { + vuint32_t R; + struct { + vuint32_t:8; /* reserved in MPC563xM */ + vuint32_t SINSELB:2; /* DSPI_B Data Input Select SIN-SELB */ + vuint32_t SSSELB:2; /* DSPI_B Slave Select Input Select SS-SELB */ + vuint32_t SCKSELB:2; /* DSPI_B Clock Input Select SCK-SELB */ + vuint32_t TRIGSELB:2; /* DSPI_B Trigger Input Select TRIG-SELB */ + vuint32_t SINSELC:2; /* DSPI_C Data Input Select SIN-SELC */ + vuint32_t SSSELC:2; /* DSPI_C Slave Select Input Select SSSELC */ + vuint32_t SCKSELC:2; /* DSPI_C Clock Input Select SCK-SELC */ + vuint32_t TRIGSELC:2; /* DSPI_C Trigger Input Select TRIG-SELC */ + vuint32_t:8; /* reserved in MPC563xM */ + } B; + } DISR; /* DSPI Input Select Register (DISR) SIU_DISR @baseaddress + 0x90c */ + + union { + vuint32_t R; + struct { + vuint32_t:2; /* */ + vuint32_t ETSEL5:5; /* eQADC queue X Enhanced Trigger Selection eTSEL5 */ + vuint32_t ETSEL4:5; /* eQADC queue X Enhanced Trigger Selection eTSEL4 */ + vuint32_t ETSEL3:5; /* eQADC queue X Enhanced Trigger Selection eTSEL3 */ + vuint32_t ETSEL2:5; /* eQADC queue X Enhanced Trigger Selection eTSEL2 */ + vuint32_t ETSEL1:5; /* eQADC queue X Enhanced Trigger Selection eTSEL1 */ + vuint32_t ETSEL0:5; /* eQADC queue X Enhanced Trigger Selection eTSEL0 */ + } B; + } ISEL3; /* MUX Select Register 3 (ISEL3) (new in MPC563xM) SIU_ISEL3 @baseaddress + 0x920 */ + + int32_t SIU_reserverd_214[4]; + + union { + vuint32_t R; + struct { + vuint32_t:11; /* */ + vuint32_t ESEL5:1; /* eSEL5 */ + vuint32_t:3; /* */ + vuint32_t ESEL4:1; /* eSEL4 */ + vuint32_t:3; /* */ + vuint32_t ESEL3:1; /* eSEL3 */ + vuint32_t:3; /* */ + vuint32_t ESEL2:1; /* eSEL2 */ + vuint32_t:3; /* */ + vuint32_t ESEL1:1; /* eSEL1 */ + vuint32_t:3; /* */ + vuint32_t ESEL0:1; /* eSEL0 */ + } B; + } ISEL8; /* MUX Select Register 8 (ISEL8) (new in MPC563xM) SIU_ISEL8 @baseaddress + 0x924 */ + + union { + vuint32_t R; + struct { + vuint32_t:27; /* */ + vuint32_t ETSEL0A:5; /* eTSEL0A */ + } B; + } ISEL9; /* MUX Select Register 9(ISEL9) SIU_ISEL9 @baseaddress + 0x980 */ + + int32_t SIU_reserverd_230[22]; + + union { + vuint32_t R; + struct { + vuint32_t:14; /* */ + vuint32_t MATCH:1; /* Compare Register Match */ + vuint32_t DISNEX:1; /* Disable Nexus */ + vuint32_t:14; /* */ + vuint32_t CRSE:1; /* Calibration Reflection Suppression Enable (new in MPC563xM) */ + vuint32_t:1; /* */ + } B; + } CCR; /* Chip Configuration Register (CCR) SIU_CCR @baseaddress + 0x984 */ + + union { + vuint32_t R; + struct { + vuint32_t:28; /* The ENGDIV bit is reserved in MPC563xM */ + vuint32_t EBTS:1; /* External Bus Tap Select */ + vuint32_t:1; /* */ + vuint32_t EBDF:2; /* External Bus Division Factor */ + } B; + } ECCR; /* External Clock Control Register (ECCR) SIU_ECCR @baseaddress + 0x988 */ + + union { + vuint32_t R; + } CARH; /* Compare A High Register (CARH) SIU_CMPAH @baseaddress + 0x98C */ + + union { + vuint32_t R; + } CARL; /* Compare A Low Register (CARL) SIU_CMPAL @baseaddress + 0x990 */ + + union { + vuint32_t R; + } CBRH; /* Compare B High Register (CBRH) SIU_CMPBH @baseaddress + 0x994 */ + + union { + vuint32_t R; + } CBRL; /* Compare B Low Register (CBRL) SIU_CMPBL @baseaddress + 0x9A0 */ + + int32_t SIU_reserverd_250[2]; + + union { + vuint32_t R; + struct { + vuint32_t:27; /* Reserved */ + vuint32_t BYPASS:1; /* Bypass bit BY-PASS */ + vuint32_t SYSCLKDIV:2; /* System Clock Divide SYS-CLKDIV */ + vuint32_t:2; /* Reserved */ + } B; + } SYSDIV; /* System Clock Register (SYSDIV) (new in MPC563xM) SIU_SYSDIV @baseaddress + 0x9A4 */ + + union { + vuint32_t R; + struct { + vuint32_t CPUSTP:1; /* CPU stop request. When asserted, a stop request is sent to the following modules: */ + vuint32_t:2; /* Reserved */ + vuint32_t SWTSTP:1; /* SWT stop request. When asserted, a stop request is sent to the Software Watchdog */ + vuint32_t:1; /* Reserved */ + vuint32_t TPUSTP:1; /* eTPU stop request. When asserted, a stop request is sent to the eTPU module. */ + vuint32_t NPCSTP:1; /* Nexus stop request. When asserted, a stop request is sent to the Nexus Controller. */ + vuint32_t EBISTP:1; /* EBI stop request. When asserted, a stop request is sent to the external bus */ + vuint32_t ADCSTP:1; /* eQADC stop request. When asserted, a stop request is sent to the eQADC module. */ + vuint32_t:1; /* Reserved */ + vuint32_t MIOSSTP:1; /* Stop mode request */ + vuint32_t DFILSTP:1; /* Decimation filter stop request. When asserted, a stop request is sent to the */ + vuint32_t:1; /* Reserved */ + vuint32_t PITSTP:1; /* PIT stop request. When asserted, a stop request is sent to the periodical internal */ + vuint32_t:3; /* Reserved */ + vuint32_t CNCSTP:1; /* FlexCAN C stop request. When asserted, a stop request is sent to the FlexCAN C */ + vuint32_t:1; /* Reserved */ + vuint32_t CNASTP:1; /* FlexCAN A stop request. When asserted, a stop request is sent to the FlexCAN A */ + vuint32_t:1; /* Reserved */ + vuint32_t SPICSTP:1; /* DSPI C stop request. When asserted, a stop request is sent to the DSPI C. */ + vuint32_t SPIBSTP:1; /* DSPI B stop request. When asserted, a stop request is sent to the DSPI B. */ + vuint32_t:7; /* Reserved */ + vuint32_t SCIBSTP:1; /* eSCI B stop request. When asserted, a stop request is sent to the eSCI B module. */ + vuint32_t SCIASTP:1; /* eSCI A stop request. When asserted, a stop request is sent to the eSCIA module. */ + } B; + } HLT; /* Halt Register (HLT) (new in MPC563xM) SIU_HLT @baseaddress + 0x9A8 */ + + union { + vuint32_t R; + struct { + vuint32_t CPUACK:1; /* CPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:2; /* Reserved */ + vuint32_t SWTACK:1; /* SWT stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:1; /* Reserved */ + vuint32_t TPUACK:1; /* eTPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t NPCACK:1; /* Nexus stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t EBIACK:1; /* EBI stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t ADCACK:1; /* eQADC stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:1; /* Reserved */ + vuint32_t MIOSACK:1; /* eMIOS stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t DFILACK:1; /* Decimation filter stop acknowledge. When asserted, indicates that a stop */ + vuint32_t:1; /* Reserved */ + vuint32_t PITACK:1; /* PIT stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:3; /* Reserved */ + vuint32_t CNCACK:1; /* FlexCAN C stop acknowledge. When asserted, indicates that a stop acknowledge */ + vuint32_t:1; /* Reserved */ + vuint32_t CNAACK:1; /* FlexCAN A stop acknowledge. When asserted, indicates that a stop acknowledge */ + vuint32_t:1; /* Reserved */ + vuint32_t SPICACK:1; /* DSPI C stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t SPIBACK:1; /* DSPI B stop acknowledge. When asserted, indicates that a stop acknowledge was */ + vuint32_t:7; /* Reserved */ + vuint32_t SCIBACK:1; /* eSCI B stop acknowledge */ + vuint32_t SCIAACK:1; /* eSCI A stop acknowledge. */ + } B; + } HLTACK; /* Halt Acknowledge Register (HLTACK) (new in MPC563xM) SIU_HLTACK @baseaddress + 0x9ac */ + + int32_t SIU_reserved3[21]; + + }; /* end of SIU_tag */ +/****************************************************************************/ +/* MODULE : EMIOS */ +/****************************************************************************/ + struct EMIOS_tag { + union { + vuint32_t R; + struct { + vuint32_t DOZEEN:1; /* new in MPC563xM */ + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t GTBE:1; + vuint32_t ETB:1; + vuint32_t GPREN:1; + vuint32_t:6; + vuint32_t SRV:4; + vuint32_t GPRE:8; + vuint32_t:8; + } B; + } MCR; /* Module Configuration Register EMIOSMCR */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t F23:1; + vuint32_t F22:1; + vuint32_t F21:1; + vuint32_t F20:1; + vuint32_t F19:1; + vuint32_t F18:1; + vuint32_t F17:1; + vuint32_t F16:1; + vuint32_t F15:1; + vuint32_t F14:1; + vuint32_t F13:1; + vuint32_t F12:1; + vuint32_t F11:1; + vuint32_t F10:1; + vuint32_t F9:1; + vuint32_t F8:1; + vuint32_t F7:1; + vuint32_t F6:1; + vuint32_t F5:1; + vuint32_t F4:1; + vuint32_t F3:1; + vuint32_t F2:1; + vuint32_t F1:1; + vuint32_t F0:1; + } B; + } GFR; /* Global FLAG Register EMIOSGFLAG */ + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t OU23:1; + vuint32_t OU22:1; + vuint32_t OU21:1; + vuint32_t OU20:1; + vuint32_t OU19:1; + vuint32_t OU18:1; + vuint32_t OU17:1; + vuint32_t OU16:1; + vuint32_t OU15:1; + vuint32_t OU14:1; + vuint32_t OU13:1; + vuint32_t OU12:1; + vuint32_t OU11:1; + vuint32_t OU10:1; + vuint32_t OU9:1; + vuint32_t OU8:1; + vuint32_t OU7:1; + vuint32_t OU6:1; + vuint32_t OU5:1; + vuint32_t OU4:1; + vuint32_t OU3:1; + vuint32_t OU2:1; + vuint32_t OU1:1; + vuint32_t OU0:1; + } B; + } OUDR; /* Output Update Disable Register EMIOSOUDIS */ + + union { + vuint32_t R; + struct { + vuint32_t:8; /* */ + vuint32_t CHDIS23:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS22:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS21:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS20:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS19:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS18:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS17:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS16:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS15:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS14:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS13:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS12:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS11:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS10:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS9:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS8:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS7:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS6:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS5:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS4:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS3:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS2:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS1:1; /* Enable Channel [n] bit */ + vuint32_t CHDIS0:1; /* Enable Channel [n] bit */ + } B; + } UCDIS; /* Disable Channel (EMIOSUCDIS) EMIOSUCDIS (new in MPC563xM) @baseaddress + 0x0C */ + + int32_t EMIOS_reserverd_30[4]; + + struct { + union { + vuint32_t R; /* Channel A Data Register */ + } CADR; /* EMIOSA */ + + union { + vuint32_t R; /* Channel B Data Register */ + } CBDR; /* EMIOSB */ + + union { + vuint32_t R; /* Channel Counter Register */ + } CCNTR; /* EMIOSCNT */ + + union { + vuint32_t R; + struct { + vuint32_t FREN:1; + vuint32_t ODIS:1; + vuint32_t ODISSL:2; + vuint32_t UCPRE:2; + vuint32_t UCPREN:1; + vuint32_t DMA:1; + vuint32_t:1; + vuint32_t IF:4; + vuint32_t FCK:1; + vuint32_t FEN:1; + vuint32_t:3; + vuint32_t FORCMA:1; + vuint32_t FORCMB:1; + vuint32_t:1; + vuint32_t BSL:2; + vuint32_t EDSEL:1; + vuint32_t EDPOL:1; + vuint32_t MODE:7; + } B; + } CCR; /* Channel Control Register EMIOSC */ + + union { + vuint32_t R; + struct { + vuint32_t OVR:1; + vuint32_t:15; + vuint32_t OVFL:1; + vuint32_t:12; + vuint32_t UCIN:1; + vuint32_t UCOUT:1; + vuint32_t FLAG:1; + } B; + } CSR; /* Channel Status Register EMIOSS */ + + union { + vuint32_t R; /* Alternate Channel A Data Register */ + } ALTA; /* new in MPC563xM EMIOSALTA */ + + uint32_t emios_channel_reserved[2]; + + } CH[24]; + + }; /* end of EMIOS_tag */ +/****************************************************************************/ +/* MODULE : ETPU */ +/****************************************************************************/ + struct ETPU_tag { /* offset 0x0000 */ + union { /* eTPU module configuration register@baseaddress + 0x00 */ + vuint32_t R; + struct { + vuint32_t GEC:1; /* Global Exception Clear */ + vuint32_t SDMERR:1; /* */ + vuint32_t WDTOA:1; /* */ + vuint32_t WDTOB:1; /* */ + vuint32_t MGE1:1; /* MGEA */ + vuint32_t MGE2:1; /* MGEB */ + vuint32_t ILF1:1; /* Invalid instruction flag eTPU A. ILFFA */ + vuint32_t ILF2:1; /* Invalid instruction flag eTPU B. ILFFB */ + vuint32_t SCMERR:1; /* . */ + vuint32_t:2; /* */ + vuint32_t SCMSIZE:5; /* Shared Code Memory size */ + vuint32_t:4; /* */ + vuint32_t SCMMISC:1; /* SCM MISC Flag */ + vuint32_t SCMMISF:1; /* SCM MISC Flag */ + vuint32_t SCMMISEN:1; /* SCM MISC Enable */ + vuint32_t:2; /* */ + vuint32_t VIS:1; /* SCM Visability */ + vuint32_t:5; /* */ + vuint32_t GTBE:1; /* Global Time Base Enable */ + } B; + } MCR; /* ETPU_MCR */ + + /* offset 0x0004 */ + union { /* eTPU coherent dual-parameter controller register@baseaddress + 0x04 */ + vuint32_t R; + struct { + vuint32_t STS:1; /* Start Status bit */ + vuint32_t CTBASE:5; /* Channel Transfer Base */ + vuint32_t PBASE:10; /* Parameter Buffer Base Address PBBASE */ + vuint32_t PWIDTH:1; /* Parameter Width */ + vuint32_t PARAM0:7; /* Channel Parameter 0 PARM0 */ + vuint32_t WR:1; /* */ + vuint32_t PARAM1:7; /* Channel Parameter 1 PARM1 */ + } B; + } CDCR; /*ETPU_CDCR */ + + vuint32_t ETPU_reserved_0; + + /* offset 0x000C */ + union { /* eTPU MISC Compare Register@baseaddress + 0x0c */ + vuint32_t R; + struct { + vuint32_t ETPUMISCCMP:32; /* Expected multiple input signature calculator compare register value. EMISCCMP */ + } B; + } MISCCMPR /*ETPU_MISCCMPR */ ; + + /* offset 0x0010 */ + union { /* eTPU SCM Off-Range Data Register@baseaddress + 0x10 */ + vuint32_t R; + struct { + vuint32_t ETPUSCMOFFDATA:32; /* SCM Off-range read data value. */ + } B; + } SCMOFFDATAR; /*ETPU_SCMOFFDATAR */ + + /* offset 0x0014 */ + union { /* eTPU Engine Configuration Register (ETPUA_ECR)@baseaddress + 0x14 */ + vuint32_t R; + struct { + vuint32_t FEND:1; /* Force END */ + vuint32_t MDIS:1; /* Low power Stop */ + vuint32_t:1; /* */ + vuint32_t STF:1; /* Stop Flag */ + vuint32_t:4; /* */ + vuint32_t HLTF:1; /* Halt Mode Flag */ + vuint32_t:3; /* */ + vuint32_t FCSS:1; + vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ + vuint32_t CDFC:2; /* */ + vuint32_t:1; /* */ + vuint32_t ERBA:5; /* */ + vuint32_t SPPDIS:1; /* */ + vuint32_t:2; /* */ + vuint32_t ETB:5; /* Entry Table Base */ + } B; + } ECR_A; /*ETPU_ECR */ + + vuint32_t ETPU_reserved_1[2]; + + /* offset 0x0020 */ + union { /* eTPU Time Base Configuration Register (ETPU_TBCR)@baseaddress + 0x20 */ + vuint32_t R; + struct { + vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ + vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ + vuint32_t AM:2; /* Angle Mode */ + vuint32_t:3; /* */ + vuint32_t TCR2P:6; /* TCR2 Prescaler Control */ + vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ + vuint32_t TCR1CS:1; /* */ + vuint32_t:5; /* */ + vuint32_t TCR1P:8; /* TCR1 Prescaler Control */ + } B; + } TBCR_A; /*ETPU_TBCR */ + + /* offset 0x0024 */ + union { /* eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)@baseaddress + 0x24 */ + vuint32_t R; + struct { + vuint32_t:8; /* */ + vuint32_t TCR1:24; /* TCR1 value. Used on matches and captures. For more information, see the eTPU reference manual. */ + } B; + } TB1R_A; /*ETPU_TB1R */ + + /* offset 0x0028 */ + union { /* eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)@baseaddress + 0x28 */ + vuint32_t R; + struct { + vuint32_t:8; /* */ + vuint32_t TCR2:24; /* TCR2 value. Used on matches and captures. For information on TCR2, see the eTPU reference manual. */ + } B; + } TB2R_A; /*ETPU_TB2R */ + + /* offset 0x002C */ + union { /* STAC Bus Configuration Register (ETPU_STACCR)@baseaddress + 0x2c */ + vuint32_t R; + struct { + vuint32_t REN1:1; /* Resource Enable TCR1 */ + vuint32_t RSC1:1; /* Resource Control TCR1 */ + vuint32_t:2; /* */ + vuint32_t SERVER_ID1:4; /* */ + vuint32_t:4; /* */ + vuint32_t SRV1:4; /* Resource Server Slot */ + vuint32_t REN2:1; /* Resource Enable TCR2 */ + vuint32_t RSC2:1; /* Resource Control TCR2 */ + vuint32_t:2; /* */ + vuint32_t SERVER_ID2:4; /* */ + vuint32_t:4; /* */ + vuint32_t SRV2:4; /* Resource Server Slot */ + } B; + } REDCR_A; /*ETPU_REDCR */ + + vuint32_t ETPU_reserved_2[12]; + + /* offset 0x0060 */ + union { /* ETPU1 WDTR Register */ + vuint32_t R; + struct { + vuint32_t WDM:2; + vuint32_t:14; + vuint32_t WDCNT:16; + } B; + } WDTR_A; + + vuint32_t ETPU1_reserved_3; + + /* offset 0x0068 */ + union { /* ETPU1 IDLE Register */ + vuint32_t R; + struct { + vuint32_t IDLE_CNT:31; + vuint32_t ICLR:1; + } B; + } IDLE_A; + + vuint32_t ETPU_reserved_4[101]; + + /* offset 0x0200 */ + union { /* eTPU Channel Interrupt Status Register (ETPU_CISR)@baseaddress + 0x200 */ + vuint32_t R; + struct { + vuint32_t CIS31:1; /* Channel 31 Interrut Status */ + vuint32_t CIS30:1; /* Channel 30 Interrut Status */ + vuint32_t CIS29:1; /* Channel 29 Interrut Status */ + vuint32_t CIS28:1; /* Channel 28 Interrut Status */ + vuint32_t CIS27:1; /* Channel 27 Interrut Status */ + vuint32_t CIS26:1; /* Channel 26 Interrut Status */ + vuint32_t CIS25:1; /* Channel 25 Interrut Status */ + vuint32_t CIS24:1; /* Channel 24 Interrut Status */ + vuint32_t CIS23:1; /* Channel 23 Interrut Status */ + vuint32_t CIS22:1; /* Channel 22 Interrut Status */ + vuint32_t CIS21:1; /* Channel 21 Interrut Status */ + vuint32_t CIS20:1; /* Channel 20 Interrut Status */ + vuint32_t CIS19:1; /* Channel 19 Interrut Status */ + vuint32_t CIS18:1; /* Channel 18 Interrut Status */ + vuint32_t CIS17:1; /* Channel 17 Interrut Status */ + vuint32_t CIS16:1; /* Channel 16 Interrut Status */ + vuint32_t CIS15:1; /* Channel 15 Interrut Status */ + vuint32_t CIS14:1; /* Channel 14 Interrut Status */ + vuint32_t CIS13:1; /* Channel 13 Interrut Status */ + vuint32_t CIS12:1; /* Channel 12 Interrut Status */ + vuint32_t CIS11:1; /* Channel 11 Interrut Status */ + vuint32_t CIS10:1; /* Channel 10 Interrut Status */ + vuint32_t CIS9:1; /* Channel 9 Interrut Status */ + vuint32_t CIS8:1; /* Channel 8 Interrut Status */ + vuint32_t CIS7:1; /* Channel 7 Interrut Status */ + vuint32_t CIS6:1; /* Channel 6 Interrut Status */ + vuint32_t CIS5:1; /* Channel 5 Interrut Status */ + vuint32_t CIS4:1; /* Channel 4 Interrut Status */ + vuint32_t CIS3:1; /* Channel 3 Interrut Status */ + vuint32_t CIS2:1; /* Channel 2 Interrut Status */ + vuint32_t CIS1:1; /* Channel 1 Interrut Status */ + vuint32_t CIS0:1; /* Channel 0 Interrut Status */ + } B; + } CISR_A; /* ETPU_CISR */ + + int32_t ETPU_reserved_5[3]; + + /* offset 0x0210 */ + union { /* @baseaddress + 0x210 */ + vuint32_t R; + struct { + vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ + vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ + vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ + vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ + vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ + vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ + vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ + vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ + vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ + vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ + vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ + vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ + vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ + vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ + vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ + vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ + vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ + vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ + vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ + vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ + vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ + vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ + vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ + vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ + vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ + vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ + vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ + vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ + vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ + vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ + vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ + vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ + } B; + } CDTRSR_A; /* ETPU_CDTRSR */ + + int32_t ETPU_reserved_6[3]; + + /* offset 0x0220 */ + union { /* eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)@baseaddress + 0x220 */ + vuint32_t R; + struct { + vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ + vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ + vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ + vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ + vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ + vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ + vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ + vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ + vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ + vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ + vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ + vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ + vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ + vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ + vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ + vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ + vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ + vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ + vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ + vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ + vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ + vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ + vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ + vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ + vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ + vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ + vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ + vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ + vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ + vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ + vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ + vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ + } B; + } CIOSR_A; /* ETPU_CIOSR */ + + int32_t ETPU_reserved_7[3]; + + /* offset 0x0230 */ + union { /* eTPU Channel Data Transfer Request Overflow Status Register@baseaddress + 0x230 */ + vuint32_t R; + struct { + vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ + vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ + vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ + vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ + vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ + vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ + vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ + vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ + vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ + vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ + vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ + vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ + vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ + vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ + vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ + vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ + vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ + vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ + vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ + vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ + vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ + vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ + vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ + vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ + vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ + vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ + vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ + vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ + vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ + vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ + vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ + vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ + } B; + } CDTROSR_A; /* ETPU_CDTROSR */ + + int32_t ETPU_reserved_8[3]; + + /* offset 0x0240 */ + union { /* eTPU Channel Interrupt Enable Register (ETPU_CIER)@baseaddress + 0x240 */ + vuint32_t R; + struct { + vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ + vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ + vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ + vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ + vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ + vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ + vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ + vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ + vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ + vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ + vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ + vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ + vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ + vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ + vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ + vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ + vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ + vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ + vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ + vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ + vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ + vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ + vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ + vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ + vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ + vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ + vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ + vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ + vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ + vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ + vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ + vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ + } B; + } CIER_A; /* ETPU_CIER */ + + int32_t ETPU_reserved_9[3]; + + /* offset 0x0250 */ + union { /* eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)@baseaddress + 0x250 */ + vuint32_t R; + struct { + vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CDTRER_A; /* ETPU_CDTRER */ + + int32_t ETPU_reserved_10[3]; + + /* offset 0x0260 */ + union { /* ETPUWDSR - eTPU Watchdog Status Register */ + vuint32_t R; + struct { + vuint32_t WDS31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t WDS30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t WDS29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t WDS28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t WDS27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t WDS26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t WDS25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t WDS24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t WDS23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t WDS22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t WDS21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t WDS20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t WDS19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t WDS18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t WDS17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t WDS16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t WDS15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t WDS14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t WDS13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t WDS12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t WDS11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t WDS10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t WDS9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t WDS8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t WDS7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t WDS6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t WDS5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t WDS4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t WDS3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t WDS2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t WDS1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t WDS0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } WDSR_A; + + int32_t ETPU_reserved_11[7]; + + /* offset 0x0280 */ + union { /* ETPUCPSSR - eTPU Channel Pending Service Status Register */ + vuint32_t R; + struct { + vuint32_t SR31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t SR30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t SR29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t SR28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t SR27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t SR26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t SR25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t SR24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t SR23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t SR22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t SR21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t SR20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t SR19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t SR18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t SR17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t SR16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t SR15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t SR14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t SR13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t SR12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t SR11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t SR10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t SR9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t SR8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t SR7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t SR6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t SR5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t SR4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t SR3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t SR2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t SR1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t SR0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CPSSR_A; /* ETPU_CPSSR */ + + int32_t ETPU_reserved_12[3]; + + /* offset 0x0290 */ + union { /* ETPUCSSR - eTPU Channel Service Status Register */ + vuint32_t R; + struct { + vuint32_t SS31:1; /* Channel 31 Data Transfer Request Enable */ + vuint32_t SS30:1; /* Channel 30 Data Transfer Request Enable */ + vuint32_t SS29:1; /* Channel 29 Data Transfer Request Enable */ + vuint32_t SS28:1; /* Channel 28 Data Transfer Request Enable */ + vuint32_t SS27:1; /* Channel 27 Data Transfer Request Enable */ + vuint32_t SS26:1; /* Channel 26 Data Transfer Request Enable */ + vuint32_t SS25:1; /* Channel 25 Data Transfer Request Enable */ + vuint32_t SS24:1; /* Channel 24 Data Transfer Request Enable */ + vuint32_t SS23:1; /* Channel 23 Data Transfer Request Enable */ + vuint32_t SS22:1; /* Channel 22 Data Transfer Request Enable */ + vuint32_t SS21:1; /* Channel 21 Data Transfer Request Enable */ + vuint32_t SS20:1; /* Channel 20 Data Transfer Request Enable */ + vuint32_t SS19:1; /* Channel 19 Data Transfer Request Enable */ + vuint32_t SS18:1; /* Channel 18 Data Transfer Request Enable */ + vuint32_t SS17:1; /* Channel 17 Data Transfer Request Enable */ + vuint32_t SS16:1; /* Channel 16 Data Transfer Request Enable */ + vuint32_t SS15:1; /* Channel 15 Data Transfer Request Enable */ + vuint32_t SS14:1; /* Channel 14 Data Transfer Request Enable */ + vuint32_t SS13:1; /* Channel 13 Data Transfer Request Enable */ + vuint32_t SS12:1; /* Channel 12 Data Transfer Request Enable */ + vuint32_t SS11:1; /* Channel 11 Data Transfer Request Enable */ + vuint32_t SS10:1; /* Channel 10 Data Transfer Request Enable */ + vuint32_t SS9:1; /* Channel 9 Data Transfer Request Enable */ + vuint32_t SS8:1; /* Channel 8 Data Transfer Request Enable */ + vuint32_t SS7:1; /* Channel 7 Data Transfer Request Enable */ + vuint32_t SS6:1; /* Channel 6 Data Transfer Request Enable */ + vuint32_t SS5:1; /* Channel 5 Data Transfer Request Enable */ + vuint32_t SS4:1; /* Channel 4 Data Transfer Request Enable */ + vuint32_t SS3:1; /* Channel 3 Data Transfer Request Enable */ + vuint32_t SS2:1; /* Channel 2 Data Transfer Request Enable */ + vuint32_t SS1:1; /* Channel 1 Data Transfer Request Enable */ + vuint32_t SS0:1; /* Channel 0 Data Transfer Request Enable */ + } B; + } CSSR_A; /* ETPU_CSSR */ + + int32_t ETPU_reserved_13[3]; + int32_t ETPU_reserved_14[88]; + +/***************************** Channels ********************************/ +/* Note not all devices implement all channels or even 2 engines */ +/* Each eTPU engine can implement 64 channels, however most devcies */ +/* only implemnet 32 channels. The eTPU block can implement 1 or 2 */ +/* engines per instantiation */ +/***********************************************************************/ + + struct { + union { /* eTPU Channel n Configuration Register (ETPU_CnCR)@baseaddress + 0x400 */ + vuint32_t R; + struct { + vuint32_t CIE:1; /* Channel Interruput Enable */ + vuint32_t DTRE:1; /* Data Transfer Request Enable */ + vuint32_t CPR:2; /* Channel Priority */ + vuint32_t:2; /* */ + vuint32_t ETPD:1; /* This bit selects which channel signal, input or output, is used in the entry point selection */ + vuint32_t ETCS:1; /* Entry Table Condition Select */ + vuint32_t:3; /* */ + vuint32_t CFS:5; /* Channel Function Select */ + vuint32_t ODIS:1; /* Output disable */ + vuint32_t OPOL:1; /* output polarity */ + vuint32_t:3; /* */ + vuint32_t CPBA:11; /* Channel Parameter Base Address */ + } B; + } CR; /* ETPU_CnCR */ + + union { /* eTPU Channel n Status Control Register (ETPU_CnSCR)@baseaddress + 0x404 */ + vuint32_t R; + struct { + vuint32_t CIS:1; /* Channel Interruput Status */ + vuint32_t CIOS:1; /* Channel Interruput Overflow Status */ + vuint32_t:6; /* */ + vuint32_t DTRS:1; /* Data Transfer Status */ + vuint32_t DTROS:1; /* Data Transfer Overflow Status */ + vuint32_t:6; /* */ + vuint32_t IPS:1; /* Input Pin State */ + vuint32_t OPS:1; /* Output Pin State */ + vuint32_t OBE:1; /* Output Pin State */ + vuint32_t:11; /* */ + vuint32_t FM1:1; /* Function mode */ + vuint32_t FM0:1; /* Function mode */ + } B; + } SCR; /* ETPU_CnSCR */ + + union { /* eTPU channel host service request register (ETPU_CnHSRR)@baseaddress + 0x408 */ + vuint32_t R; + struct { + vuint32_t:29; /* Host Service Request */ + vuint32_t HSR:3; /* */ + } B; + } HSRR; /* ETPU_CnHSRR */ + int32_t ETPU_reserved_18; + + } CHAN[127]; + /**** Note: Not all channels implemented on all devices. Up 64 can be implemented on */ + }; /* end of ETPU_tag */ +/****************************************************************************/ +/* MODULE : XBAR */ +/****************************************************************************/ + struct XBAR_tag { + union { + vuint32_t R; + struct { + vuint32_t:4; /* Master 7 Priority - Not implemented */ + vuint32_t:4; /* Master 6 Priority - Not implemented */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ + vuint32_t:1; /* */ + vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ + vuint32_t:1; /* */ + vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ + } B; + } MPR0; /* Master Priority Register for Slave port 0 @baseaddress + 0x00 - Flash */ + + int32_t XBAR_reserverd_35[3]; + + union { + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ + vuint32_t:6; /* Slave General Purpose Control Register Reserved */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:6; /* */ + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; /* */ + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; /* */ + vuint32_t PARK:3; /* PARK */ + } B; + } SGPCR0; /* Slave General Purpose Control Register 0 @baseaddress + 0x10 */ + + int32_t XBAR_reserverd_71[59]; + + union { + vuint32_t R; + struct { + vuint32_t:4; /* Master 7 Priority - Not implemented */ + vuint32_t:4; /* Master 6 Priority - Not implemented */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ + vuint32_t:1; /* */ + vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ + vuint32_t:1; /* */ + vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ + } B; + } MPR1; /* Master Priority Register for Slave port 1 @baseaddress + 0x100 */ + + int32_t XBAR_reserverd_105[3]; + + union { + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ + vuint32_t:6; /* Slave General Purpose Control Register Reserved */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:6; /* */ + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; /* */ + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; /* */ + vuint32_t PARK:3; /* PARK */ + } B; + } SGPCR1; /* Slave General Purpose Control Register 1 @baseaddress + 0x110 */ + + int32_t XBAR_reserverd_141[59]; + +/* Slave General Purpose Control Register 2 @baseaddress + 0x210 - not implemented */ + + int32_t XBAR_reserverd_211[64]; + + union { + vuint32_t R; + struct { + vuint32_t:4; /* Master 7 Priority - Not implemented */ + vuint32_t:4; /* Master 6 Priority - Not implemented */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ + vuint32_t:1; /* */ + vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ + vuint32_t:1; /* */ + vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ + } B; + } MPR3; /* Master Priority Register for Slave port 3 @baseaddress + 0x300 */ + + int32_t XBAR_reserverd_245[3]; + + union { + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ + vuint32_t:6; /* Slave General Purpose Control Register Reserved */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:6; /* */ + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; /* */ + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; /* */ + vuint32_t PARK:3; /* PARK */ + } B; + } SGPCR3; /* Slave General Purpose Control Register 3 @baseaddress + 0x310 */ + + int32_t XBAR_reserverd_281[59]; + + /* Slave General Purpose Control Register 4 @baseaddress + 0x410 - not implemented */ + + int32_t XBAR_reserverd_351[64]; + + /* Slave XBAR Port 5 Not implemented @baseaddress + 0x510 */ + + int32_t XBAR_reserverd_421[64]; + + /* Slave Port 6 not implemented @baseaddress + 0x610 */ + + int32_t XBAR_reserverd_491[64]; + + union { + vuint32_t R; + struct { + vuint32_t:4; /* Master 7 Priority - Not implemented */ + vuint32_t:4; /* Master 6 Priority - Not implemented */ + vuint32_t:4; /* Master 5 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ + vuint32_t:4; /* Master 3 Priority - Not implemented */ + vuint32_t:1; /* */ + vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ + vuint32_t:1; /* */ + vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ + vuint32_t:1; /* */ + vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ + } B; + } MPR7; /* Master Priority Register for Slave port 7 @baseaddress + 0x700 */ + + int32_t XBAR_reserverd_525[3]; + + union { + vuint32_t R; + struct { + vuint32_t RO:1; /* Read Only */ + vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ + vuint32_t:6; /* Slave General Purpose Control Register Reserved */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ + vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ + vuint32_t:6; /* */ + vuint32_t ARB:2; /* Arbitration Mode */ + vuint32_t:2; /* */ + vuint32_t PCTL:2; /* Parking Control */ + vuint32_t:1; /* */ + vuint32_t PARK:3; /* PARK */ + } B; + } SGPCR7; /* Slave General Purpose Control Register 7 @baseaddress + 0x710 */ + + int32_t XBAR_reserverd_561[59]; + + union { + vuint32_t R; + struct { + vuint32_t:29; /* */ + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MGPCR0; /* Master General Purpose Control Register 0 @baseaddress + 0x800 */ + + int32_t XBAR_reserverd_564[63]; + + union { + vuint32_t R; + struct { + vuint32_t:29; /* */ + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MGPCR1; /* Master General Purpose Control Register 1 @baseaddress + 0x900 */ + + int32_t XBAR_reserverd_567[63]; + + union { + vuint32_t R; + struct { + vuint32_t:29; /* */ + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MGPCR2; /* Master General Purpose Control Register 2 @baseaddress + 0xA00 */ + + int32_t XBAR_reserverd_570[63]; + + /* Master General Purpose Control Register 3 not implemented @baseaddress + 0xB00 */ + + int32_t XBAR_reserverd_573[64]; + + union { + vuint32_t R; + struct { + vuint32_t:29; /* */ + vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ + } B; + } MGPCR4; /* Master General Purpose Control Register 4 @baseaddress + 0xC00 */ + + int32_t XBAR_reserverd_576[64]; + + /* Master General Purpose Control Register 5 not implemented @baseaddress + 0xD00 */ + + int32_t XBAR_reserverd_579[64]; + + /* Master General Purpose Control Register 6 not implemented @baseaddress + 0xE00 */ + + int32_t XBAR_reserverd_582[64]; + + /* Master General Purpose Control Register 7 not implemented @baseaddress + 0xF00 */ + + }; /* end of XBAR_tag */ +/****************************************************************************/ +/* MODULE : ECSM */ +/****************************************************************************/ + struct ECSM_tag { + /* SWTCR, SWTSR and SWTIR don't exist in MPC563xM */ + uint32_t ecsm_reserved1[16]; + + uint8_t ecsm_reserved3[3]; /* base + 0x40 */ + + union { + vuint8_t R; + struct { + vuint8_t:6; + vuint8_t ERNCR:1; /* EPRNCR */ + vuint8_t EFNCR:1; /* EPFNCR */ + } B; + } ECR; /* ECC Configuration Register */ + + uint8_t ecsm_reserved4[3]; /* base + 0x44 */ + + union { + vuint8_t R; + struct { + vuint8_t:6; + vuint8_t RNCE:1; /* PRNCE */ + vuint8_t FNCE:1; /* PFNCE */ + } B; + } ESR; /* ECC Status Register */ + + /* EEGR don't exist in MPC563xM */ + uint32_t ecsm_reserved4a[2]; + + union { + vuint32_t R; + struct { + vuint32_t FEAR:32; /* PFEAR */ + } B; + } FEAR; /* Flash ECC Address Register PFEAR - 0x50 */ + + uint16_t ecsm_reserved4b; + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t FEMR:4; /* PFEMR */ + } B; + } FEMR; /* Flash ECC Master Register PFEMR */ + + union { + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROT0:1; /* PROTECTION */ + vuint8_t PROT1:1; /* PROTECTION */ + vuint8_t PROT2:1; /* PROTECTION */ + vuint8_t PROT3:1; /* PROTECTION */ + } B; + } FEAT; /* Flash ECC Attributes Register PFEAT */ + + union { + vuint32_t R; + struct { + vuint32_t FEDH:32; /* PFEDR */ + } B; + } FEDRH; /* Flash ECC Data High Register PFEDRH */ + + union { + vuint32_t R; + struct { + vuint32_t FEDL:32; /* PFEDR */ + } B; + } FEDRL; /* Flash ECC Data Low Register PFEDRL */ + + union { + vuint32_t R; + struct { + vuint32_t REAR:32; /* PREAR */ + } B; + } REAR; /* RAM ECC Address PREAR */ + + uint8_t ecsm_reserved5; + + union { + vuint8_t R; + struct { + vuint8_t PRESR:8; + } B; + } PRESR; /* RAM ECC Syndrome (new in MPC563xM) */ + + union { + vuint8_t R; + struct { + vuint8_t:4; + vuint8_t REMR:4; /* PREMR */ + } B; + } REMR; /* RAM ECC Master PREMR */ + + union { + vuint8_t R; + struct { + vuint8_t WRITE:1; + vuint8_t SIZE:3; + vuint8_t PROT0:1; /* PROTECTION */ + vuint8_t PROT1:1; /* PROTECTION */ + vuint8_t PROT2:1; /* PROTECTION */ + vuint8_t PROT3:1; /* PROTECTION */ + } B; + } REAT; /* RAM ECC Attributes Register PREAT */ + + union { + vuint32_t R; + struct { + vuint32_t REDH:32; /* PREDR */ + } B; + } REDRH; /* RAM ECC Data High Register PREDRH */ + + union { + vuint32_t R; + struct { + vuint32_t REDL:32; /* PREDR */ + } B; + } REDRL; /* RAMECC Data Low Register PREDRL */ + + }; +/****************************************************************************/ +/* MODULE : EDMA */ +/****************************************************************************/ + struct EDMA_tag { + union { + vuint32_t R; + struct { + vuint32_t:14; /* Reserved */ + vuint32_t CX:1; /* Cancel Transfer (new in MPC563xM) */ + vuint32_t ECX:1; /* Error Cancel Transfer (new in MPC563xM) */ + vuint32_t GRP3PRI:2; /* Channel Group 3 Priority (new in MPC563xM) */ + vuint32_t GRP2PRI:2; /* Channel Group 2 Priority (new in MPC563xM) */ + vuint32_t GRP1PRI:2; /* Channel Group 1 Priority */ + vuint32_t GRP0PRI:2; /* Channel Group 0 Priority */ + vuint32_t EMLM:1; /* Enable Minor Loop Mapping (new in MPC563xM) */ + vuint32_t CLM:1; /* Continuous Link Mode (new in MPC563xM) */ + vuint32_t HALT:1; /* Halt DMA Operations (new in MPC563xM) */ + vuint32_t HOE:1; /* Halt On Error (new in MPC563xM) */ + vuint32_t ERGA:1; /* Enable Round Robin Group Arbitration */ + vuint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */ + vuint32_t EDBG:1; /* Enable Debug */ + vuint32_t EBW:1; /* Enable Buffered Writes */ + } B; + } CR; /* DMA Control Register DMACR @baseaddress + 0x0 */ + + union { + vuint32_t R; + struct { + vuint32_t VLD:1; /* Logical OR of all DMAERRH */ + + vuint32_t:14; /* Reserved */ + vuint32_t ECX:1; /* (new in MPC563xM) */ + vuint32_t GPE:1; /* Group Priority Error */ + vuint32_t CPE:1; /* Channel Priority Error */ + vuint32_t ERRCHN:6; /* ERRCHN[5:0] Error Channel Number or The channel number of the last recorded error */ + vuint32_t SAE:1; /* Source Address Error 0 */ + vuint32_t SOE:1; /* Source Offset Error */ + vuint32_t DAE:1; /* Destination Address Error */ + vuint32_t DOE:1; /* Destination Offset Error */ + vuint32_t NCE:1; /* Nbytes/Citer Configuration Error */ + vuint32_t SGE:1; /* Scatter/Gather Configuration Error */ + vuint32_t SBE:1; /* Source Bus Error */ + vuint32_t DBE:1; /* Destination Bus Error */ + + } B; + } ESR; /* DMAES Error Status Register */ + + uint32_t edma_reserved_erqrh; + + union { + vuint32_t R; + struct { + vuint32_t ERQ31:1; + vuint32_t ERQ30:1; + vuint32_t ERQ29:1; + vuint32_t ERQ28:1; + vuint32_t ERQ27:1; + vuint32_t ERQ26:1; + vuint32_t ERQ25:1; + vuint32_t ERQ24:1; + vuint32_t ERQ23:1; + vuint32_t ERQ22:1; + vuint32_t ERQ21:1; + vuint32_t ERQ20:1; + vuint32_t ERQ19:1; + vuint32_t ERQ18:1; + vuint32_t ERQ17:1; + vuint32_t ERQ16:1; + vuint32_t ERQ15:1; + vuint32_t ERQ14:1; + vuint32_t ERQ13:1; + vuint32_t ERQ12:1; + vuint32_t ERQ11:1; + vuint32_t ERQ10:1; + vuint32_t ERQ09:1; + vuint32_t ERQ08:1; + vuint32_t ERQ07:1; + vuint32_t ERQ06:1; + vuint32_t ERQ05:1; + vuint32_t ERQ04:1; + vuint32_t ERQ03:1; + vuint32_t ERQ02:1; + vuint32_t ERQ01:1; + vuint32_t ERQ00:1; + } B; + } ERQRL; /* DMAERQL ,DMA Enable Request Register Low */ + + uint32_t edma_reserved_eeirh; + + union { + vuint32_t R; + struct { + vuint32_t EEI31:1; + vuint32_t EEI30:1; + vuint32_t EEI29:1; + vuint32_t EEI28:1; + vuint32_t EEI27:1; + vuint32_t EEI26:1; + vuint32_t EEI25:1; + vuint32_t EEI24:1; + vuint32_t EEI23:1; + vuint32_t EEI22:1; + vuint32_t EEI21:1; + vuint32_t EEI20:1; + vuint32_t EEI19:1; + vuint32_t EEI18:1; + vuint32_t EEI17:1; + vuint32_t EEI16:1; + vuint32_t EEI15:1; + vuint32_t EEI14:1; + vuint32_t EEI13:1; + vuint32_t EEI12:1; + vuint32_t EEI11:1; + vuint32_t EEI10:1; + vuint32_t EEI09:1; + vuint32_t EEI08:1; + vuint32_t EEI07:1; + vuint32_t EEI06:1; + vuint32_t EEI05:1; + vuint32_t EEI04:1; + vuint32_t EEI03:1; + vuint32_t EEI02:1; + vuint32_t EEI01:1; + vuint32_t EEI00:1; + } B; + } EEIRL; /* DMAEEIL , DMA Enable Error Interrupt Register Low */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 SERQ:7 */ + } SERQR; /* DMASERQ , DMA Set Enable Request Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CERQ:7 */ + } CERQR; /* DMACERQ , DMA Clear Enable Request Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 SEEI:7 */ + } SEEIR; /* DMASEEI , DMA Set Enable Error Interrupt Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CEEI:7 */ + } CEEIR; /* DMACEEI , DMA Clear Enable Error Interrupt Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CINT:7 */ + } CIRQR; /* DMACINT , DMA Clear Interrupt Request Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CERR:7 */ + } CER; /* DMACERR , DMA Clear error Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 SSRT:7 */ + } SSBR; /* DMASSRT , Set Start Bit Register */ + + union { + vuint8_t R; + vuint8_t B; /* NOP:1 CDNE:7 */ + } CDSBR; /* DMACDNE , Clear Done Status Bit Register */ + + uint32_t edma_reserved_irqrh; + + union { + vuint32_t R; + struct { + vuint32_t INT31:1; + vuint32_t INT30:1; + vuint32_t INT29:1; + vuint32_t INT28:1; + vuint32_t INT27:1; + vuint32_t INT26:1; + vuint32_t INT25:1; + vuint32_t INT24:1; + vuint32_t INT23:1; + vuint32_t INT22:1; + vuint32_t INT21:1; + vuint32_t INT20:1; + vuint32_t INT19:1; + vuint32_t INT18:1; + vuint32_t INT17:1; + vuint32_t INT16:1; + vuint32_t INT15:1; + vuint32_t INT14:1; + vuint32_t INT13:1; + vuint32_t INT12:1; + vuint32_t INT11:1; + vuint32_t INT10:1; + vuint32_t INT09:1; + vuint32_t INT08:1; + vuint32_t INT07:1; + vuint32_t INT06:1; + vuint32_t INT05:1; + vuint32_t INT04:1; + vuint32_t INT03:1; + vuint32_t INT02:1; + vuint32_t INT01:1; + vuint32_t INT00:1; + } B; + } IRQRL; /* DMAINTL , DMA Interrupt Request Low */ + + uint32_t edma_reserved_erh; + + union { + vuint32_t R; + struct { + vuint32_t ERR31:1; + vuint32_t ERR30:1; + vuint32_t ERR29:1; + vuint32_t ERR28:1; + vuint32_t ERR27:1; + vuint32_t ERR26:1; + vuint32_t ERR25:1; + vuint32_t ERR24:1; + vuint32_t ERR23:1; + vuint32_t ERR22:1; + vuint32_t ERR21:1; + vuint32_t ERR20:1; + vuint32_t ERR19:1; + vuint32_t ERR18:1; + vuint32_t ERR17:1; + vuint32_t ERR16:1; + vuint32_t ERR15:1; + vuint32_t ERR14:1; + vuint32_t ERR13:1; + vuint32_t ERR12:1; + vuint32_t ERR11:1; + vuint32_t ERR10:1; + vuint32_t ERR09:1; + vuint32_t ERR08:1; + vuint32_t ERR07:1; + vuint32_t ERR06:1; + vuint32_t ERR05:1; + vuint32_t ERR04:1; + vuint32_t ERR03:1; + vuint32_t ERR02:1; + vuint32_t ERR01:1; + vuint32_t ERR00:1; + } B; + } ERL; /* DMAERRL , DMA Error Low */ + + int32_t edma_reserverd_hrsh[1]; + + int32_t edma_reserverd_hrsl[1]; + + int32_t edma_reserverd_gpor[1]; + + int32_t EDMA_reserverd_223[49]; + + union { + vuint8_t R; + struct { + vuint8_t ECP:1; + vuint8_t DPA:1; + vuint8_t GRPPRI:2; + vuint8_t CHPRI:4; + } B; + } CPR[64]; /* DCHPRI [32] , Channel n Priority */ + + uint32_t edma_reserved2[944]; + +/****************************************************************************/ +/* DMA2 Transfer Control Descriptor */ +/****************************************************************************/ + + struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */ + vuint32_t SADDR; /* source address */ + + vuint16_t SMOD:5; /* source address modulo */ + vuint16_t SSIZE:3; /* source transfer size */ + vuint16_t DMOD:5; /* destination address modulo */ + vuint16_t DSIZE:3; /* destination transfer size */ + vint16_t SOFF; /* signed source address offset */ + vuint32_t NBYTES; /* inner (“minor”) byte count */ + vint32_t SLAST; /* last destination address adjustment, or + + scatter/gather address (if e_sg = 1) */ + vuint32_t DADDR; /* destination address */ + vuint16_t CITERE_LINK:1; + vuint16_t CITER:15; + vint16_t DOFF; /* signed destination address offset */ + vint32_t DLAST_SGA; + vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */ + vuint16_t BITER:15; + vuint16_t BWC:2; /* bandwidth control */ + vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ + vuint16_t DONE:1; /* channel done */ + vuint16_t ACTIVE:1; /* channel active */ + vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ + vuint16_t E_SG:1; /* enable scatter/gather descriptor */ + vuint16_t D_REQ:1; /* disable ipd_req when done */ + vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ + vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ + vuint16_t START:1; /* explicit channel start */ + } TCD[64]; /* TCD [32] , transfer_control_descriptor */ + }; + + struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */ + + struct tcd_alt1_t { + vuint32_t SADDR; /* source address */ + + vuint16_t SMOD:5; /* source address modulo */ + vuint16_t SSIZE:3; /* source transfer size */ + vuint16_t DMOD:5; /* destination address modulo */ + vuint16_t DSIZE:3; /* destination transfer size */ + vint16_t SOFF; /* signed source address offset */ + vuint32_t NBYTES; /* inner (“minor”) byte count */ + vint32_t SLAST; /* last destination address adjustment, or + + scatter/gather address (if e_sg = 1) */ + vuint32_t DADDR; /* destination address */ + vuint16_t CITERE_LINK:1; + vuint16_t CITERLINKCH:6; + vuint16_t CITER:9; + vint16_t DOFF; /* signed destination address offset */ + vint32_t DLAST_SGA; + vuint16_t BITERE_LINK:1; /* beginning (“major”) iteration count */ + vuint16_t BITERLINKCH:6; + vuint16_t BITER:9; + vuint16_t BWC:2; /* bandwidth control */ + vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ + vuint16_t DONE:1; /* channel done */ + vuint16_t ACTIVE:1; /* channel active */ + vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ + vuint16_t E_SG:1; /* enable scatter/gather descriptor */ + vuint16_t D_REQ:1; /* disable ipd_req when done */ + vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ + vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ + vuint16_t START:1; /* explicit channel start */ + } TCD[64]; /* TCD [32] , transfer_control_descriptor */ + }; + +/****************************************************************************/ +/* MODULE : INTC */ +/****************************************************************************/ + struct INTC_tag { + union { + vuint32_t R; + struct { + vuint32_t:18; /* Reserved */ + vuint32_t VTES_PRC1:1; /* Vector Table Entry Size for PRC1 (new in MPC563xM) */ + vuint32_t:4; /* Reserved */ + vuint32_t HVEN_PRC1:1; /* Hardware Vector Enable for PRC1 (new in MPC563xM) */ + vuint32_t:2; /* Reserved */ + vuint32_t VTES:1; /* Vector Table Entry Size for PRC0 VTES_PRC0 */ + vuint32_t:4; /* Reserved */ + vuint32_t HVEN:1; /* Hardware Vector Enable for PRC0 HVEN_PRC0 */ + } B; + } MCR; /* INTC Module Configuration Register (MCR) INTC_BCR @baseaddress + 0x00 */ + int32_t INTC_reserverd_10[1]; + + union { + vuint32_t R; + struct { + vuint32_t:28; /* Reserved */ + vuint32_t PRI:4; /* Priority */ + } B; + } CPR; /* INTC Current Priority Register for Processor 0 (CPR) INTC_CPR_PRC0 @baseaddress + 0x08 */ + + int32_t INTC_reserved_1; /* CPR_PRC1 - INTC Current Priority Register for Processor 1 (CPR_PRC1) INTC_CPR_PRC1 @baseaddress + 0x0c */ + + union { + vuint32_t R; + struct { + vuint32_t VTBA:21; /* Vector Table Base Address VTBA_PRC0 */ + vuint32_t INTVEC:9; /* Interrupt Vector INTVEC_PRC0 */ + vuint32_t:2; /* Reserved */ + } B; + } IACKR; /* INTC Interrupt Acknowledge Register for Processor 0 (IACKR) INTC_IACKR_PRC0 @baseaddress + 0x10 */ + + int32_t INTC_reserverd_2; /* IACKR_PRC1 - INTC Interrupt Acknowledge Register for Processor 1 (IACKR_PRC1) INTC_IACKR_PRC1 @baseaddress + 0x14 */ + + union { + vuint32_t R; + } EOIR; /* INTC End of Interrupt Register for Processor 0 (EOIR) INTC_EOIR_PRC0 @baseaddress + 0x18 */ + + int32_t INTC_reserverd_3; /* EOIR_PRC1 - INTC End of Interrupt Register for Processor 1 (EOIR_PRC1) INTC_EOIR_PRC1 @baseaddress + 0x1C */ + + union { + vuint8_t R; + struct { + vuint8_t:6; /* Reserved */ + vuint8_t SET:1; /* Set Flag bits */ + vuint8_t CLR:1; /* Clear Flag bits */ + } B; + } SSCIR[8]; /* INTC Software Set/Clear Interrupt Registers (SSCIR) INTC_SSCIRn @baseaddress + 0x20 */ + + int32_t INTC_reserverd_32[6]; + + union { + vuint8_t R; + struct { + vuint8_t PRC_SEL:2; /* Processor Select (new in MPC563xM) */ + vuint8_t:2; /* Reserved */ + vuint8_t PRI:4; /* Priority Select */ + } B; + } PSR[512]; /* INTC Priority Select Registers (PSR) INTC_PSR @baseaddress + 0x40 */ + + }; /* end of INTC_tag */ +/****************************************************************************/ +/* MODULE : EQADC */ +/****************************************************************************/ + struct EQADC_tag { + union { + vuint32_t R; + struct { + vuint32_t:24; + vuint32_t ICEA0:1; + vuint32_t ICEA1:1; + vuint32_t:1; + vuint32_t ESSIE:2; + vuint32_t:1; + vuint32_t DBG:2; + } B; + } MCR; /* Module Configuration Register EQADC_MCR */ + + int32_t EQADC_reserved00; + + union { + vuint32_t R; + struct { + vuint32_t:6; + vuint32_t NMF:26; + } B; + } NMSFR; /* Null Message Send Format Register EQADC_NMSFR */ + + union { + vuint32_t R; + struct { + vuint32_t:28; + vuint32_t DFL:4; + } B; + } ETDFR; /* External Trigger Digital Filter Register EQADC_ETDFR */ + + union { + vuint32_t R; + struct { + vuint32_t CFPUSH:32; /* CF_PUSH */ + } B; + } CFPR[6]; /* CFIFO Push Registers EQADC_CFPR */ + + uint32_t eqadc_reserved1; + + uint32_t eqadc_reserved2; + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RFPOP:16; /* RF_POP */ + } B; + } RFPR[6]; /* Result FIFO Pop Registers EQADC_RFPR */ + + uint32_t eqadc_reserved3; + + uint32_t eqadc_reserved4; + + union { + vuint16_t R; + struct { + vuint16_t:3; + vuint16_t CFEE0:1; + vuint16_t STRME0:1; + vuint16_t SSE:1; + vuint16_t CFINV:1; + vuint16_t:1; + vuint16_t MODE:4; + vuint16_t AMODE0:4; /* CFIFO0 only */ + } B; + } CFCR[6]; /* CFIFO Control Registers EQADC_CFCR */ + + uint32_t eqadc_reserved5; + + union { + vuint16_t R; + struct { + vuint16_t NCIE:1; + vuint16_t TORIE:1; + vuint16_t PIE:1; + vuint16_t EOQIE:1; + vuint16_t CFUIE:1; + vuint16_t:1; + vuint16_t CFFE:1; + vuint16_t CFFS:1; + vuint16_t:4; + vuint16_t RFOIE:1; + vuint16_t:1; + vuint16_t RFDE:1; + vuint16_t RFDS:1; + } B; + } IDCR[6]; /* Interrupt and DMA Control Registers EQADC_IDCR */ + + uint32_t eqadc_reserved6; + + union { + vuint32_t R; + struct { + vuint32_t NCF:1; + vuint32_t TORF:1; + vuint32_t PF:1; + vuint32_t EOQF:1; + vuint32_t CFUF:1; + vuint32_t SSS:1; + vuint32_t CFFF:1; + vuint32_t:5; + vuint32_t RFOF:1; + vuint32_t:1; + vuint32_t RFDF:1; + vuint32_t:1; + vuint32_t CFCTR:4; + vuint32_t TNXTPTR:4; + vuint32_t RFCTR:4; + vuint32_t POPNXTPTR:4; + } B; + } FISR[6]; /* FIFO and Interrupt Status Registers EQADC_FISR */ + + uint32_t eqadc_reserved7; + + uint32_t eqadc_reserved8; + + union { + vuint16_t R; + struct { + vuint16_t:5; + vuint16_t TCCF:11; /* TC_CF */ + } B; + } CFTCR[6]; /* CFIFO Transfer Counter Registers EQADC_CFTCR */ + + uint32_t eqadc_reserved9; + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; /* CFS0_TCB0 */ + vuint32_t CFS1:2; /* CFS1_TCB0 */ + vuint32_t CFS2:2; /* CFS2_TCB0 */ + vuint32_t CFS3:2; /* CFS3_TCB0 */ + vuint32_t CFS4:2; /* CFS4_TCB0 */ + vuint32_t CFS5:2; /* CFS5_TCB0 */ + vuint32_t:5; + vuint32_t LCFTCB0:4; + vuint32_t TC_LCFTCB0:11; + } B; + } CFSSR0; /* CFIFO Status Register 0 EQADC_CFSSR0 */ + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; /* CFS0_TCB1 */ + vuint32_t CFS1:2; /* CFS1_TCB1 */ + vuint32_t CFS2:2; /* CFS2_TCB1 */ + vuint32_t CFS3:2; /* CFS3_TCB1 */ + vuint32_t CFS4:2; /* CFS4_TCB1 */ + vuint32_t CFS5:2; /* CFS5_TCB1 */ + vuint32_t:5; + vuint32_t LCFTCB1:4; + vuint32_t TC_LCFTCB1:11; + } B; + } CFSSR1; /* CFIFO Status Register 1 EQADC_CFSSR1 */ + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; /* CFS0_TSSI */ + vuint32_t CFS1:2; /* CFS1_TSSI */ + vuint32_t CFS2:2; /* CFS2_TSSI */ + vuint32_t CFS3:2; /* CFS3_TSSI */ + vuint32_t CFS4:2; /* CFS4_TSSI */ + vuint32_t CFS5:2; /* CFS5_TSSI */ + vuint32_t:4; + vuint32_t ECBNI:1; + vuint32_t LCFTSSI:4; + vuint32_t TC_LCFTSSI:11; + } B; + } CFSSR2; /* CFIFO Status Register 2 EQADC_CFSSR2 */ + + union { + vuint32_t R; + struct { + vuint32_t CFS0:2; + vuint32_t CFS1:2; + vuint32_t CFS2:2; + vuint32_t CFS3:2; + vuint32_t CFS4:2; + vuint32_t CFS5:2; + vuint32_t:20; + } B; + } CFSR; /* EQADC_CFSR */ + + uint32_t eqadc_reserved11; + + union { + vuint32_t R; + struct { + vuint32_t:21; + vuint32_t MDT:3; + vuint32_t:4; + vuint32_t BR:4; + } B; + } SSICR; /* SSI Control Register EQADC_SSICR */ + + union { + vuint32_t R; + struct { + vuint32_t RDV:1; + vuint32_t:5; + vuint32_t RDATA:26; + } B; + } SSIRDR; /* SSI Recieve Data Register EQADC_SSIRDR @ baseaddress + 0xB8 */ + + uint32_t eqadc_reserved11b[5]; + + uint32_t eqadc_reserved15; /* EQADC Red Line Client Configuration Register @ baseaddress + 0xD0 */ + /* REDLCCR is not implemented in the MPC563xM */ + + uint32_t eqadc_reserved12[11]; + + struct { + union { + vuint32_t R; + + /*B.CFIFOx_DATAw */ + + } R[4]; /*EQADC_CFxRw */ + + union { + vuint32_t R; + /*B.CFIFOx_EDATAw */ + } EDATA[4]; /*EQADC_CFxERw (new in MPC563xM) */ + + uint32_t eqadc_reserved13[8]; + + } CF[6]; + + uint32_t eqadc_reserved14[32]; + + struct { + union { + vuint32_t R; + /*RFIFOx_DATAw */ + } R[4]; /*EQADC_RFxRw */ + + uint32_t eqadc_reserved15[12]; + + } RF[6]; + + }; + /****************************************************************************/ +/* MODULE : DSPI */ +/****************************************************************************/ + struct DSPI_tag { + union { + vuint32_t R; + struct { + vuint32_t MSTR:1; + vuint32_t CONT_SCKE:1; + vuint32_t DCONF:2; + vuint32_t FRZ:1; + vuint32_t MTFE:1; + vuint32_t PCSSE:1; + vuint32_t ROOE:1; + vuint32_t PCSIS7:1; /* new in MPC563xM */ + vuint32_t PCSIS6:1; /* new in MPC563xM */ + vuint32_t PCSIS5:1; + vuint32_t PCSIS4:1; + vuint32_t PCSIS3:1; + vuint32_t PCSIS2:1; + vuint32_t PCSIS1:1; + vuint32_t PCSIS0:1; + vuint32_t DOZE:1; + vuint32_t MDIS:1; + vuint32_t DIS_TXF:1; + vuint32_t DIS_RXF:1; + vuint32_t CLR_TXF:1; + vuint32_t CLR_RXF:1; + vuint32_t SMPL_PT:2; + vuint32_t:7; + vuint32_t HALT:1; + } B; + } MCR; /* Module Configuration Register DSPI_MCR @baseaddress + 0x00 */ + + uint32_t dspi_reserved1; + + union { + vuint32_t R; + struct { + vuint32_t TCNT:16; /* SPI_TCNT */ + vuint32_t:16; + } B; + } TCR; /* DSPI Transfer Count Register DSPI_TCR @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t DBR:1; + vuint32_t FMSZ:4; + vuint32_t CPOL:1; + vuint32_t CPHA:1; + vuint32_t LSBFE:1; + vuint32_t PCSSCK:2; + vuint32_t PASC:2; + vuint32_t PDT:2; + vuint32_t PBR:2; + vuint32_t CSSCK:4; + vuint32_t ASC:4; + vuint32_t DT:4; + vuint32_t BR:4; + } B; + } CTAR[8]; /* Clock and Transfer Attributes Registers DSPI_CTARx @baseaddress + 0x0C - 0x28 */ + + union { + vuint32_t R; + struct { + vuint32_t TCF:1; + vuint32_t TXRXS:1; + vuint32_t:1; + vuint32_t EOQF:1; + vuint32_t TFUF:1; + vuint32_t:1; + vuint32_t TFFF:1; + vuint32_t:5; + vuint32_t RFOF:1; + vuint32_t:1; + vuint32_t RFDF:1; + vuint32_t:1; + vuint32_t TXCTR:4; + vuint32_t TXNXTPTR:4; + vuint32_t RXCTR:4; + vuint32_t POPNXTPTR:4; + } B; + } SR; /* Status Register DSPI_SR @baseaddress + 0x2C */ + + union { + vuint32_t R; + struct { + vuint32_t TCFRE:1; /*TCF_RE */ + vuint32_t:2; + vuint32_t EOQFRE:1; /*EQQF_RE */ + vuint32_t TFUFRE:1; /*TFUF_RE */ + vuint32_t:1; + vuint32_t TFFFRE:1; /*TFFF_RE */ + vuint32_t TFFFDIRS:1; /*TFFF_DIRS */ + vuint32_t:4; + vuint32_t RFOFRE:1; /*RFOF_RE */ + vuint32_t:1; + vuint32_t RFDFRE:1; /*RFDF_RE */ + vuint32_t RFDFDIRS:1; /*RFDF_DIRS */ + vuint32_t:16; + } B; + } RSER; /* DMA/Interrupt Request Select and Enable Register DSPI_RSER @baseaddress + 0x30 */ + + union { + vuint32_t R; + struct { + vuint32_t CONT:1; + vuint32_t CTAS:3; + vuint32_t EOQ:1; + vuint32_t CTCNT:1; + vuint32_t:2; + vuint32_t PCS7:1; /* new in MPC563xM */ + vuint32_t PCS6:1; /* new in MPC563xM */ + vuint32_t PCS5:1; + vuint32_t PCS4:1; + vuint32_t PCS3:1; + vuint32_t PCS2:1; + vuint32_t PCS1:1; + vuint32_t PCS0:1; + vuint32_t TXDATA:16; + } B; + } PUSHR; /* PUSH TX FIFO Register DSPI_PUSHR @baseaddress + 0x34 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; + } B; + } POPR; /* POP RX FIFO Register DSPI_POPR @baseaddress + 0x38 */ + + union { + vuint32_t R; + struct { + vuint32_t TXCMD:16; + vuint32_t TXDATA:16; + } B; + } TXFR[4]; /* Transmit FIFO Registers DSPI_TXFRx @baseaddress + 0x3c - 0x78 */ + + vuint32_t DSPI_reserved_txf[12]; + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXDATA:16; + } B; + } RXFR[4]; /* Transmit FIFO Registers DSPI_RXFRx @baseaddress + 0x7c - 0xB8 */ + + vuint32_t DSPI_reserved_rxf[12]; + + union { + vuint32_t R; + struct { + vuint32_t MTOE:1; + vuint32_t:1; + vuint32_t MTOCNT:6; + vuint32_t:3; + vuint32_t TSBC:1; + vuint32_t TXSS:1; + vuint32_t TPOL:1; + vuint32_t TRRE:1; + vuint32_t CID:1; + vuint32_t DCONT:1; + vuint32_t DSICTAS:3; + vuint32_t:4; + vuint32_t DPCS7:1; + vuint32_t DPCS6:1; + vuint32_t DPCS5:1; + vuint32_t DPCS4:1; + vuint32_t DPCS3:1; + vuint32_t DPCS2:1; + vuint32_t DPCS1:1; + vuint32_t DPCS0:1; + } B; + } DSICR; /* DSI Configuration Register DSPI_DSICR @baseaddress + 0xBC */ + + union { + vuint32_t R; + struct { + vuint32_t SER_DATA:32; /* 32bit instead of 16 in MPC563xM */ + } B; + } SDR; /* DSI Serialization Data Register DSPI_SDR @baseaddress + 0xC0 */ + + union { + vuint32_t R; + struct { + vuint32_t ASER_DATA:32; /* 32bit instead of 16 in MPC563xM */ + } B; + } ASDR; /* DSI Alternate Serialization Data Register DSPI_ASDR @baseaddress + 0xC4 */ + + union { + vuint32_t R; + struct { + vuint32_t COMP_DATA:32; /* 32bit instead of 16 in MPC563xM */ + } B; + } COMPR; /* DSI Transmit Comparison Register DSPI_COMPR @baseaddress + 0xC8 */ + + union { + vuint32_t R; + struct { + vuint32_t DESER_DATA:32; /* 32bit instead of 16 in MPC563xM */ + } B; + } DDR; /* DSI deserialization Data Register DSPI_DDR @baseaddress + 0xCC */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t TSBCNT:5; + vuint32_t:16; + vuint32_t DPCS1_7:1; + vuint32_t DPCS1_6:1; + vuint32_t DPCS1_5:1; + vuint32_t DPCS1_4:1; + vuint32_t DPCS1_3:1; + vuint32_t DPCS1_2:1; + vuint32_t DPCS1_1:1; + vuint32_t DPCS1_0:1; + } B; + } DSICR1; /* DSI Configuration Register 1 DSPI_DSICR1 @baseaddress + 0xD0 */ + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_tag { + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t SBR:13; + vuint32_t LOOPS:1; + vuint32_t:1; /* Reserved in MPC563xM */ + vuint32_t RSRC:1; + vuint32_t M:1; + vuint32_t WAKE:1; + vuint32_t ILT:1; + vuint32_t PE:1; + vuint32_t PT:1; + vuint32_t TIE:1; + vuint32_t TCIE:1; + vuint32_t RIE:1; + vuint32_t ILIE:1; + vuint32_t TE:1; + vuint32_t RE:1; + vuint32_t RWU:1; + vuint32_t SBK:1; + } B; + } CR1; /* Control Register 1 SCIBDH, SCIBDL, SCICR1, SCICR2 @baseaddress + 0x00 */ + + union { + vuint16_t R; + struct { + vuint16_t MDIS:1; + vuint16_t FBR:1; + vuint16_t BSTP:1; + vuint16_t IEBERR:1; /* BERIE */ + vuint16_t RXDMA:1; + vuint16_t TXDMA:1; + vuint16_t BRK13:1; /* BRCL */ + vuint16_t TXDIR:1; + vuint16_t BESM13:1; /* BESM */ + vuint16_t SBSTP:1; /* BESTP */ + vuint16_t RXPOL:1; + vuint16_t PMSK:1; + vuint16_t ORIE:1; + vuint16_t NFIE:1; + vuint16_t FEIE:1; + vuint16_t PFIE:1; + } B; + } CR2; /* Control Register 2 SCICR3, SCICR4 @baseaddress + 0x04 */ + + union { + vuint16_t R; + struct { + vuint16_t R8:1; /* RN */ + vuint16_t T8:1; /* TN */ + vuint16_t ERR:1; + vuint16_t:1; + vuint16_t R:4; + vuint8_t D; + } B; + } DR; /* Data Register SCIDRH, SCIDRL @baseaddress + 0x06 */ + + union { + vuint32_t R; + struct { + vuint32_t TDRE:1; + vuint32_t TC:1; + vuint32_t RDRF:1; + vuint32_t IDLE:1; + vuint32_t OR:1; + vuint32_t NF:1; + vuint32_t FE:1; + vuint32_t PF:1; + vuint32_t:3; + vuint32_t BERR:1; + vuint32_t:2; + vuint32_t TACT:1; + vuint32_t RAF:1; /* RACT */ + vuint32_t RXRDY:1; + vuint32_t TXRDY:1; + vuint32_t LWAKE:1; + vuint32_t STO:1; + vuint32_t PBERR:1; + vuint32_t CERR:1; + vuint32_t CKERR:1; + vuint32_t FRC:1; + vuint32_t:6; + vuint32_t UREQ:1; + vuint32_t OVFL:1; + } B; + } SR; /* Status Register SCISR1, SCIRSR2, LINSTAT1, LINSTAT2 @baseaddress + 0x08 */ + + union { + vuint32_t R; + struct { + vuint32_t LRES:1; + vuint32_t WU:1; + vuint32_t WUD0:1; + vuint32_t WUD1:1; + vuint32_t:2; /* reserved: LDBG and DSF not longer supported */ + vuint32_t PRTY:1; + vuint32_t LIN:1; + vuint32_t RXIE:1; + vuint32_t TXIE:1; + vuint32_t WUIE:1; + vuint32_t STIE:1; + vuint32_t PBIE:1; + vuint32_t CIE:1; + vuint32_t CKIE:1; + vuint32_t FCIE:1; + vuint32_t:6; + vuint32_t UQIE:1; + vuint32_t OFIE:1; + vuint32_t:8; + } B; + } LCR; /* LIN Control Register LINCTRL1, LINCTRL2, LINCTRL3 @baseaddress + 0x0C */ + + union { + vuint32_t R; + } LTR; /* LIN Transmit Register LINTX @baseaddress + 0x10 */ + + union { + vuint32_t R; + } LRR; /* LIN Recieve Register LINRX @baseaddress + 0x14 */ + + union { + vuint32_t R; + struct { + vuint32_t P:16; + vuint32_t:3; + vuint32_t SYNM:1; + vuint32_t EROE:1; + vuint32_t ERFE:1; + vuint32_t ERPE:1; + vuint32_t M2:1; + vuint32_t:8; + } B; + } LPR; /* LIN CRC Polynom Register LINCRCP1, LINCRCP2, SCICR5 @baseaddress + 0x18 */ + + }; +/****************************************************************************/ +/* MODULE : eSCI */ +/****************************************************************************/ + struct ESCI_12_13_bit_tag { + union { + vuint16_t R; + struct { + vuint16_t R8:1; + vuint16_t T8:1; + vuint16_t ERR:1; + vuint16_t:1; + vuint16_t D:12; + } B; + } DR; /* Data Register */ + }; +/****************************************************************************/ +/* MODULE : FlexCAN */ +/****************************************************************************/ + struct FLEXCAN_BUF_t { + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t CODE:4; + vuint32_t:1; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t PRIO:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ + } DATA; + + }; /* end of FLEXCAN_BUF_t */ + + struct FLEXCAN_RXFIFO_t { + union { + vuint32_t R; + struct { + vuint32_t:9; + vuint32_t SRR:1; + vuint32_t IDE:1; + vuint32_t RTR:1; + vuint32_t LENGTH:4; + vuint32_t TIMESTAMP:16; + } B; + } CS; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t STD_ID:11; + vuint32_t EXT_ID:18; + } B; + } ID; + + union { + /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ + /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ + vuint32_t W[2]; /* Data buffer in words (32 bits) */ + /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ + } DATA; + + uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */ + + union { + vuint32_t R; + } IDTABLE[8]; + + }; /* end of FLEXCAN_RXFIFO_t */ + + struct FLEXCAN2_tag { + union { + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FRZ:1; + vuint32_t FEN:1; /* new in MPC563xM */ + vuint32_t HALT:1; + vuint32_t NOTRDY:1; /* NOT_RDY */ + vuint32_t WAK_MSK:1; /* new in MPC563xM */ + vuint32_t SOFTRST:1; /* SOFT_RST */ + vuint32_t FRZACK:1; /* FRZ_ACK */ + vuint32_t SUPV:1; /* new in MPC563xM */ + vuint32_t SLF_WAK:1; /* new in MPC563xM */ + + vuint32_t WRNEN:1; /* WRN_EN */ + + vuint32_t MDISACK:1; /* LPM_ACK */ + vuint32_t WAK_SRC:1; /* new in MPC563xM */ + vuint32_t DOZE:1; /* new in MPC563xM */ + + vuint32_t SRXDIS:1; /* SRX_DIS */ + vuint32_t MBFEN:1; /* BCC */ + vuint32_t:2; + + vuint32_t LPRIO_EN:1; /* new in MPC563xM */ + vuint32_t AEN:1; /* new in MPC563xM */ + vuint32_t:2; + vuint32_t IDAM:2; /* new in MPC563xM */ + vuint32_t:2; + + vuint32_t MAXMB:6; + } B; + } MCR; /* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t PRESDIV:8; + vuint32_t RJW:2; + vuint32_t PSEG1:3; + vuint32_t PSEG2:3; + vuint32_t BOFFMSK:1; /* BOFF_MSK */ + vuint32_t ERRMSK:1; /* ERR_MSK */ + vuint32_t CLKSRC:1; /* CLK_SRC */ + vuint32_t LPB:1; + vuint32_t TWRNMSK:1; /* TWRN_MSK */ + vuint32_t RWRNMSK:1; /* RWRN_MSK */ + vuint32_t:2; + vuint32_t SMP:1; + vuint32_t BOFFREC:1; /* BOFF_REC */ + vuint32_t TSYN:1; + vuint32_t LBUF:1; + vuint32_t LOM:1; + vuint32_t PROPSEG:3; + } B; /* Control Register */ + } CR; /* CTRL */ + + union { + vuint32_t R; + } TIMER; /* Free Running Timer */ + + int32_t FLEXCAN_reserved00; + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t MI:29; + } B; + } RXGMASK; /* RX Global Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t MI:29; + } B; + } RX14MASK; /* RX 14 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:3; + vuint32_t MI:29; + } B; + } RX15MASK; /* RX 15 Mask */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t RXECNT:8; + vuint32_t TXECNT:8; + } B; + } ECR; /* Error Counter Register */ + + union { + vuint32_t R; + struct { + vuint32_t:14; + vuint32_t TWRNINT:1; /* TWRN_INT */ + vuint32_t RWRNINT:1; /* RWRN_INT */ + vuint32_t BIT1ERR:1; /* BIT1_ERR */ + vuint32_t BIT0ERR:1; /* BIT0_ERR */ + vuint32_t ACKERR:1; /* ACK_ERR */ + vuint32_t CRCERR:1; /* CRC_ERR */ + vuint32_t FRMERR:1; /* FRM_ERR */ + vuint32_t STFERR:1; /* STF_ERR */ + vuint32_t TXWRN:1; /* TX_WRN */ + vuint32_t RXWRN:1; /* RX_WRN */ + vuint32_t IDLE:1; + vuint32_t TXRX:1; + vuint32_t FLTCONF:2; /* FLT_CONF */ + vuint32_t:1; + vuint32_t BOFFINT:1; /* BOFF_INT */ + vuint32_t ERRINT:1; /* ERR_INT */ + vuint32_t WAK_INT:1; /* new in MPC563xM */ + } B; + } ESR; /* Error and Status Register */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63M:1; + vuint32_t BUF62M:1; + vuint32_t BUF61M:1; + vuint32_t BUF60M:1; + vuint32_t BUF59M:1; + vuint32_t BUF58M:1; + vuint32_t BUF57M:1; + vuint32_t BUF56M:1; + vuint32_t BUF55M:1; + vuint32_t BUF54M:1; + vuint32_t BUF53M:1; + vuint32_t BUF52M:1; + vuint32_t BUF51M:1; + vuint32_t BUF50M:1; + vuint32_t BUF49M:1; + vuint32_t BUF48M:1; + vuint32_t BUF47M:1; + vuint32_t BUF46M:1; + vuint32_t BUF45M:1; + vuint32_t BUF44M:1; + vuint32_t BUF43M:1; + vuint32_t BUF42M:1; + vuint32_t BUF41M:1; + vuint32_t BUF40M:1; + vuint32_t BUF39M:1; + vuint32_t BUF38M:1; + vuint32_t BUF37M:1; + vuint32_t BUF36M:1; + vuint32_t BUF35M:1; + vuint32_t BUF34M:1; + vuint32_t BUF33M:1; + vuint32_t BUF32M:1; + } B; /* Interruput Masks Register */ + } IMRH; /* IMASK2 */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31M:1; + vuint32_t BUF30M:1; + vuint32_t BUF29M:1; + vuint32_t BUF28M:1; + vuint32_t BUF27M:1; + vuint32_t BUF26M:1; + vuint32_t BUF25M:1; + vuint32_t BUF24M:1; + vuint32_t BUF23M:1; + vuint32_t BUF22M:1; + vuint32_t BUF21M:1; + vuint32_t BUF20M:1; + vuint32_t BUF19M:1; + vuint32_t BUF18M:1; + vuint32_t BUF17M:1; + vuint32_t BUF16M:1; + vuint32_t BUF15M:1; + vuint32_t BUF14M:1; + vuint32_t BUF13M:1; + vuint32_t BUF12M:1; + vuint32_t BUF11M:1; + vuint32_t BUF10M:1; + vuint32_t BUF09M:1; + vuint32_t BUF08M:1; + vuint32_t BUF07M:1; + vuint32_t BUF06M:1; + vuint32_t BUF05M:1; + vuint32_t BUF04M:1; + vuint32_t BUF03M:1; + vuint32_t BUF02M:1; + vuint32_t BUF01M:1; + vuint32_t BUF00M:1; + } B; /* Interruput Masks Register */ + } IMRL; /* IMASK1 */ + + union { + vuint32_t R; + struct { + vuint32_t BUF63I:1; + vuint32_t BUF62I:1; + vuint32_t BUF61I:1; + vuint32_t BUF60I:1; + vuint32_t BUF59I:1; + vuint32_t BUF58I:1; + vuint32_t BUF57I:1; + vuint32_t BUF56I:1; + vuint32_t BUF55I:1; + vuint32_t BUF54I:1; + vuint32_t BUF53I:1; + vuint32_t BUF52I:1; + vuint32_t BUF51I:1; + vuint32_t BUF50I:1; + vuint32_t BUF49I:1; + vuint32_t BUF48I:1; + vuint32_t BUF47I:1; + vuint32_t BUF46I:1; + vuint32_t BUF45I:1; + vuint32_t BUF44I:1; + vuint32_t BUF43I:1; + vuint32_t BUF42I:1; + vuint32_t BUF41I:1; + vuint32_t BUF40I:1; + vuint32_t BUF39I:1; + vuint32_t BUF38I:1; + vuint32_t BUF37I:1; + vuint32_t BUF36I:1; + vuint32_t BUF35I:1; + vuint32_t BUF34I:1; + vuint32_t BUF33I:1; + vuint32_t BUF32I:1; + } B; /* Interruput Flag Register */ + } IFRH; /* IFLAG2 */ + + union { + vuint32_t R; + struct { + vuint32_t BUF31I:1; + vuint32_t BUF30I:1; + vuint32_t BUF29I:1; + vuint32_t BUF28I:1; + vuint32_t BUF27I:1; + vuint32_t BUF26I:1; + vuint32_t BUF25I:1; + vuint32_t BUF24I:1; + vuint32_t BUF23I:1; + vuint32_t BUF22I:1; + vuint32_t BUF21I:1; + vuint32_t BUF20I:1; + vuint32_t BUF19I:1; + vuint32_t BUF18I:1; + vuint32_t BUF17I:1; + vuint32_t BUF16I:1; + vuint32_t BUF15I:1; + vuint32_t BUF14I:1; + vuint32_t BUF13I:1; + vuint32_t BUF12I:1; + vuint32_t BUF11I:1; + vuint32_t BUF10I:1; + vuint32_t BUF09I:1; + vuint32_t BUF08I:1; + vuint32_t BUF07I:1; + vuint32_t BUF06I:1; + vuint32_t BUF05I:1; + vuint32_t BUF04I:1; + vuint32_t BUF03I:1; + vuint32_t BUF02I:1; + vuint32_t BUF01I:1; + vuint32_t BUF00I:1; + } B; /* Interruput Flag Register */ + } IFRL; /* IFLAG1 */ + + uint32_t flexcan2_reserved2[19]; + +/****************************************************************************/ +/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ +/****************************************************************************/ + /* Standard Buffer Structure */ + struct FLEXCAN_BUF_t BUF[64]; + + /* RX FIFO and Buffer Structure *//* New options in MPC563xM */ + /*struct FLEXCAN_RXFIFO_t RXFIFO; */ + /*struct FLEXCAN_BUF_t BUF[56]; */ +/****************************************************************************/ + + uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 *//* (New in MPC563xM) Address Base + 0x0034 */ + + union { + vuint32_t R; + struct { + vuint32_t MI:32; + } B; /* RX Individual Mask Registers */ + } RXIMR[64]; /* (New in MPC563xM) Address Base + 0x0880 */ + + }; /* end of FLEXCAN_tag */ +/****************************************************************************/ +/* MODULE : Decimation Filter (DECFIL) */ +/****************************************************************************/ + struct DECFIL_tag { + union { + vuint32_t R; + struct { + vuint32_t MDIS:1; + vuint32_t FREN:1; + vuint32_t:1; + vuint32_t FRZ:1; + vuint32_t SRES:1; + vuint32_t:2; /* CASCD not supported in MPC563xM */ + vuint32_t IDEN:1; + vuint32_t ODEN:1; + vuint32_t ERREN:1; + vuint32_t:1; + vuint32_t FTYPE:2; + vuint32_t:1; + vuint32_t SCAL:2; + vuint32_t:1; + vuint32_t SAT:1; + vuint32_t ISEL:1; + vuint32_t:1; /* MIXM does not appear to be implemented on the MPC563xM */ + vuint32_t DEC_RATE:4; + vuint32_t:1; /* SDIE not supported in MPC563xM */ + vuint32_t DSEL:1; + vuint32_t IBIE:1; + vuint32_t OBIE:1; + vuint32_t EDME:1; + vuint32_t TORE:1; + vuint32_t TMODE:2; /* the LSB of TMODE is always 0 on the MPC563xM */ + } B; + } MCR; /* Configuration Register DECFILTER_MCR @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t BSY:1; + vuint32_t:1; + vuint32_t DEC_COUNTER:4; + vuint32_t IDFC:1; + vuint32_t ODFC:1; + vuint32_t SDFC:1; /* SDFC not supported in MPC563xM */ + vuint32_t IBIC:1; + vuint32_t OBIC:1; + vuint32_t SVRC:1; /* SVRC not supported in MPC563xM */ + vuint32_t DIVRC:1; + vuint32_t OVFC:1; + vuint32_t OVRC:1; + vuint32_t IVRC:1; + vuint32_t:6; + vuint32_t IDF:1; + vuint32_t ODF:1; + vuint32_t SDF:1; /* SDF not supported in MPC563xM */ + vuint32_t IBIF:1; + vuint32_t OBIF:1; + vuint32_t SVR:1; /* SVR not supported in MPC563xM */ + vuint32_t DIVR:1; + vuint32_t OVF:1; + vuint32_t OVR:1; + vuint32_t IVR:1; + } B; + } MSR; /* Status Register DECFILTER_MSR @baseaddress + 0x04 */ + + /* Module Extended Config.Register - not siupported on the MPC563xM DECFILTER_MXCR @baseaddress + 0x08 */ + + uint32_t decfil_reserved1[2]; + + union { + vuint32_t R; + struct { + vuint32_t:4; + vuint32_t INTAG:4; + vuint32_t:6; + vuint32_t PREFILL:1; + vuint32_t FLUSH:1; + vuint32_t INPBUF:16; + } B; + } IB; /* Interface Input Buffer DECFILTER_IB @baseaddress + 0x10 */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t OUTTAG:4; + vuint32_t OUTBUF:16; + } B; + } OB; /* Interface Output Buffer DECFILTER_OB @baseaddress + 0x14 */ + + uint32_t decfil_reserved2[2]; + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t COEF:24; + } B; + } COEF[9]; /* Filter Coefficient Registers DECFILTER_COEFx @baseaddress + 0x20 - 0x40 */ + + uint32_t decfil_reserved3[13]; + + union { + vuint32_t R; + struct { + vuint32_t:8; + vuint32_t TAP:24; + } B; + } TAP[8]; /* Filter TAP Registers DECFILTER_TAPx @baseaddress + 0x78 - 0x94 */ + + uint32_t decfil_reserved4[14]; + + /* 0x0D0 */ + union { + vuint16_t R; + struct { + vuint32_t:16; + vuint32_t SAMP_DATA:16; + } B; + } EDID; /* Filter EDID Registers DECFILTER_EDID @baseaddress + 0xD0 */ + + uint32_t decfil_reserved5[3]; + + /* 0x0E0 */ + uint32_t decfil_reserved6; + /* Filter FINTVAL Registers - Not supported on MPC563xM DECFILTER_FINTVAL @baseaddress + 0xE0 */ + + /* 0x0E4 */ + uint32_t decfil_reserved7; + /* Filter FINTCNT Registers - Not supported on MPC563xM DECFILTER_FINTCNT @baseaddress + 0xE4 */ + + /* 0x0E8 */ + uint32_t decfil_reserved8; + /* Filter CINTVAL Registers - Not supported on MPC563xM DECFILTER_CINTVAL @baseaddress + 0xE8 */ + + /* 0x0EC */ + uint32_t decfil_reserved9; + /* Filter CINTCNT Registers - Not supported on MPC563xM DECFILTER_CINTCNT @baseaddress + 0xEC */ + + }; +/****************************************************************************/ +/* MODULE : Periodic Interval Timer (PIT) */ +/****************************************************************************/ + struct PIT_tag { + + union { + vuint32_t R; + struct { + vuint32_t:29; + vuint32_t MDIS_RTI:1; + vuint32_t MDIS:1; + vuint32_t FRZ:1; + } B; + } PITMCR; /* PIT Module Control Register */ + + uint32_t pit_reserved1[59]; + + struct { + union { + vuint32_t R; /* TSVn */ + } LDVAL; /* Timer Load Value Register */ + + union { + vuint32_t R; /* TVLn */ + } CVAL; /* Current Timer Value Register */ + + union { + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t TIE:1; + vuint32_t TEN:1; + } B; + } TCTRL; /* Timer Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } TFLG; /* Timer Flag Register */ + } RTI; /* RTI Channel */ + + struct { + union { + vuint32_t R; + } LDVAL; /* Timer Load Value Register */ + + union { + vuint32_t R; + } CVAL; /* Current Timer Value Register */ + + union { + vuint32_t R; + struct { + vuint32_t:30; + vuint32_t TIE:1; + vuint32_t TEN:1; + } B; + } TCTRL; /* Timer Control Register */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } TFLG; /* Timer Flag Register */ + } TIMER[4]; /* Timer Channels */ + + }; +/****************************************************************************/ +/* MODULE : System Timer Module (STM) */ +/****************************************************************************/ + struct STM_tag { + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t CPS:8; + vuint32_t:6; + vuint32_t FRZ:1; + vuint32_t TEN:1; + } B; + } CR; /* STM Control Register STM_CR (new in MPC563xM) Offset 0x0000 */ + + union { + vuint32_t R; + } CNT; /* STM Count Register STM_CNT (new in MPC563xM) Offset Offset 0x0004 */ + + uint32_t stm_reserved1[2]; /* Reserved (new in MPC563xM) Offset Offset 0x0008 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR0; /* STM Channel Control Register STM_CCR0 (new in MPC563xM) Offset 0x0010 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR0; /* STM Channel Interrupt Register STM_CIR0 (new in MPC563xM) Offset 0x0014 */ + + union { + vuint32_t R; + } CMP0; /* STM Channel Compare Register STM_CMP0 (new in MPC563xM) Offset Offset 0x0018 */ + + uint32_t stm_reserved2; /* Reserved (new in MPC563xM) Offset Offset 0x001C */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR1; /* STM Channel Control Register STM_CCR1 (new in MPC563xM) Offset 0x0020 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR1; /* STM Channel Interrupt Register STM_CIR1 (new in MPC563xM) Offset 0x0024 */ + + union { + vuint32_t R; + } CMP1; /* STM Channel Compare Register STM_CMP1 (new in MPC563xM) Offset Offset 0x0028 */ + + uint32_t stm_reserved3; /* Reserved (new in MPC563xM) Offset Offset 0x002C */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR2; /* STM Channel Control Register STM_CCR2 (new in MPC563xM) Offset 0x0030 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR2; /* STM Channel Interrupt Register STM_CIR2 (new in MPC563xM) Offset 0x0034 */ + + union { + vuint32_t R; + } CMP2; /* STM Channel Compare Register STM_CMP2 (new in MPC563xM) Offset Offset 0x0038 */ + + uint32_t stm_reserved4; /* Reserved (new in MPC563xM) Offset Offset 0x003C */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CEN:1; + } B; + } CCR3; /* STM Channel Control Register STM_CCR3 (new in MPC563xM) Offset 0x0040 */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t CIF:1; + } B; + } CIR3; /* STM Channel Interrupt Register STM_CIR3 (new in MPC563xM) Offset 0x0044 */ + + union { + vuint32_t R; + } CMP3; /* STM Channel Compare Register STM_CMP3 (new in MPC563xM) Offset Offset 0x0048 */ + + uint32_t stm_reserved5; /* Reserved (new in MPC563xM) Offset Offset 0x004C */ + }; + +/****************************************************************************/ +/* MODULE : SWT */ +/****************************************************************************/ + + struct SWT_tag { + union { + vuint32_t R; + struct { + vuint32_t MAP0:1; + vuint32_t MAP1:1; + vuint32_t MAP2:1; + vuint32_t MAP3:1; + vuint32_t MAP4:1; + vuint32_t MAP5:1; + vuint32_t MAP6:1; + vuint32_t MAP7:1; + vuint32_t:14; + vuint32_t KEY:1; + vuint32_t RIA:1; + vuint32_t WND:1; + vuint32_t ITR:1; + vuint32_t HLK:1; + vuint32_t SLK:1; + vuint32_t CSL:1; + vuint32_t STP:1; + vuint32_t FRZ:1; + vuint32_t WEN:1; + } B; + } MCR; /*SWT_CR *//* Module Configuration Register */ + + union { + vuint32_t R; + struct { + vuint32_t:31; + vuint32_t TIF:1; + } B; + } IR; /* Interrupt register SWT_IR */ + + union { + vuint32_t R; + struct { + vuint32_t WTO:32; + } B; + } TO; /* Timeout register SWT_TO */ + + union { + vuint32_t R; + struct { + vuint32_t WST:32; + + } B; + } WN; /* Window register SWT_WN */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t WSC:16; + } B; + } SR; /* Service register SWT_SR */ + + union { + vuint32_t R; + struct { + vuint32_t CNT:32; + } B; + } CO; /* Counter output register SWT_CO */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t SK:16; + } B; + } SK; /* Service key register SWT_SK */ + }; +/****************************************************************************/ +/* MODULE : Power Management Controller (PMC) */ +/****************************************************************************/ + struct PMC_tag { + union { + vuint32_t R; + struct { + vuint32_t LVRER:1; /* LVIRR */ + vuint32_t LVREH:1; /* LVIHR */ + vuint32_t LVRE50:1; /* LVI5R */ + vuint32_t LVRE33:1; /* LVI3R */ + vuint32_t LVREC:1; /* LVI1R */ + vuint32_t:3; + vuint32_t LVIER:1; /* LVIRE */ + vuint32_t LVIEH:1; /* LVIHE */ + vuint32_t LVIE50:1; /* LVI5E */ + vuint32_t LVIE33:1; /* LVI3E */ + vuint32_t LVIC:1; /* LVI1E */ + vuint32_t:2; + vuint32_t TLK:1; + vuint32_t:16; + } B; + } MCR; /* Module Configuration register CFGR */ + + union { + vuint32_t R; + struct { + vuint32_t:12; + vuint32_t LVDREGTRIM:4; /* LVI50TRIM */ + vuint32_t VDD33TRIM:4; /* BV33TRIM */ + vuint32_t LVD33TRIM:4; /* LVI33TRIM */ + vuint32_t VDDCTRIM:4; /* V12TRIM */ + vuint32_t LVDCTRIM:4; /* LVI33TRIM */ + } B; + } TRIMR; /* Trimming register */ + + union { + vuint32_t R; + struct { + vuint32_t:5; + vuint32_t LVFVSTBY:1; + vuint32_t BGRDY:1; /* BGS1 */ + vuint32_t BGTS:1; /* BGS2 */ + vuint32_t:5; + vuint32_t LVFCSTBY:1; + vuint32_t:1; + vuint32_t V33DIS:1; /* 3.3V Regulator Disable V33S */ + vuint32_t LVFCR:1; /* Clear LVFR LVIRC */ + vuint32_t LVFCH:1; /* Clear LVFH LVIHC */ + vuint32_t LVFC50:1; /* Clear LVF5 LVI5 */ + vuint32_t LVFC33:1; /* Clear LVF3 LVI3 */ + vuint32_t LVFCC:1; /* Clear LVFC LVI1 */ + vuint32_t:3; + vuint32_t LVFR:1; /* Low Voltage Flag Reset Supply LVIRF */ + vuint32_t LVFH:1; /* Low Voltage Flag VDDEH Supply LVIHF */ + vuint32_t LVF50:1; /* Low Voltage Flag 5V Supply LVI5F */ + vuint32_t LVF33:1; /* Low Voltage Flag 3.3V Supply LVI3F */ + vuint32_t LVFC:1; /* Low Voltage Flag Core (1.2V) LVI1F */ + vuint32_t:3; + + } B; + } SR; /* status register */ + }; +/****************************************************************************/ +/* MODULE : TSENS (Temperature Sensor) */ +/****************************************************************************/ + + struct TSENS_tag { + + union { + vuint32_t R; + struct { + vuint32_t TSCV2:16; + vuint32_t TSCV1:16; + } B; + } TCCR0; /* Temperature Sensor Calibration B @baseaddress + 0x00 */ + + union { + vuint32_t R; + struct { + vuint32_t:16; + vuint32_t TSCV3:16; + } B; + } TCCR1; /* Temperature Sensor Calibration A @baseaddress + 0x04 */ + + uint32_t TSENS_reserved0008[16382]; /* 0x0008-0xFFFF */ + + }; + +/* Define memories */ +/* Comments need to be moved for different memory sizes */ + +#define SRAM_START 0x40000000 + /*#define SRAM_SIZE 0xC000 48K SRAM */ + /*#define SRAM_SIZE 0x10000 64K SRAM */ +#define SRAM_SIZE 0x17800 /* 94K SRAM */ + /*#define SRAM_END 0x4000BFFF 48K SRAM */ + /*#define SRAM_END 0x4000FFFF 64K SRAM */ +#define SRAM_END 0x400177FF /* 94K SRAM */ + +#define FLASH_START 0x0 + /*#define FLASH_SIZE 0x100000 1M Flash */ +#define FLASH_SIZE 0x180000 /* 1.5M Flash */ + /*#define FLASH_END 0xFFFFF 1M Flash */ +#define FLASH_END 0x17FFFF /* 1.5M Flash */ + +/* Shadow Flash start and end address */ +#define FLASH_SHADOW_START 0x00FFC000 +#define FLASH_SHADOW_SIZE 0x4000 +#define FLASH_SHADOW_END 0x00FFFFFF + +/* Define instances of modules */ +#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000) +#define EBI (*( volatile struct EBI_tag *) 0xC3F84000) +#define CFLASH0 (*( volatile struct FLASH_tag *) 0xC3F88000) +#define CFLASH1 (*( volatile struct FLASH_tag *) 0xC3FB0000) +#define CFLASH2 (*( volatile struct FLASH_tag *) 0xC3FB4000) +#define SIU (*( volatile struct SIU_tag *) 0xC3F90000) + +#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000) +#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000) +#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000) +#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) +#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) +#define ETPU_DATA_RAM_END 0xC3FC8BFC +#define CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) +#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000) + +#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000) +#define SWT (*( volatile struct SWT_tag *) 0xFFF38000) +#define STM (*( volatile struct STM_tag *) 0xFFF3C000) +#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000) +#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000) +#define INTC (*( volatile struct INTC_tag *) 0xFFF48000) + +#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000) +#define DECFIL (*( volatile struct DECFIL_tag *) 0xFFF88000) + +#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000) +#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000) + +#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000) +#define ESCI_A_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB0006) +#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000) +#define ESCI_B_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB4006) + +#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000) +#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000) + +#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000) + +#ifdef __MWERKS__ +#pragma pop +#endif /* + */ + +#ifdef __cplusplus +} +#endif /* + */ + +#endif /* ifdef _MPC563M_H */ +/********************************************************************* + * + * Copyright: + * Freescale Semiconductor, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Freescale + * Semiconductor, Inc. This software is provided on an "AS IS" + * basis and without warranty. + * + * To the maximum extent permitted by applicable law, Freescale + * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, + * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A + * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH + * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) + * AND ANY ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER + * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, + * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER + * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Freescale Semiconductor assumes no responsibility for the + * maintenance and support of this software + * + ********************************************************************/ + diff --git a/os/hal/platforms/SPC563Mxx/platform.dox b/os/hal/platforms/SPC563Mxx/platform.dox new file mode 100644 index 000000000..9b8eec901 --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/platform.dox @@ -0,0 +1,70 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup SPC563 SPC563Mx Drivers + * @details This section describes all the supported drivers on the + * SPC563Mx/MPC563xM platform and the implementation details + * of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup SPC563_HAL SPC563Mx Initialization Support + * @details The SPC563Mx/MPC563xM HAL support is responsible for system + * initialization. + * + * @section spc563_hal_1 Supported HW resources + * - FMPLL. + * - INTC. + * - XBAR. + * - CFLASH0. + * . + * @section spc563_hal_2 SPC563Mx HAL driver implementation features + * - FMPLL startup and stabilization. + * - Clock tree initialization. + * - Clock source selection. + * - Flash wait states initialization based on the selected clock options. + * - SYSTICK initialization based on current clock and kernel required rate. + * - DMA support initialization. + * . + * @ingroup SPC563 + */ + +/** + * @defgroup SPC563_SERIAL SPC563Mx Serial Support + * @details The SPC563Mx/MPC563xM Serial driver uses the ESCI peripherals + * in a buffered, interrupt driven, implementation. + * + * @section spc563_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - ESCIA. + * - ESCIB. + * . + * @section spc563_serial_2 SPC563Mx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each ESCI can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * - Programmable priority levels for each ESCI. + * . + * @ingroup SPC563 + */ diff --git a/os/hal/platforms/SPC563Mxx/platform.mk b/os/hal/platforms/SPC563Mxx/platform.mk new file mode 100644 index 000000000..e9a508857 --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/platform.mk @@ -0,0 +1,6 @@ +# List of all the SPC56x platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC563Mxx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/ESCIv1/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC563Mxx diff --git a/os/hal/platforms/SPC563Mxx/serial_lld.c b/os/hal/platforms/SPC563Mxx/serial_lld.c new file mode 100644 index 000000000..e562b6c2d --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/serial_lld.c @@ -0,0 +1,294 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC56x/serial_lld.c + * @brief SPC563 low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief eSCI-A serial driver identifier. + */ +#if USE_SPC563_ESCIA || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief eSCI-B serial driver identifier. + */ +#if USE_SPC563_ESCIB || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + SD_MODE_NORMAL | SD_MODE_PARITY_NONE +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief eSCI initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration + */ +static void esci_init(SerialDriver *sdp, const SerialConfig *config) { + volatile struct ESCI_tag *escip = sdp->escip; + uint8_t mode = config->sc_mode; + + escip->CR2.R = 0; /* MDIS off. */ + escip->CR1.R = 0; + escip->LCR.R = 0; + escip->CR1.B.SBR = SPC563_SYSCLK / (16 * config->sc_speed); + if (mode & SD_MODE_LOOPBACK) + escip->CR1.B.LOOPS = 1; + switch (mode & SD_MODE_PARITY) { + case SD_MODE_PARITY_ODD: + escip->CR1.B.PT = 1; + case SD_MODE_PARITY_EVEN: + escip->CR1.B.PE = 1; + escip->CR1.B.M = 1; /* Makes it 8 bits data + 1 bit parity. */ + default: + ; + } + escip->LPR.R = 0; + escip->CR1.R |= 0x0000002C; /* RIE, TE, RE to 1. */ + escip->CR2.R |= 0x000F; /* ORIE, NFIE, FEIE, PFIE to 1. */ +} + +/** + * @brief eSCI de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] escip pointer to an eSCI I/O block + */ +static void esci_deinit(volatile struct ESCI_tag *escip) { + + escip->LPR.R = 0; + escip->SR.R = 0xFFFFFFFF; + escip->CR1.R = 0; + escip->CR2.R = 0x8000; /* MDIS on. */ +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] sr eSCI SR register value + */ +static void set_error(SerialDriver *sdp, uint32_t sr) { + flagsmask_t sts = 0; + + if (sr & 0x08000000) + sts |= SD_OVERRUN_ERROR; + if (sr & 0x04000000) + sts |= SD_NOISE_ERROR; + if (sr & 0x02000000) + sts |= SD_FRAMING_ERROR; + if (sr & 0x01000000) + sts |= SD_PARITY_ERROR; +/* if (sr & 0x00000000) + sts |= SD_BREAK_DETECTED;*/ + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +static void serve_interrupt(SerialDriver *sdp) { + volatile struct ESCI_tag *escip = sdp->escip; + + uint32_t sr = escip->SR.R; + escip->SR.R = 0x3FFFFFFF; /* Does not clear TDRE | TC.*/ + if (sr & 0x0F000000) /* OR | NF | FE | PF. */ + set_error(sdp, sr); + if (sr & 0x20000000) { /* RDRF. */ + chSysLockFromIsr(); + sdIncomingDataI(sdp, escip->DR.B.D); + chSysUnlockFromIsr(); + } + if (escip->CR1.B.TIE && (sr & 0x80000000)) { /* TDRE. */ + msg_t b; + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + escip->CR1.B.TIE = 0; + } + else { + ESCI_A.SR.B.TDRE = 1; + escip->DR.R = (uint16_t)b; + } + chSysUnlockFromIsr(); + } +} + +#if USE_SPC563_ESCIA || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + if (ESCI_A.SR.B.TDRE) { + msg_t b = sdRequestDataI(&SD1); + if (b != Q_EMPTY) { + ESCI_A.SR.B.TDRE = 1; + ESCI_A.CR1.B.TIE = 1; + ESCI_A.DR.R = (uint16_t)b; + } + } +} +#endif + +#if USE_SPC563_ESCIB || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + if (ESCI_B.SR.B.TDRE) { + msg_t b = sdRequestDataI(&SD2); + if (b != Q_EMPTY) { + ESCI_B.SR.B.TDRE = 1; + ESCI_B.CR1.B.TIE = 1; + ESCI_B.DR.R = (uint16_t)b; + } + } +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if USE_SPC563_ESCIA || defined(__DOXYGEN__) +/** + * @brief eSCI-A interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(vector146) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if USE_SPC563_ESCIB || defined(__DOXYGEN__) +/** + * @brief eSCI-B interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(vector149) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if USE_SPC563_ESCIA + sdObjectInit(&SD1, NULL, notify1); + SD1.escip = &ESCI_A; + ESCI_A.CR2.R = 0x8000; /* MDIS ON. */ + INTC.PSR[146].R = SPC563_ESCIA_PRIORITY; +#endif + +#if USE_SPC563_ESCIB + sdObjectInit(&SD2, NULL, notify2); + SD2.escip = &ESCI_B; + ESCI_B.CR2.R = 0x8000; /* MDIS ON. */ + INTC.PSR[149].R = SPC563_ESCIB_PRIORITY; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + esci_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) + esci_deinit(sdp->escip); +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/SPC563Mxx/serial_lld.h b/os/hal/platforms/SPC563Mxx/serial_lld.h new file mode 100644 index 000000000..b02b160b1 --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/serial_lld.h @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC56x/serial_lld.h + * @brief SPC563 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define SD_MODE_PARITY_MASK 0x03 /**< @brief Parity field mask. */ +#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ +#define SD_MODE_PARITY_EVEN 0x01 /**< @brief Even parity. */ +#define SD_MODE_PARITY_ODD 0x02 /**< @brief Odd parity. */ + +#define SD_MODE_NORMAL 0x00 /**< @brief Normal operations. */ +#define SD_MODE_LOOPBACK 0x80 /**< @brief Internal loopback. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief eSCI-A driver enable switch. + * @details If set to @p TRUE the support for eSCI-A is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SPC563_ESCIA) || defined(__DOXYGEN__) +#define USE_SPC563_ESCIA TRUE +#endif + +/** + * @brief eSCI-B driver enable switch. + * @details If set to @p TRUE the support for eSCI-B is included. + * @note The default is @p TRUE. + */ +#if !defined(USE_SPC563_ESCIB) || defined(__DOXYGEN__) +#define USE_SPC563_ESCIB TRUE +#endif + +/** + * @brief eSCI-A interrupt priority level setting. + */ +#if !defined(SPC563_ESCIA_PRIORITY) || defined(__DOXYGEN__) +#define SPC563_ESCIA_PRIORITY 8 +#endif + +/** + * @brief eSCI-B interrupt priority level setting. + */ +#if !defined(SPC563_ESCIB_PRIORITY) || defined(__DOXYGEN__) +#define SPC563_ESCIB_PRIORITY 8 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Mode flags. + */ + uint8_t sc_mode; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the volatile eSCI registers block.*/ \ + volatile struct ESCI_tag *escip; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if USE_SPC563_ESCIA && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if USE_SPC563_ESCIB && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC563Mxx/typedefs.h b/os/hal/platforms/SPC563Mxx/typedefs.h new file mode 100644 index 000000000..2214513eb --- /dev/null +++ b/os/hal/platforms/SPC563Mxx/typedefs.h @@ -0,0 +1,25 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file SPC56x/typedefs.h + * @brief Dummy typedefs file. + */ + +#ifndef _TYPEDEFS_H_ +#define _TYPEDEFS_H_ + +#include "chtypes.h" + +#endif /* _TYPEDEFS_H_ */ diff --git a/os/hal/platforms/SPC56x/hal_lld.c b/os/hal/platforms/SPC56x/hal_lld.c deleted file mode 100644 index f5dec4516..000000000 --- a/os/hal/platforms/SPC56x/hal_lld.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file SPC56x/hal_lld.c - * @brief SPC563 HAL subsystem low level driver source. - * - * @addtogroup HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - * - * @notapi - */ -void hal_lld_init(void) { - extern void _vectors(void); - uint32_t n; - - /* Enables the branch prediction, clears and enables the BTB into the - BUCSR special register (1013).*/ - asm volatile ("li %%r3, 0x0201 \t\n" - "mtspr 1013, %%r3": : : "r3"); - - /* FLASH wait states and prefetching setup.*/ - CFLASH0.BIUCR.R = SPC563_FLASH_BIUCR | SPC563_FLASH_WS; - CFLASH0.BIUCR2.R = 0; - CFLASH0.PFCR3.R = 0; - - /* Optimal crossbar settings. The DMA priority is placed above the CPU - priority in order to not starve I/O activities while the CPU is - executing tight loops (FLASH and SRAM slave ports only). - The SRAM is parked on the load/store port, for some unknown reason it - is defaulted on the instructions port and this kills performance.*/ - XBAR.SGPCR3.B.PARK = 4; /* RAM slave on load/store port.*/ - XBAR.MPR0.R = 0x00030201; /* Flash slave port priorities: - eDMA (1): 0 (highest) - Core Instructions (0): 1 - Undocumented (2): 2 - Core Data (4): 3 */ - XBAR.MPR3.R = 0x00030201; /* SRAM slave port priorities: - eDMA (1): 0 (highest) - Core Instructions (0): 1 - Undocumented (2): 2 - Core Data (4): 3 */ - - /* Downcounter timer initialized for system tick use, TB enabled for debug - and measurements.*/ - n = SPC563_SYSCLK / CH_FREQUENCY; - asm volatile ("li %%r3, 0 \t\n" - "mtspr 284, %%r3 \t\n" /* Clear TBL register. */ - "mtspr 285, %%r3 \t\n" /* Clear TBU register. */ - "mtspr 22, %[n] \t\n" /* Init. DEC register. */ - "mtspr 54, %[n] \t\n" /* Init. DECAR register.*/ - "li %%r3, 0x4000 \t\n" /* TBEN bit. */ - "mtspr 1008, %%r3 \t\n" /* HID0 register. */ - "lis %%r3, 0x0440 \t\n" /* DIE ARE bits. */ - "mtspr 340, %%r3" /* TCR register. */ - : : [n] "r" (n) : "r3"); - - /* INTC initialization, software vector mode, 4 bytes vectors, starting - at priority 0.*/ - INTC.MCR.R = 0; - INTC.CPR.R = 0; - INTC.IACKR.R = (uint32_t)_vectors; -} - -/** - * @brief SPC563 clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h and - * @p hal_lld.h - * @note This function must be invoked only after the system reset. - * - * @special - */ -void spc563_clock_init(void) { - - /* PLL activation.*/ - FMPLL.ESYNCR1.B.EMODE = 1; - FMPLL.ESYNCR1.B.CLKCFG &= 1; /* Bypass mode, PLL off.*/ - FMPLL.ESYNCR1.B.CLKCFG |= 2; /* PLL on. */ - FMPLL.ESYNCR1.B.EPREDIV = SPC563_CLK_PREDIV; - FMPLL.ESYNCR1.B.EMFD = SPC563_CLK_MFD; - FMPLL.ESYNCR2.B.ERFD = SPC563_CLK_RFD; - while (!FMPLL.SYNSR.B.LOCK) - ; - FMPLL.ESYNCR1.B.CLKCFG |= 4; /* Clock from the PLL. */ -} - -/** @} */ diff --git a/os/hal/platforms/SPC56x/hal_lld.h b/os/hal/platforms/SPC56x/hal_lld.h deleted file mode 100644 index 8a30113ba..000000000 --- a/os/hal/platforms/SPC56x/hal_lld.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file SPC56x/hal_lld.h - * @brief SPC563 HAL subsystem low level driver header. - * - * @addtogroup HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "mpc563m.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Defines the support for realtime counters in the HAL. - */ -#define HAL_IMPLEMENTS_COUNTERS FALSE - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "SPC563M64" - -#define RFD_DIV2 0 /**< Divide VCO frequency by 2. */ -#define RFD_DIV4 1 /**< Divide VCO frequency by 4. */ -#define RFD_DIV8 2 /**< Divide VCO frequency by 8. */ -#define RFD_DIV16 3 /**< Divide VCO frequency by 16.*/ - -/* The following settings are related to the FLASH controller, performance - and stability depends on them, be careful.*/ -#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/ -#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */ -#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */ -#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */ -#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */ -#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */ -#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */ -#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */ -#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */ -#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */ -#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */ -#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */ -#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */ -#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */ -#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */ -#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */ -#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */ -#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */ -#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */ -#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */ -#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */ -#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */ -#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */ -#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */ -#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */ -#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */ -#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */ -#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */ -#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */ -#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */ -#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */ -#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */ -#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */ -#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */ -#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */ -#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */ -#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */ -#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Clock bypass. - * @note If set to @p TRUE then the PLL is not started and initialized, the - * external clock is used as-is and the other clock-related settings - * are ignored. - */ -#if !defined(SPC563_CLK_BYPASS) || defined(__DOXYGEN__) -#define SPC563_CLK_BYPASS FALSE -#endif - -/** - * @brief Disables the overclock checks. - */ -#if !defined(SPC563_ALLOW_OVERCLOCK) || defined(__DOXYGEN__) -#define SPC563_ALLOW_OVERCLOCK FALSE -#endif - -/** - * @brief External clock pre-divider. - * @note Must be in range 0...14. - * @note The effective divider factor is this value plus one. - */ -#if !defined(SPC563_CLK_PREDIV) || defined(__DOXYGEN__) -#define SPC563_CLK_PREDIV 1 -#endif - -/** - * @brief Multiplication factor divider. - * @note Must be in range 32...96. - */ -#if !defined(SPC563_CLK_MFD) || defined(__DOXYGEN__) -#define SPC563_CLK_MFD 80 -#endif - -/** - * @brief Reduced frequency divider. - */ -#if !defined(SPC563_CLK_RFD) || defined(__DOXYGEN__) -#define SPC563_CLK_RFD RFD_DIV4 -#endif - -/** - * @brief Flash buffer and prefetching settings. - * @note Please refer to the SPC563M64 reference manual about the meaning - * of the following bits, if in doubt DO NOT MODIFY IT. - * @note Do not specify the APC, WWSC, RWSC bits in this value because - * those are calculated from the system clock and ORed with this - * value. - */ -#if !defined(SPC563_FLASH_BIUCR) || defined(__DOXYGEN__) -#define SPC563_FLASH_BIUCR (BIUCR_BANK1_TOO | \ - BIUCR_MASTER4_PREFETCH | \ - BIUCR_MASTER0_PREFETCH | \ - BIUCR_DPFEN | \ - BIUCR_IPFEN | \ - BIUCR_PFLIM_ON_MISS | \ - BIUCR_BFEN) -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (SPC563_CLK_PREDIV < 0) || (SPC563_CLK_PREDIV > 14) -#error "invalid SPC563_CLK_PREDIV value specified" -#endif - -#if (SPC563_CLK_MFD < 32) || (SPC563_CLK_MFD > 96) -#error "invalid SPC563_CLK_MFD value specified" -#endif - -#if (SPC563_CLK_RFD != RFD_DIV2) && (SPC563_CLK_RFD != RFD_DIV4) && \ - (SPC563_CLK_RFD != RFD_DIV8) && (SPC563_CLK_RFD != RFD_DIV16) -#error "invalid SPC563_CLK_RFD value specified" -#endif - -/** - * @brief PLL output clock. - */ -#define SPC563_PLLCLK ((EXTCLK / (SPC563_CLK_PREDIV + 1)) * SPC563_CLK_MFD) - -#if (SPC563_PLLCLK < 256000000) || (SPC563_PLLCLK > 512000000) -#error "VCO frequency out of the acceptable range (256...512)" -#endif - -/** - * @brief PLL output clock. - */ -#if !SPC563_CLK_BYPASS || defined(__DOXYGEN__) -#define SPC563_SYSCLK (SPC563_PLLCLK / (1 << (SPC563_CLK_RFD + 1))) -#else -#define SPC563_SYSCLK EXTCLK -#endif - -#if (SPC563_SYSCLK > 80000000) && !SPC563_ALLOW_OVERCLOCK -#error "System clock above maximum rated frequency (80MHz)" -#endif - -/** - * @brief Flash wait states are a function of the system clock. - */ -#if (SPC563_SYSCLK <= 30000000) || defined(__DOXYGEN__) -#define SPC563_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_1) -#elif SPC563_SYSCLK <= 60000000 -#define SPC563_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_1) -#else -#define SPC563_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_1) -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void spc563_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/SPC56x/mpc563m.h b/os/hal/platforms/SPC56x/mpc563m.h deleted file mode 100644 index 8ee2b5787..000000000 --- a/os/hal/platforms/SPC56x/mpc563m.h +++ /dev/null @@ -1,4123 +0,0 @@ -/**************************************************************************/ - -/* FILE NAME: mpc563xm.h COPYRIGHT (c) Freescale 2008,2009 */ -/* VERSION: 2.0 All Rights Reserved */ -/* */ -/* DESCRIPTION: */ -/* This file contain all of the register and bit field definitions for */ -/* MPC563xM. This version supports revision 1.0 and later. */ -/*========================================================================*/ -/* UPDATE HISTORY */ -/* REV AUTHOR DATE DESCRIPTION OF CHANGE */ -/* --- ----------- --------- --------------------- */ -/* 1.0 G. Emerson 31/OCT/07 Initial version. */ -/* 1.1 G. Emerson 20/DEC/07 Added SYSDIV HLT HLTACK */ -/* Added ESYNCR1 ESYNCR2 SYNFMMR */ -/* 1.2 G. Emerson 31/JAN/08 Change eMIOS channels so there are 24. */ -/* 8 channels in the middle of the range */ -/* do not exist */ -/* 1.3 G. Emerson 30/JUL/08 FLEXCAN - Supports FIFO and Buffer. */ -/* RXIMR added */ -/* FMPLL - Added FMPLL.SYNFMMR.B.BSY */ -/* SIU - Added SIU.ISEL0-3 */ -/* EMIOS - Added EMIOS.CH[x].ALTCADR.R */ -/* MCM - Replaced ECSM with MCM */ -/* removing SWT registers as defined at */ -/* seperate memory location. PFLASH */ -/* registers pre-fixed with P*. Added PCT,*/ -/* PLREV, PLAMC, PLASC, IOPMC, MRSR, MWCR.*/ -/* PBRIDGE - Removed as no PBRIDGE */ -/* registers. */ -/* INTC - Updated number of PSR from */ -/* 358 to 360. */ -/* mpc5500_spr.h - Added RI to MSR and NMI*/ -/* to MSCR. */ -/* 1.4 G. Emerson 30/SEP/08 Add SIU.MIDR2 */ -/* Changes to SIU.MIDR as per RM. */ -/* 1.5 May 2009 Changes to match documentation, removed*/ -/* Not released */ -/* 1.6 K. Odenthal 03/June/09 Update for 1.5M version of the MPC563xM*/ -/* & R. Dees */ -/* INTC - All Processor 0 regs matched to previous */ -/* version */ -/* INTC - BCR renamed to MCR to match previous */ -/* version */ -/* INTC - VTES_PRC1 and HVEN_PRC1 added to MCR */ -/* INTC - CPR_PRC1, IACKR_PRC1 and EOIR_PRC1 */ -/* registers added */ -/* INTC - 512 PSR registers instead of 364 */ -/* ECSM - (Internal - mcm -> ecsm in the source files*/ -/* for generating the header file */ -/* ECSM - All bits and regs got an additional "p" in */ -/* the name in the user manual for "Platform" */ -/* -> deleted to match */ -/* ECSM - SWTCR, SWTSR and SWTIR don't exist in */ -/* MPC563xM -> deleted */ -/* ECSM - PROTECTION in the URM is one bitfield, */ -/* in mop5534 this are four: PROT1-4 -> */ -/* changed to match */ -/* EMCM - removed undocumented registers */ -/* ECSM - RAM ECC Syndrome is new in MPC563xM -> added */ -/* XBAR - removed AMPR and ASGPCR registers */ -/* XBAR - removed HPE bits for nonexistant masters */ -/* EBI - added: D16_31, AD_MUX and SETA bits */ -/* EBI - Added reserved register at address 0x4. */ -/* EBI - Corrected number of chip selects in for both*/ -/* the EBI_CS and the CAL_EBI_CS */ -/* SIU - corrected number of GPDO registers and */ -/* allowed for maximum PCR registers. */ -/* SWT - add KEY bit to CR, correct WND (from WNO) */ -/* SWT - add SK register */ -/* PMC - moved bits from CFGR to Status Register (SR)*/ -/* PMC - Added SR */ -/* DECFIL - Added new bits DSEL, IBIE, OBIE, EDME, */ -/* TORE, & TRFE to MCR. Added IBIC, OBIC, */ -/* DIVRC, IBIF, OBIF, DIVR to MSR. */ -/* changed OUTTEG to OUTTAG in OB */ -/* Change COEF to TAG in TAG register */ -/* EQADC - removed REDLCCR - not supported */ -/* FLASH - Aligned register and bit names with legacy*/ -/* 1.7 K. Odenthal 10/November/09 */ -/* SIU - changed PCR[n].PA from 3 bit to 4 bit */ -/* eTPU - changed WDTR_A.WDM from 1 bit to 2 bits */ -/* DECFIL - changed COEF.R and TAP.R from 16 bit to */ -/* 32 bit */ -/* 2.0 K. Odenthal 12/February/2010 */ -/* TSENS - Temperature Sensor Module added to */ -/* header file */ -/* ANSI C Compliance - Register structures have a */ -/* Bitfield Tag ('B') tag only if there is */ -/* at least one Bitfiels defined. Empty */ -/* tags like 'vuint32_t:32;' are not */ -/* allowed. */ -/* DECFIL - removed MXCR register. This register is */ -/* not supported on this part */ -/* SIU - SWT_SEL bit added in SIU DIRER register */ -/* EDMA - removed HRSL, HRSH and GPOR registers. */ -/* Those registers are not supported in */ -/* that part. */ -/* ESCI - removed LDBG and DSF bits from LCR */ -/* registers. Those bits are not supported */ -/* in that part. */ -/* Those registers are not supported in */ -/* that part. */ -/**************************************************************************/ -/*>>>>NOTE! this file is auto-generated please do not edit it!<<<<*/ - -#ifndef _MPC563M_H_ -#define _MPC563M_H_ - -#include "typedefs.h" - -#ifdef __cplusplus -extern "C" { - -#endif /* - */ - -#ifdef __MWERKS__ -#pragma push -#pragma ANSI_strict off -#endif /* - */ - -/****************************************************************************/ -/* MODULE : FMPLL */ -/****************************************************************************/ - struct FMPLL_tag { - union { - vuint32_t R; - struct { - vuint32_t:1; - vuint32_t PREDIV:3; - vuint32_t MFD:5; - vuint32_t:1; - vuint32_t RFD:3; - vuint32_t LOCEN:1; - vuint32_t LOLRE:1; - vuint32_t LOCRE:1; - vuint32_t:1; /* Reserved in MPC563xM - - Deleted for legacy header version [mpc5534.h]: - - */ - vuint32_t LOLIRQ:1; - vuint32_t LOCIRQ:1; - vuint32_t:13; /* Reserved in MPC563xM - - Deleted for legacy header version [mpc5534.h]: - - - - - - */ - } B; - } SYNCR; - union { - vuint32_t R; - struct { - vuint32_t:22; - vuint32_t LOLF:1; - vuint32_t LOC:1; - vuint32_t MODE:1; - vuint32_t PLLSEL:1; - vuint32_t PLLREF:1; - vuint32_t LOCKS:1; - vuint32_t LOCK:1; - vuint32_t LOCF:1; - vuint32_t:2; /* Reserved in MPC563xM - - Deleted for legacy header version [mpc5534.h]: - - - - */ - } B; - } SYNSR; - union { - vuint32_t R; - struct { - vuint32_t EMODE:1; - vuint32_t CLKCFG:3; - vuint32_t:8; - vuint32_t EPREDIV:4; - vuint32_t:9; - vuint32_t EMFD:7; - } B; - } ESYNCR1; /* Enhanced Synthesizer Control Register 1 (ESYNCR1) (new in MPC563xM) Offset 0x0008 */ - union { - vuint32_t R; - struct { - vuint32_t:8; - vuint32_t LOCEN:1; - vuint32_t LOLRE:1; - vuint32_t LOCRE:1; - vuint32_t LOLIRQ:1; - vuint32_t LOCIRQ:1; - vuint32_t:17; - vuint32_t ERFD:2; - } B; - } ESYNCR2; /* Enhanced Synthesizer Control Register 2 (ESYNCR2) (new in MPC563xM) Offset 0x000C */ - int32_t FMPLL_reserved0[2]; - union { - vuint32_t R; - struct { - vuint32_t BSY:1; - vuint32_t MODEN:1; - vuint32_t MODSEL:1; - vuint32_t MODPERIOD:13; - vuint32_t:1; - vuint32_t INCSTEP:15; - } B; - } SYNFMMR; /* Synthesizer FM Modulation Register (SYNFMMR) (new in MPC563xM) Offset 0x0018 */ - }; -/****************************************************************************/ -/* MODULE : EBI */ -/****************************************************************************/ - struct CS_tag { - union { - vuint32_t R; - struct { - vuint32_t BA:17; /* */ - vuint32_t:3; /* */ - vuint32_t PS:1; /* */ - vuint32_t:3; /* */ - vuint32_t AD_MUX:1; /* new in MPC563xM */ - vuint32_t BL:1; /* */ - vuint32_t WEBS:1; /* */ - vuint32_t TBDIP:1; /* */ - vuint32_t:1; /* */ - vuint32_t SETA:1; /* new in MPC563xM */ - vuint32_t BI:1; /* */ - vuint32_t V:1; /* */ - } B; - } BR; /* EBI_BR */ - union { - vuint32_t R; - struct { - vuint32_t AM:17; /* */ - vuint32_t:7; /* */ - vuint32_t SCY:4; /* */ - vuint32_t:1; /* */ - vuint32_t BSCY:2; /* */ - vuint32_t:1; /* */ - } B; - } OR; /* EBI_OR */ - }; - struct CAL_CS_tag { - union { - vuint32_t R; - struct { - vuint32_t BA:17; /* */ - vuint32_t:3; /* */ - vuint32_t PS:1; /* */ - vuint32_t:3; /* */ - vuint32_t AD_MUX:1; /* new in MPC563xM */ - vuint32_t BL:1; /* */ - vuint32_t WEBS:1; /* */ - vuint32_t TBDIP:1; /* */ - vuint32_t:1; /* */ - vuint32_t SETA:1; /* new in MPC563xM */ - vuint32_t BI:1; /* */ - vuint32_t V:1; /* */ - } B; - } BR; /* EBI_CAL_BR */ - - union { - vuint32_t R; - struct { - vuint32_t AM:17; /* */ - vuint32_t:7; /* */ - vuint32_t SCY:4; /* */ - vuint32_t:1; /* */ - vuint32_t BSCY:2; /* */ - vuint32_t:1; /* */ - } B; - } OR; /* EBI_CAL_OR */ - - }; - - struct EBI_tag { - union { - vuint32_t R; - struct { - vuint32_t:5; /* */ - vuint32_t SIZEEN:1; /* SIZEN */ - vuint32_t SIZE:2; /* */ - vuint32_t:8; /* */ - vuint32_t ACGE:1; /* */ - vuint32_t EXTM:1; /* */ - vuint32_t EARB:1; /* */ - vuint32_t EARP:2; /* */ - vuint32_t:4; /* */ - vuint32_t MDIS:1; /* */ - vuint32_t:3; /* */ - vuint32_t D16_31:1; /* new in MPC563xM */ - vuint32_t AD_MUX:1; /* new in MPC563xM */ - vuint32_t DBM:1; /* */ - } B; - } MCR; /* EBI Module Configuration Register (MCR) EBI_MCR @baseaddress + 0x00 */ - - uint32_t EBI_reserved1[1]; - - union { - vuint32_t R; - struct { - vuint32_t:30; /* */ - vuint32_t TEAF:1; /* */ - vuint32_t BMTF:1; /* */ - } B; - } TESR; /* EBI Transfer Error Status Register (TESR) EBI_TESR @baseaddress + 0x08 */ - - union { - vuint32_t R; - struct { - vuint32_t:16; /* */ - vuint32_t BMT:8; /* */ - vuint32_t BME:1; /* */ - vuint32_t:7; /* */ - } B; - } BMCR; /* EBI_BMCR @baseaddress + 0x0C */ - - struct CS_tag CS[4]; - - uint32_t EBI_reserved2[4]; - - /* Calibration registers */ - struct CAL_CS_tag CAL_CS[4]; - - }; /* end of EBI_tag */ -/****************************************************************************/ -/* MODULE : FLASH */ -/****************************************************************************/ -/* 3 flash modules implemented. */ -/* HBL and HBS not used in Bank 0 / Array 0 */ -/* LML, SLL, LMS, PFCR1, PFAPR, PFCR2, and PFCR3 not used in */ -/* Bank 1 / Array 1 or Bank 1 / Array 3 */ -/****************************************************************************/ - struct FLASH_tag { - union { /* Module Configuration Register (MCR)@baseaddress + 0x00 */ - vuint32_t R; - struct { - vuint32_t EDC:1; /* ECC Data Correction (Read/Clear) */ - vuint32_t:4; /* Reserved */ - vuint32_t SIZE:3; /* Array Size (Read Only) */ - vuint32_t:1; /* Reserved */ - vuint32_t LAS:3; /* Low Address Space (Read Only) */ - vuint32_t:3; /* Reserved */ - vuint32_t MAS:1; /* Mid Address Space (Read Only) */ - vuint32_t EER:1; /* ECC Event Error (Read/Clear) *//* BBEPE and EPE */ - vuint32_t RWE:1; /* Read While Write Event Error (Read/Clear) */ - vuint32_t:2; /* Reserved */ - vuint32_t PEAS:1; /* Program/Erase Access Space (Read Only) */ - vuint32_t DONE:1; /* Status (Read Only) */ - vuint32_t PEG:1; /* Program/Erase Good (Read Only) */ - vuint32_t:4; /* Reserved *//* RSD PEG STOP RSVD */ - vuint32_t PGM:1; /* Program (Read/Write) */ - vuint32_t PSUS:1; /* Program Suspend (Read/Write) */ - vuint32_t ERS:1; /* Erase (Read/Write) */ - vuint32_t ESUS:1; /* Erase Suspend (Read/Write) */ - vuint32_t EHV:1; /* Enable High Voltage (Read/Write) */ - } B; - } MCR; - - union { /* Low/Mid-Address Space Block Locking Register (LML)@baseaddress + 0x04 */ - vuint32_t R; - struct { - vuint32_t LME:1; /* Low/Mid address space block enable (Read Only) */ - vuint32_t:10; /* Reserved */ - vuint32_t SLOCK:1; /*SLK *//* Shadow address space block lock (Read/Write) */ - vuint32_t:2; /* Reserved */ - vuint32_t MLOCK:2; /*MLK *//* Mid address space block lock (Read/Write) */ - vuint32_t:8; /* Reserved */ - vuint32_t LLOCK:8; /*LLK *//* Low address space block lock (Read/Write) */ - } B; - } LMLR; /*LML */ - - union { /* High-Address Space Block Locking Register (HBL) - @baseaddress + 0x08 */ - vuint32_t R; - struct { - vuint32_t HBE:1; /* High address space Block Enable (Read Only) */ - vuint32_t:27; /* Reserved */ - vuint32_t HBLOCK:4; /* High address space block lock (Read/Write) */ - } B; - } HLR; /*HBL */ - - union { /* Secondary Low/Mid-Address Space Block Locking Register (SLL)@baseaddress + 0x0C */ - vuint32_t R; - struct { - vuint32_t SLE:1; /* Secondary low/mid address space block enable (Read Only) */ - vuint32_t:10; /* Reserved */ - vuint32_t SSLOCK:1; /*SSLK *//* Secondary shadow address space block lock (Read/Write) */ - vuint32_t:2; /* Reserved */ - vuint32_t SMLOCK:2; /*SMK *//* Secondary mid address space block lock (Read/Write) */ - vuint32_t:8; /* Reserved */ - vuint32_t SLLOCK:8; /*SLK *//* Secondary low address space block lock (Read/Write) */ - } B; - } SLMLR; /*SLL */ - - union { /* Low/Mid-Address Space Block Select Register (LMS)@baseaddress + 0x10 */ - vuint32_t R; - struct { - vuint32_t:14; /* Reserved */ - vuint32_t MSEL:2; /*MSL *//* Mid address space block select (Read/Write) */ - vuint32_t:8; /* Reserved */ - vuint32_t LSEL:8; /*LSL *//* Low address space block select (Read/Write) */ - } B; - } LMSR; /*LMS */ - - union { /* High-Address Space Block Select Register (HBS) - not used@baseaddress + 0x14 */ - vuint32_t R; - struct { - vuint32_t:28; /* Reserved */ - vuint32_t HBSEL:4; /*HSL *//* High address space block select (Read/Write) */ - } B; - } HSR; /*HBS */ - - union { /* Address Register (ADR)@baseaddress + 0x18 */ - vuint32_t R; - struct { - vuint32_t SAD:1; /* Shadow address (Read Only) */ - vuint32_t:10; /* Reserved */ - vuint32_t ADDR:18; /*AD *//* Address 20-3 (Read Only) */ - vuint32_t:3; /* Reserved */ - } B; - } AR; /*ADR */ - - union { /* @baseaddress + 0x1C */ - vuint32_t R; - struct { - vuint32_t:7; /* Reserved */ - vuint32_t GCE:1; /* Global Configuration Enable (Read/Write) */ - vuint32_t:4; /* Reserved */ - vuint32_t M3PFE:1; /* Master 3 Prefetch Enable (Read/Write) */ - vuint32_t M2PFE:1; /* Master 2 Prefetch Enable (Read/Write) */ - vuint32_t M1PFE:1; /* Master 1 Prefetch Enable (Read/Write) */ - vuint32_t M0PFE:1; /* Master 0 Prefetch Enable (Read/Write) */ - vuint32_t APC:3; /* Address Pipelining Control (Read/Write) */ - vuint32_t WWSC:2; /* Write Wait State Control (Read/Write) */ - vuint32_t RWSC:3; /* Read Wait State Control (Read/Write) */ - vuint32_t:1; /* Reserved */ - vuint32_t DPFEN:1; /*DPFE *//* Data Prefetch Enable (Read/Write) */ - vuint32_t:1; /* Reserved */ - vuint32_t IPFEN:1; /*IPFE *//* Instruction Prefetch Enable (Read/Write) */ - vuint32_t:1; /* Reserved */ - vuint32_t PFLIM:2; /* Prefetch Limit (Read/Write) */ - vuint32_t BFEN:1; /*BFE *//* Buffer Enable (Read/Write) */ - } B; - } BIUCR; /*PFCR1 */ - - union { /* @baseaddress + 0x20 */ - vuint32_t R; - struct { - vuint32_t:24; /* Reserved */ - vuint32_t M3AP:2; /* Master 3 Access Protection (Read/Write) */ - vuint32_t M2AP:2; /* Master 2 Access Protection (Read/Write) */ - vuint32_t M1AP:2; /* Master 1 Access Protection (Read/Write) */ - vuint32_t M0AP:2; /* Master 0 Access Protection (Read/Write) */ - } B; - } BIUAPR; /*PFAPR */ - - union { /* @baseaddress + 0x24 */ - vuint32_t R; - struct { - vuint32_t LBCFG:2; /* Line Buffer Configuration (Read/Write) */ - vuint32_t:30; /* Reserved */ - } B; - } BIUCR2; - - union { /* @baseaddress + 0x28 */ - vuint32_t R; - struct { - vuint32_t:25; /* Reserved */ - vuint32_t B1_DPFE:1; /* Bank1 Data Prefetch Enable (Read/Write) */ - vuint32_t:1; /* Reserved */ - vuint32_t B1_IPFE:1; /* Bank1 Instruction Prefetch Enable (Read/Write) */ - vuint32_t:1; /* Reserved */ - vuint32_t B1_PFLIM:2; /* Bank1 Prefetch Limit (Read/Write) */ - vuint32_t B1_BFE:1; /* Bank1 Buffer Enable (Read/Write) */ - } B; - } PFCR3; - - int32_t FLASH_reserverd_89[4]; - - union { /* User Test 0 (UT0) register@baseaddress + 0x3c */ - vuint32_t R; - struct { - vuint32_t UTE:1; /* User test enable (Read/Clear) */ - vuint32_t SBCE:1; /* Single bit correction enable (Read/Clear) */ - vuint32_t:6; /* Reserved */ - vuint32_t DSI:8; /* Data syndrome input (Read/Write) */ - vuint32_t:9; /* Reserved */ - vuint32_t:1; /* Reserved (Read/Write) */ - vuint32_t MRE:1; /* Margin Read Enable (Read/Write) */ - vuint32_t MRV:1; /* Margin Read Value (Read/Write) */ - vuint32_t EIE:1; /* ECC data Input Enable (Read/Write) */ - vuint32_t AIS:1; /* Array Integrity Sequence (Read/Write) */ - vuint32_t AIE:1; /* Array Integrity Enable (Read/Write) */ - vuint32_t AID:1; /* Array Integrity Done (Read Only) */ - } B; - } UT0; - - union { /* User Test 1 (UT1) register@baseaddress + 0x40 */ - vuint32_t R; - struct { - vuint32_t DAI:32; /* Data Array Input (Read/Write) */ - } B; - } UT1; - - union { /* User Test 2 (UT2) register@baseaddress + 0x44 */ - vuint32_t R; - struct { - vuint32_t DAI:32; /* Data Array Input (Read/Write) */ - } B; - } UT2; - - union { /* User Multiple Input Signature Register 0-5 (UMISR[5])@baseaddress + 0x48 */ - vuint32_t R; - struct { - vuint32_t MS:32; /* Multiple input Signature (Read/Write) */ - } B; - } UMISR[5]; - - }; /* end of FLASH_tag */ -/****************************************************************************/ -/* MODULE : SIU */ -/****************************************************************************/ - struct SIU_tag { - union { - vuint32_t R; - struct { - vuint32_t S_F:1; /* Identifies the Manufacturer S/F */ - vuint32_t FLASH_SIZE_1:4; /* Define major Flash memory size (see Table 15-4 for details) Flash Size 1 */ - vuint32_t FLASH_SIZE_2:4; /* Define Flash memory size, small granularity (see Table 15-5 for details) Flash Size 1 */ - vuint32_t TEMP_RANGE:2; /* Define maximum operating range Temp Range */ - vuint32_t:1; /* Reserved for future enhancements */ - vuint32_t MAX_FREQ:2; /* Define maximum device speed Max Freq */ - vuint32_t:1; /* Reserved for future enhancements */ - vuint32_t SUPPLY:1; /* Defines if the part is 5V or 3V Supply */ - vuint32_t PART_NUMBER:8; /* Contain the ASCII representation of the character that indicates the product Part Number */ - vuint32_t TBD:1; /* 1-bit field defined by SoC to describe optional feature, e.g., additional SPI */ - vuint32_t:2; /* Reserved for future enhancements */ - vuint32_t EE:1; /* Indicates if Data Flash is present */ - vuint32_t:3; /* Reserved for future enhancements */ - vuint32_t FR:1; /* Indicates if Data FlexRay is present */ - } B; - } MIDR2; /* MCU ID Register 2 SIU_MIDR2 @baseaddress + 0x4 */ - - union { - vuint32_t R; - struct { - vuint32_t PARTNUM:16; /* Device part number: 0x5633 */ - vuint32_t CSP:1; /* CSP configuration (new in MPC563xM) */ - vuint32_t PKG:5; /* Indicate the package the die is mounted in. (new in MPC563xM) */ - vuint32_t:2; /* Reserved */ - vuint32_t MASKNUM:8; /* MCU major mask number; updated for each complete resynthesis. MCU minor mask number; updated for each mask revision */ - } B; - } MIDR; /* MCU ID Register (MIDR) SIU_MIDR @baseaddress + 0x8 */ - - union { - vuint32_t R; - } TST; /* SIU Test Register (SIU_TST) SIU_TST @baseaddress + 0xC */ - - union { - vuint32_t R; - struct { - vuint32_t PORS:1; /* Power-On Reset Status */ - vuint32_t ERS:1; /* External Reset Status */ - vuint32_t LLRS:1; /* Loss of Lock Reset Status */ - vuint32_t LCRS:1; /* Loss of Clock Reset Status */ - vuint32_t WDRS:1; /* Watchdog Timer/Debug Reset Status */ - vuint32_t CRS:1; /* Checkstop Reset Status */ - vuint32_t SWTRS:1; /* Software Watchdog Timer Reset Status (new in MPC563xM) */ - vuint32_t:7; /* */ - vuint32_t SSRS:1; /* Software System Reset Status */ - vuint32_t SERF:1; /* Software External Reset Flag */ - vuint32_t WKPCFG:1; /* Weak Pull Configuration Pin Status */ - vuint32_t:11; /* */ - vuint32_t ABR:1; /* Auto Baud Rate (new in MPC563xM) */ - vuint32_t BOOTCFG:2; /* Reset Configuration Pin Status */ - vuint32_t RGF:1; /* RESET Glitch Flag */ - } B; - } RSR; /* Reset Status Register (SIU_RSR) SIU_RSR @baseaddress + 0x10 */ - - union { - vuint32_t R; - struct { - vuint32_t SSR:1; /* Software System Reset */ - vuint32_t SER:1; /* Software External Reset */ - vuint32_t:14; /* */ - vuint32_t CRE:1; /* Checkstop Reset Enable */ - vuint32_t:15; /* */ - } B; - } SRCR; /* System Reset Control Register (SRCR) SIU_SRCR @baseaddress + 0x14 */ - - union { - vuint32_t R; - struct { - vuint32_t NMI:1; /* Non-Maskable Interrupt Flag (new in MPC563xM) */ - vuint32_t:7; /* */ - vuint32_t SWT:1; /* Software Watch Dog Timer Interrupt Flag, from platform (new in MPC563xM) */ - vuint32_t:7; /* */ - vuint32_t EIF15:1; /* External Interrupt Request Flag x */ - vuint32_t EIF14:1; /* External Interrupt Request Flag x */ - vuint32_t EIF13:1; /* External Interrupt Request Flag x */ - vuint32_t EIF12:1; /* External Interrupt Request Flag x */ - vuint32_t EIF11:1; /* External Interrupt Request Flag x */ - vuint32_t EIF10:1; /* External Interrupt Request Flag x */ - vuint32_t EIF9:1; /* External Interrupt Request Flag x */ - vuint32_t EIF8:1; /* External Interrupt Request Flag x */ - vuint32_t:3; /* (reserved in MPC563xM) */ - vuint32_t EIF4:1; /* External Interrupt Request Flag x */ - vuint32_t EIF3:1; /* External Interrupt Request Flag x */ - vuint32_t:2; /* (reserved in MPC563xM) */ - vuint32_t EIF0:1; /* External Interrupt Request Flag x */ - } B; - } EISR; /* SIU External Interrupt Status Register (EISR) SIU_EISR @baseaddress + 0x18 */ - - union { - vuint32_t R; - struct { - vuint32_t NMI_SEL:1; /* NMI Interrupt Platform Input Selection (new in MPC563xM) */ - vuint32_t:7; /* */ - vuint32_t SWT_SEL:1; - vuint32_t:7; - vuint32_t EIRE15:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE14:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE13:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE12:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE11:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE10:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE9:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE8:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE7:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE6:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE5:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE4:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE3:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE2:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE1:1; /* External DMA/Interrupt Request Enable x */ - vuint32_t EIRE0:1; /* External DMA/Interrupt Request Enable x */ - } B; - } DIRER; /* DMA/Interrupt Request Enable Register (DIRER) SIU_DIRER @baseaddress + 0x1C */ - - union { - vuint32_t R; - struct { - vuint32_t:28; /* */ - vuint32_t DIRS3:1; /* DMA/Interrupt Request Select x */ - vuint32_t:2; /* reserved in MPC563xM */ - vuint32_t DIRS0:1; /* DMA/Interrupt Request Select x */ - } B; - } DIRSR; /* DMA/Interrupt Request Select Register (DIRSR) SIU_DIRSR @baseaddress + 0x20 */ - - union { - vuint32_t R; - struct { - vuint32_t:16; /* */ - vuint32_t OVF15:1; /* Overrun Flag x */ - vuint32_t OVF14:1; /* Overrun Flag x */ - vuint32_t OVF13:1; /* Overrun Flag x */ - vuint32_t OVF12:1; /* Overrun Flag x */ - vuint32_t OVF11:1; /* Overrun Flag x */ - vuint32_t OVF10:1; /* Overrun Flag x */ - vuint32_t OVF9:1; /* Overrun Flag x */ - vuint32_t OVF8:1; /* Overrun Flag x */ - vuint32_t:3; /* reserved in MPC563xM */ - vuint32_t OVF4:1; /* Overrun Flag x */ - vuint32_t OVF3:1; /* Overrun Flag x */ - vuint32_t:2; /* reserved in MPC563xM */ - vuint32_t OVF0:1; /* Overrun Flag x */ - } B; - } OSR; /* Overrun Status Register (OSR) SIU_OSR @baseaddress + 0x24 */ - - union { - vuint32_t R; - struct { - vuint32_t:16; /* */ - vuint32_t ORE15:1; /* Overrun Request Enable x */ - vuint32_t ORE14:1; /* Overrun Request Enable x */ - vuint32_t ORE13:1; /* Overrun Request Enable x */ - vuint32_t ORE12:1; /* Overrun Request Enable x */ - vuint32_t ORE11:1; /* Overrun Request Enable x */ - vuint32_t ORE10:1; /* Overrun Request Enable x */ - vuint32_t ORE9:1; /* Overrun Request Enable x */ - vuint32_t ORE8:1; /* Overrun Request Enable x */ - vuint32_t:3; /* reserved in MPC563xM */ - vuint32_t ORE4:1; /* Overrun Request Enable x */ - vuint32_t ORE3:1; /* Overrun Request Enable x */ - vuint32_t:2; /* reserved in MPC563xM */ - vuint32_t ORE0:1; /* Overrun Request Enable x */ - } B; - } ORER; /* Overrun Request Enable Register (ORER) SIU_ORER @baseaddress + 0x28 */ - - union { - vuint32_t R; - struct { - vuint32_t NMIRE:1; /* NMI Rising-Edge Event Enable x (new in MPC563xM) */ - vuint32_t:15; /* reserved in MPC563xM */ - vuint32_t IREE15:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE14:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE13:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE12:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE11:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE10:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE9:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE8:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t:3; /* reserved in MPC563xM */ - vuint32_t IREE4:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t IREE3:1; /* IRQ Rising-Edge Event Enable x */ - vuint32_t:2; /* reserved in MPC563xM */ - vuint32_t IREE0:1; /* IRQ Rising-Edge Event Enable x */ - } B; - } IREER; /* External IRQ Rising-Edge Event Enable Register (IREER) SIU_IREER @baseaddress + 0x2C */ - - union { - vuint32_t R; - struct { - vuint32_t NMIFE:1; /* NMI Falling-Edge Event Enable x (new in MPC563xM) */ - vuint32_t Reserverd:15; /* */ - vuint32_t IFEE15:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE14:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE13:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE12:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE11:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE10:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE9:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE8:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t:3; /* reserved in MPC563xM */ - vuint32_t IFEE4:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t IFEE3:1; /* IRQ Falling-Edge Event Enable x */ - vuint32_t:2; /* reserved in MPC563xM */ - vuint32_t IFEE0:1; /* IRQ Falling-Edge Event Enable x */ - } B; - } IFEER; /* External IRQ Falling-Edge Event Enable Regi (IFEER) SIU_IFEER @baseaddress + 0x30 */ - - union { - vuint32_t R; - struct { - vuint32_t:28; /* */ - vuint32_t DFL:4; /* Digital Filter Length */ - } B; - } IDFR; /* External IRQ Digital Filter Register (IDFR) SIU_IDFR @baseaddress + 0x40 */ - - int32_t SIU_reserverd_153[3]; - - union { - vuint16_t R; - struct { - vuint16_t:2; /* */ - vuint16_t PA:4; /* */ - vuint16_t OBE:1; /* */ - vuint16_t IBE:1; /* */ - vuint16_t DSC:2; /* */ - vuint16_t ODE:1; /* */ - vuint16_t HYS:1; /* */ - vuint16_t SRC:2; /* */ - vuint16_t WPE:1; /* */ - vuint16_t WPS:1; /* */ - } B; - } PCR[512]; /* Pad Configuration Register (PCR) SIU_PCR @baseaddress + 0x600 */ - - int32_t SIU_reserverd_164[112]; - - union { - vuint8_t R; - struct { - vuint8_t:7; /* */ - vuint8_t PDO:1; /* */ - } B; - } GPDO[512]; /* GPIO Pin Data Output Register (GPDO) SIU_GDPO @baseaddress + 0x800 */ - - union { - vuint8_t R; - struct { - vuint8_t:7; /* */ - vuint8_t PDI:1; /* */ - } B; - } GPDI[256]; /* GPIO Pin Data Input Register (GDPI) SIU_GDPI @baseaddress + 0x900 */ - - union { - vuint32_t R; - struct { - vuint32_t TSEL5:2; /* eQADC Trigger 5 Input */ - vuint32_t TSEL4:2; /* eQADC Trigger 4 Input */ - vuint32_t TSEL3:2; /* eQADC Trigger 3 Input */ - vuint32_t TSEL2:2; /* eQADC Trigger 4 Input */ - vuint32_t TSEL1:2; /* eQADC Trigger 1 Input */ - vuint32_t TSEL0:2; /* eQADC Trigger 0 Input */ - vuint32_t:20; /* */ - } B; - } ETISR; /* eQADC Trigger Input Select Register (ETISR) SIU_ETISR @baseaddress + 0x904 */ - - union { - vuint32_t R; - struct { - vuint32_t ESEL15:2; /* External IRQ Input Select x */ - vuint32_t ESEL14:2; /* External IRQ Input Select x */ - vuint32_t ESEL13:2; /* External IRQ Input Select x */ - vuint32_t ESEL12:2; /* External IRQ Input Select x */ - vuint32_t ESEL11:2; /* External IRQ Input Select x */ - vuint32_t ESEL10:2; /* External IRQ Input Select x */ - vuint32_t ESEL9:2; /* External IRQ Input Select x */ - vuint32_t ESEL8:2; /* External IRQ Input Select x */ - vuint32_t ESEL7:2; /* External IRQ Input Select x */ - vuint32_t ESEL6:2; /* External IRQ Input Select x */ - vuint32_t ESEL5:2; /* External IRQ Input Select x */ - vuint32_t ESEL4:2; /* External IRQ Input Select x */ - vuint32_t ESEL3:2; /* External IRQ Input Select x */ - vuint32_t ESEL2:2; /* External IRQ Input Select x */ - vuint32_t ESEL1:2; /* External IRQ Input Select x */ - vuint32_t ESEL0:2; /* External IRQ Input Select x */ - } B; - } EIISR; /* External IRQ Input Select Register (EIISR) SIU_EIISR @baseaddress + 0x908 */ - - union { - vuint32_t R; - struct { - vuint32_t:8; /* reserved in MPC563xM */ - vuint32_t SINSELB:2; /* DSPI_B Data Input Select SIN-SELB */ - vuint32_t SSSELB:2; /* DSPI_B Slave Select Input Select SS-SELB */ - vuint32_t SCKSELB:2; /* DSPI_B Clock Input Select SCK-SELB */ - vuint32_t TRIGSELB:2; /* DSPI_B Trigger Input Select TRIG-SELB */ - vuint32_t SINSELC:2; /* DSPI_C Data Input Select SIN-SELC */ - vuint32_t SSSELC:2; /* DSPI_C Slave Select Input Select SSSELC */ - vuint32_t SCKSELC:2; /* DSPI_C Clock Input Select SCK-SELC */ - vuint32_t TRIGSELC:2; /* DSPI_C Trigger Input Select TRIG-SELC */ - vuint32_t:8; /* reserved in MPC563xM */ - } B; - } DISR; /* DSPI Input Select Register (DISR) SIU_DISR @baseaddress + 0x90c */ - - union { - vuint32_t R; - struct { - vuint32_t:2; /* */ - vuint32_t ETSEL5:5; /* eQADC queue X Enhanced Trigger Selection eTSEL5 */ - vuint32_t ETSEL4:5; /* eQADC queue X Enhanced Trigger Selection eTSEL4 */ - vuint32_t ETSEL3:5; /* eQADC queue X Enhanced Trigger Selection eTSEL3 */ - vuint32_t ETSEL2:5; /* eQADC queue X Enhanced Trigger Selection eTSEL2 */ - vuint32_t ETSEL1:5; /* eQADC queue X Enhanced Trigger Selection eTSEL1 */ - vuint32_t ETSEL0:5; /* eQADC queue X Enhanced Trigger Selection eTSEL0 */ - } B; - } ISEL3; /* MUX Select Register 3 (ISEL3) (new in MPC563xM) SIU_ISEL3 @baseaddress + 0x920 */ - - int32_t SIU_reserverd_214[4]; - - union { - vuint32_t R; - struct { - vuint32_t:11; /* */ - vuint32_t ESEL5:1; /* eSEL5 */ - vuint32_t:3; /* */ - vuint32_t ESEL4:1; /* eSEL4 */ - vuint32_t:3; /* */ - vuint32_t ESEL3:1; /* eSEL3 */ - vuint32_t:3; /* */ - vuint32_t ESEL2:1; /* eSEL2 */ - vuint32_t:3; /* */ - vuint32_t ESEL1:1; /* eSEL1 */ - vuint32_t:3; /* */ - vuint32_t ESEL0:1; /* eSEL0 */ - } B; - } ISEL8; /* MUX Select Register 8 (ISEL8) (new in MPC563xM) SIU_ISEL8 @baseaddress + 0x924 */ - - union { - vuint32_t R; - struct { - vuint32_t:27; /* */ - vuint32_t ETSEL0A:5; /* eTSEL0A */ - } B; - } ISEL9; /* MUX Select Register 9(ISEL9) SIU_ISEL9 @baseaddress + 0x980 */ - - int32_t SIU_reserverd_230[22]; - - union { - vuint32_t R; - struct { - vuint32_t:14; /* */ - vuint32_t MATCH:1; /* Compare Register Match */ - vuint32_t DISNEX:1; /* Disable Nexus */ - vuint32_t:14; /* */ - vuint32_t CRSE:1; /* Calibration Reflection Suppression Enable (new in MPC563xM) */ - vuint32_t:1; /* */ - } B; - } CCR; /* Chip Configuration Register (CCR) SIU_CCR @baseaddress + 0x984 */ - - union { - vuint32_t R; - struct { - vuint32_t:28; /* The ENGDIV bit is reserved in MPC563xM */ - vuint32_t EBTS:1; /* External Bus Tap Select */ - vuint32_t:1; /* */ - vuint32_t EBDF:2; /* External Bus Division Factor */ - } B; - } ECCR; /* External Clock Control Register (ECCR) SIU_ECCR @baseaddress + 0x988 */ - - union { - vuint32_t R; - } CARH; /* Compare A High Register (CARH) SIU_CMPAH @baseaddress + 0x98C */ - - union { - vuint32_t R; - } CARL; /* Compare A Low Register (CARL) SIU_CMPAL @baseaddress + 0x990 */ - - union { - vuint32_t R; - } CBRH; /* Compare B High Register (CBRH) SIU_CMPBH @baseaddress + 0x994 */ - - union { - vuint32_t R; - } CBRL; /* Compare B Low Register (CBRL) SIU_CMPBL @baseaddress + 0x9A0 */ - - int32_t SIU_reserverd_250[2]; - - union { - vuint32_t R; - struct { - vuint32_t:27; /* Reserved */ - vuint32_t BYPASS:1; /* Bypass bit BY-PASS */ - vuint32_t SYSCLKDIV:2; /* System Clock Divide SYS-CLKDIV */ - vuint32_t:2; /* Reserved */ - } B; - } SYSDIV; /* System Clock Register (SYSDIV) (new in MPC563xM) SIU_SYSDIV @baseaddress + 0x9A4 */ - - union { - vuint32_t R; - struct { - vuint32_t CPUSTP:1; /* CPU stop request. When asserted, a stop request is sent to the following modules: */ - vuint32_t:2; /* Reserved */ - vuint32_t SWTSTP:1; /* SWT stop request. When asserted, a stop request is sent to the Software Watchdog */ - vuint32_t:1; /* Reserved */ - vuint32_t TPUSTP:1; /* eTPU stop request. When asserted, a stop request is sent to the eTPU module. */ - vuint32_t NPCSTP:1; /* Nexus stop request. When asserted, a stop request is sent to the Nexus Controller. */ - vuint32_t EBISTP:1; /* EBI stop request. When asserted, a stop request is sent to the external bus */ - vuint32_t ADCSTP:1; /* eQADC stop request. When asserted, a stop request is sent to the eQADC module. */ - vuint32_t:1; /* Reserved */ - vuint32_t MIOSSTP:1; /* Stop mode request */ - vuint32_t DFILSTP:1; /* Decimation filter stop request. When asserted, a stop request is sent to the */ - vuint32_t:1; /* Reserved */ - vuint32_t PITSTP:1; /* PIT stop request. When asserted, a stop request is sent to the periodical internal */ - vuint32_t:3; /* Reserved */ - vuint32_t CNCSTP:1; /* FlexCAN C stop request. When asserted, a stop request is sent to the FlexCAN C */ - vuint32_t:1; /* Reserved */ - vuint32_t CNASTP:1; /* FlexCAN A stop request. When asserted, a stop request is sent to the FlexCAN A */ - vuint32_t:1; /* Reserved */ - vuint32_t SPICSTP:1; /* DSPI C stop request. When asserted, a stop request is sent to the DSPI C. */ - vuint32_t SPIBSTP:1; /* DSPI B stop request. When asserted, a stop request is sent to the DSPI B. */ - vuint32_t:7; /* Reserved */ - vuint32_t SCIBSTP:1; /* eSCI B stop request. When asserted, a stop request is sent to the eSCI B module. */ - vuint32_t SCIASTP:1; /* eSCI A stop request. When asserted, a stop request is sent to the eSCIA module. */ - } B; - } HLT; /* Halt Register (HLT) (new in MPC563xM) SIU_HLT @baseaddress + 0x9A8 */ - - union { - vuint32_t R; - struct { - vuint32_t CPUACK:1; /* CPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t:2; /* Reserved */ - vuint32_t SWTACK:1; /* SWT stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t:1; /* Reserved */ - vuint32_t TPUACK:1; /* eTPU stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t NPCACK:1; /* Nexus stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t EBIACK:1; /* EBI stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t ADCACK:1; /* eQADC stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t:1; /* Reserved */ - vuint32_t MIOSACK:1; /* eMIOS stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t DFILACK:1; /* Decimation filter stop acknowledge. When asserted, indicates that a stop */ - vuint32_t:1; /* Reserved */ - vuint32_t PITACK:1; /* PIT stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t:3; /* Reserved */ - vuint32_t CNCACK:1; /* FlexCAN C stop acknowledge. When asserted, indicates that a stop acknowledge */ - vuint32_t:1; /* Reserved */ - vuint32_t CNAACK:1; /* FlexCAN A stop acknowledge. When asserted, indicates that a stop acknowledge */ - vuint32_t:1; /* Reserved */ - vuint32_t SPICACK:1; /* DSPI C stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t SPIBACK:1; /* DSPI B stop acknowledge. When asserted, indicates that a stop acknowledge was */ - vuint32_t:7; /* Reserved */ - vuint32_t SCIBACK:1; /* eSCI B stop acknowledge */ - vuint32_t SCIAACK:1; /* eSCI A stop acknowledge. */ - } B; - } HLTACK; /* Halt Acknowledge Register (HLTACK) (new in MPC563xM) SIU_HLTACK @baseaddress + 0x9ac */ - - int32_t SIU_reserved3[21]; - - }; /* end of SIU_tag */ -/****************************************************************************/ -/* MODULE : EMIOS */ -/****************************************************************************/ - struct EMIOS_tag { - union { - vuint32_t R; - struct { - vuint32_t DOZEEN:1; /* new in MPC563xM */ - vuint32_t MDIS:1; - vuint32_t FRZ:1; - vuint32_t GTBE:1; - vuint32_t ETB:1; - vuint32_t GPREN:1; - vuint32_t:6; - vuint32_t SRV:4; - vuint32_t GPRE:8; - vuint32_t:8; - } B; - } MCR; /* Module Configuration Register EMIOSMCR */ - - union { - vuint32_t R; - struct { - vuint32_t:8; - vuint32_t F23:1; - vuint32_t F22:1; - vuint32_t F21:1; - vuint32_t F20:1; - vuint32_t F19:1; - vuint32_t F18:1; - vuint32_t F17:1; - vuint32_t F16:1; - vuint32_t F15:1; - vuint32_t F14:1; - vuint32_t F13:1; - vuint32_t F12:1; - vuint32_t F11:1; - vuint32_t F10:1; - vuint32_t F9:1; - vuint32_t F8:1; - vuint32_t F7:1; - vuint32_t F6:1; - vuint32_t F5:1; - vuint32_t F4:1; - vuint32_t F3:1; - vuint32_t F2:1; - vuint32_t F1:1; - vuint32_t F0:1; - } B; - } GFR; /* Global FLAG Register EMIOSGFLAG */ - - union { - vuint32_t R; - struct { - vuint32_t:8; - vuint32_t OU23:1; - vuint32_t OU22:1; - vuint32_t OU21:1; - vuint32_t OU20:1; - vuint32_t OU19:1; - vuint32_t OU18:1; - vuint32_t OU17:1; - vuint32_t OU16:1; - vuint32_t OU15:1; - vuint32_t OU14:1; - vuint32_t OU13:1; - vuint32_t OU12:1; - vuint32_t OU11:1; - vuint32_t OU10:1; - vuint32_t OU9:1; - vuint32_t OU8:1; - vuint32_t OU7:1; - vuint32_t OU6:1; - vuint32_t OU5:1; - vuint32_t OU4:1; - vuint32_t OU3:1; - vuint32_t OU2:1; - vuint32_t OU1:1; - vuint32_t OU0:1; - } B; - } OUDR; /* Output Update Disable Register EMIOSOUDIS */ - - union { - vuint32_t R; - struct { - vuint32_t:8; /* */ - vuint32_t CHDIS23:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS22:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS21:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS20:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS19:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS18:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS17:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS16:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS15:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS14:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS13:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS12:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS11:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS10:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS9:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS8:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS7:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS6:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS5:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS4:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS3:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS2:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS1:1; /* Enable Channel [n] bit */ - vuint32_t CHDIS0:1; /* Enable Channel [n] bit */ - } B; - } UCDIS; /* Disable Channel (EMIOSUCDIS) EMIOSUCDIS (new in MPC563xM) @baseaddress + 0x0C */ - - int32_t EMIOS_reserverd_30[4]; - - struct { - union { - vuint32_t R; /* Channel A Data Register */ - } CADR; /* EMIOSA */ - - union { - vuint32_t R; /* Channel B Data Register */ - } CBDR; /* EMIOSB */ - - union { - vuint32_t R; /* Channel Counter Register */ - } CCNTR; /* EMIOSCNT */ - - union { - vuint32_t R; - struct { - vuint32_t FREN:1; - vuint32_t ODIS:1; - vuint32_t ODISSL:2; - vuint32_t UCPRE:2; - vuint32_t UCPREN:1; - vuint32_t DMA:1; - vuint32_t:1; - vuint32_t IF:4; - vuint32_t FCK:1; - vuint32_t FEN:1; - vuint32_t:3; - vuint32_t FORCMA:1; - vuint32_t FORCMB:1; - vuint32_t:1; - vuint32_t BSL:2; - vuint32_t EDSEL:1; - vuint32_t EDPOL:1; - vuint32_t MODE:7; - } B; - } CCR; /* Channel Control Register EMIOSC */ - - union { - vuint32_t R; - struct { - vuint32_t OVR:1; - vuint32_t:15; - vuint32_t OVFL:1; - vuint32_t:12; - vuint32_t UCIN:1; - vuint32_t UCOUT:1; - vuint32_t FLAG:1; - } B; - } CSR; /* Channel Status Register EMIOSS */ - - union { - vuint32_t R; /* Alternate Channel A Data Register */ - } ALTA; /* new in MPC563xM EMIOSALTA */ - - uint32_t emios_channel_reserved[2]; - - } CH[24]; - - }; /* end of EMIOS_tag */ -/****************************************************************************/ -/* MODULE : ETPU */ -/****************************************************************************/ - struct ETPU_tag { /* offset 0x0000 */ - union { /* eTPU module configuration register@baseaddress + 0x00 */ - vuint32_t R; - struct { - vuint32_t GEC:1; /* Global Exception Clear */ - vuint32_t SDMERR:1; /* */ - vuint32_t WDTOA:1; /* */ - vuint32_t WDTOB:1; /* */ - vuint32_t MGE1:1; /* MGEA */ - vuint32_t MGE2:1; /* MGEB */ - vuint32_t ILF1:1; /* Invalid instruction flag eTPU A. ILFFA */ - vuint32_t ILF2:1; /* Invalid instruction flag eTPU B. ILFFB */ - vuint32_t SCMERR:1; /* . */ - vuint32_t:2; /* */ - vuint32_t SCMSIZE:5; /* Shared Code Memory size */ - vuint32_t:4; /* */ - vuint32_t SCMMISC:1; /* SCM MISC Flag */ - vuint32_t SCMMISF:1; /* SCM MISC Flag */ - vuint32_t SCMMISEN:1; /* SCM MISC Enable */ - vuint32_t:2; /* */ - vuint32_t VIS:1; /* SCM Visability */ - vuint32_t:5; /* */ - vuint32_t GTBE:1; /* Global Time Base Enable */ - } B; - } MCR; /* ETPU_MCR */ - - /* offset 0x0004 */ - union { /* eTPU coherent dual-parameter controller register@baseaddress + 0x04 */ - vuint32_t R; - struct { - vuint32_t STS:1; /* Start Status bit */ - vuint32_t CTBASE:5; /* Channel Transfer Base */ - vuint32_t PBASE:10; /* Parameter Buffer Base Address PBBASE */ - vuint32_t PWIDTH:1; /* Parameter Width */ - vuint32_t PARAM0:7; /* Channel Parameter 0 PARM0 */ - vuint32_t WR:1; /* */ - vuint32_t PARAM1:7; /* Channel Parameter 1 PARM1 */ - } B; - } CDCR; /*ETPU_CDCR */ - - vuint32_t ETPU_reserved_0; - - /* offset 0x000C */ - union { /* eTPU MISC Compare Register@baseaddress + 0x0c */ - vuint32_t R; - struct { - vuint32_t ETPUMISCCMP:32; /* Expected multiple input signature calculator compare register value. EMISCCMP */ - } B; - } MISCCMPR /*ETPU_MISCCMPR */ ; - - /* offset 0x0010 */ - union { /* eTPU SCM Off-Range Data Register@baseaddress + 0x10 */ - vuint32_t R; - struct { - vuint32_t ETPUSCMOFFDATA:32; /* SCM Off-range read data value. */ - } B; - } SCMOFFDATAR; /*ETPU_SCMOFFDATAR */ - - /* offset 0x0014 */ - union { /* eTPU Engine Configuration Register (ETPUA_ECR)@baseaddress + 0x14 */ - vuint32_t R; - struct { - vuint32_t FEND:1; /* Force END */ - vuint32_t MDIS:1; /* Low power Stop */ - vuint32_t:1; /* */ - vuint32_t STF:1; /* Stop Flag */ - vuint32_t:4; /* */ - vuint32_t HLTF:1; /* Halt Mode Flag */ - vuint32_t:3; /* */ - vuint32_t FCSS:1; - vuint32_t FPSCK:3; /* Filter Prescaler Clock Control */ - vuint32_t CDFC:2; /* */ - vuint32_t:1; /* */ - vuint32_t ERBA:5; /* */ - vuint32_t SPPDIS:1; /* */ - vuint32_t:2; /* */ - vuint32_t ETB:5; /* Entry Table Base */ - } B; - } ECR_A; /*ETPU_ECR */ - - vuint32_t ETPU_reserved_1[2]; - - /* offset 0x0020 */ - union { /* eTPU Time Base Configuration Register (ETPU_TBCR)@baseaddress + 0x20 */ - vuint32_t R; - struct { - vuint32_t TCR2CTL:3; /* TCR2 Clock/Gate Control */ - vuint32_t TCRCF:2; /* TCRCLK Signal Filter Control */ - vuint32_t AM:2; /* Angle Mode */ - vuint32_t:3; /* */ - vuint32_t TCR2P:6; /* TCR2 Prescaler Control */ - vuint32_t TCR1CTL:2; /* TCR1 Clock/Gate Control */ - vuint32_t TCR1CS:1; /* */ - vuint32_t:5; /* */ - vuint32_t TCR1P:8; /* TCR1 Prescaler Control */ - } B; - } TBCR_A; /*ETPU_TBCR */ - - /* offset 0x0024 */ - union { /* eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)@baseaddress + 0x24 */ - vuint32_t R; - struct { - vuint32_t:8; /* */ - vuint32_t TCR1:24; /* TCR1 value. Used on matches and captures. For more information, see the eTPU reference manual. */ - } B; - } TB1R_A; /*ETPU_TB1R */ - - /* offset 0x0028 */ - union { /* eTPU Time Base 2 (TCR2) Visibility Register (ETPU_TB2R)@baseaddress + 0x28 */ - vuint32_t R; - struct { - vuint32_t:8; /* */ - vuint32_t TCR2:24; /* TCR2 value. Used on matches and captures. For information on TCR2, see the eTPU reference manual. */ - } B; - } TB2R_A; /*ETPU_TB2R */ - - /* offset 0x002C */ - union { /* STAC Bus Configuration Register (ETPU_STACCR)@baseaddress + 0x2c */ - vuint32_t R; - struct { - vuint32_t REN1:1; /* Resource Enable TCR1 */ - vuint32_t RSC1:1; /* Resource Control TCR1 */ - vuint32_t:2; /* */ - vuint32_t SERVER_ID1:4; /* */ - vuint32_t:4; /* */ - vuint32_t SRV1:4; /* Resource Server Slot */ - vuint32_t REN2:1; /* Resource Enable TCR2 */ - vuint32_t RSC2:1; /* Resource Control TCR2 */ - vuint32_t:2; /* */ - vuint32_t SERVER_ID2:4; /* */ - vuint32_t:4; /* */ - vuint32_t SRV2:4; /* Resource Server Slot */ - } B; - } REDCR_A; /*ETPU_REDCR */ - - vuint32_t ETPU_reserved_2[12]; - - /* offset 0x0060 */ - union { /* ETPU1 WDTR Register */ - vuint32_t R; - struct { - vuint32_t WDM:2; - vuint32_t:14; - vuint32_t WDCNT:16; - } B; - } WDTR_A; - - vuint32_t ETPU1_reserved_3; - - /* offset 0x0068 */ - union { /* ETPU1 IDLE Register */ - vuint32_t R; - struct { - vuint32_t IDLE_CNT:31; - vuint32_t ICLR:1; - } B; - } IDLE_A; - - vuint32_t ETPU_reserved_4[101]; - - /* offset 0x0200 */ - union { /* eTPU Channel Interrupt Status Register (ETPU_CISR)@baseaddress + 0x200 */ - vuint32_t R; - struct { - vuint32_t CIS31:1; /* Channel 31 Interrut Status */ - vuint32_t CIS30:1; /* Channel 30 Interrut Status */ - vuint32_t CIS29:1; /* Channel 29 Interrut Status */ - vuint32_t CIS28:1; /* Channel 28 Interrut Status */ - vuint32_t CIS27:1; /* Channel 27 Interrut Status */ - vuint32_t CIS26:1; /* Channel 26 Interrut Status */ - vuint32_t CIS25:1; /* Channel 25 Interrut Status */ - vuint32_t CIS24:1; /* Channel 24 Interrut Status */ - vuint32_t CIS23:1; /* Channel 23 Interrut Status */ - vuint32_t CIS22:1; /* Channel 22 Interrut Status */ - vuint32_t CIS21:1; /* Channel 21 Interrut Status */ - vuint32_t CIS20:1; /* Channel 20 Interrut Status */ - vuint32_t CIS19:1; /* Channel 19 Interrut Status */ - vuint32_t CIS18:1; /* Channel 18 Interrut Status */ - vuint32_t CIS17:1; /* Channel 17 Interrut Status */ - vuint32_t CIS16:1; /* Channel 16 Interrut Status */ - vuint32_t CIS15:1; /* Channel 15 Interrut Status */ - vuint32_t CIS14:1; /* Channel 14 Interrut Status */ - vuint32_t CIS13:1; /* Channel 13 Interrut Status */ - vuint32_t CIS12:1; /* Channel 12 Interrut Status */ - vuint32_t CIS11:1; /* Channel 11 Interrut Status */ - vuint32_t CIS10:1; /* Channel 10 Interrut Status */ - vuint32_t CIS9:1; /* Channel 9 Interrut Status */ - vuint32_t CIS8:1; /* Channel 8 Interrut Status */ - vuint32_t CIS7:1; /* Channel 7 Interrut Status */ - vuint32_t CIS6:1; /* Channel 6 Interrut Status */ - vuint32_t CIS5:1; /* Channel 5 Interrut Status */ - vuint32_t CIS4:1; /* Channel 4 Interrut Status */ - vuint32_t CIS3:1; /* Channel 3 Interrut Status */ - vuint32_t CIS2:1; /* Channel 2 Interrut Status */ - vuint32_t CIS1:1; /* Channel 1 Interrut Status */ - vuint32_t CIS0:1; /* Channel 0 Interrut Status */ - } B; - } CISR_A; /* ETPU_CISR */ - - int32_t ETPU_reserved_5[3]; - - /* offset 0x0210 */ - union { /* @baseaddress + 0x210 */ - vuint32_t R; - struct { - vuint32_t DTRS31:1; /* Channel 31 Data Transfer Request Status */ - vuint32_t DTRS30:1; /* Channel 30 Data Transfer Request Status */ - vuint32_t DTRS29:1; /* Channel 29 Data Transfer Request Status */ - vuint32_t DTRS28:1; /* Channel 28 Data Transfer Request Status */ - vuint32_t DTRS27:1; /* Channel 27 Data Transfer Request Status */ - vuint32_t DTRS26:1; /* Channel 26 Data Transfer Request Status */ - vuint32_t DTRS25:1; /* Channel 25 Data Transfer Request Status */ - vuint32_t DTRS24:1; /* Channel 24 Data Transfer Request Status */ - vuint32_t DTRS23:1; /* Channel 23 Data Transfer Request Status */ - vuint32_t DTRS22:1; /* Channel 22 Data Transfer Request Status */ - vuint32_t DTRS21:1; /* Channel 21 Data Transfer Request Status */ - vuint32_t DTRS20:1; /* Channel 20 Data Transfer Request Status */ - vuint32_t DTRS19:1; /* Channel 19 Data Transfer Request Status */ - vuint32_t DTRS18:1; /* Channel 18 Data Transfer Request Status */ - vuint32_t DTRS17:1; /* Channel 17 Data Transfer Request Status */ - vuint32_t DTRS16:1; /* Channel 16 Data Transfer Request Status */ - vuint32_t DTRS15:1; /* Channel 15 Data Transfer Request Status */ - vuint32_t DTRS14:1; /* Channel 14 Data Transfer Request Status */ - vuint32_t DTRS13:1; /* Channel 13 Data Transfer Request Status */ - vuint32_t DTRS12:1; /* Channel 12 Data Transfer Request Status */ - vuint32_t DTRS11:1; /* Channel 11 Data Transfer Request Status */ - vuint32_t DTRS10:1; /* Channel 10 Data Transfer Request Status */ - vuint32_t DTRS9:1; /* Channel 9 Data Transfer Request Status */ - vuint32_t DTRS8:1; /* Channel 8 Data Transfer Request Status */ - vuint32_t DTRS7:1; /* Channel 7 Data Transfer Request Status */ - vuint32_t DTRS6:1; /* Channel 6 Data Transfer Request Status */ - vuint32_t DTRS5:1; /* Channel 5 Data Transfer Request Status */ - vuint32_t DTRS4:1; /* Channel 4 Data Transfer Request Status */ - vuint32_t DTRS3:1; /* Channel 3 Data Transfer Request Status */ - vuint32_t DTRS2:1; /* Channel 2 Data Transfer Request Status */ - vuint32_t DTRS1:1; /* Channel 1 Data Transfer Request Status */ - vuint32_t DTRS0:1; /* Channel 0 Data Transfer Request Status */ - } B; - } CDTRSR_A; /* ETPU_CDTRSR */ - - int32_t ETPU_reserved_6[3]; - - /* offset 0x0220 */ - union { /* eTPU Channel Interrupt Overflow Status Register (ETPU_CIOSR)@baseaddress + 0x220 */ - vuint32_t R; - struct { - vuint32_t CIOS31:1; /* Channel 31 Interruput Overflow Status */ - vuint32_t CIOS30:1; /* Channel 30 Interruput Overflow Status */ - vuint32_t CIOS29:1; /* Channel 29 Interruput Overflow Status */ - vuint32_t CIOS28:1; /* Channel 28 Interruput Overflow Status */ - vuint32_t CIOS27:1; /* Channel 27 Interruput Overflow Status */ - vuint32_t CIOS26:1; /* Channel 26 Interruput Overflow Status */ - vuint32_t CIOS25:1; /* Channel 25 Interruput Overflow Status */ - vuint32_t CIOS24:1; /* Channel 24 Interruput Overflow Status */ - vuint32_t CIOS23:1; /* Channel 23 Interruput Overflow Status */ - vuint32_t CIOS22:1; /* Channel 22 Interruput Overflow Status */ - vuint32_t CIOS21:1; /* Channel 21 Interruput Overflow Status */ - vuint32_t CIOS20:1; /* Channel 20 Interruput Overflow Status */ - vuint32_t CIOS19:1; /* Channel 19 Interruput Overflow Status */ - vuint32_t CIOS18:1; /* Channel 18 Interruput Overflow Status */ - vuint32_t CIOS17:1; /* Channel 17 Interruput Overflow Status */ - vuint32_t CIOS16:1; /* Channel 16 Interruput Overflow Status */ - vuint32_t CIOS15:1; /* Channel 15 Interruput Overflow Status */ - vuint32_t CIOS14:1; /* Channel 14 Interruput Overflow Status */ - vuint32_t CIOS13:1; /* Channel 13 Interruput Overflow Status */ - vuint32_t CIOS12:1; /* Channel 12 Interruput Overflow Status */ - vuint32_t CIOS11:1; /* Channel 11 Interruput Overflow Status */ - vuint32_t CIOS10:1; /* Channel 10 Interruput Overflow Status */ - vuint32_t CIOS9:1; /* Channel 9 Interruput Overflow Status */ - vuint32_t CIOS8:1; /* Channel 8 Interruput Overflow Status */ - vuint32_t CIOS7:1; /* Channel 7 Interruput Overflow Status */ - vuint32_t CIOS6:1; /* Channel 6 Interruput Overflow Status */ - vuint32_t CIOS5:1; /* Channel 5 Interruput Overflow Status */ - vuint32_t CIOS4:1; /* Channel 4 Interruput Overflow Status */ - vuint32_t CIOS3:1; /* Channel 3 Interruput Overflow Status */ - vuint32_t CIOS2:1; /* Channel 2 Interruput Overflow Status */ - vuint32_t CIOS1:1; /* Channel 1 Interruput Overflow Status */ - vuint32_t CIOS0:1; /* Channel 0 Interruput Overflow Status */ - } B; - } CIOSR_A; /* ETPU_CIOSR */ - - int32_t ETPU_reserved_7[3]; - - /* offset 0x0230 */ - union { /* eTPU Channel Data Transfer Request Overflow Status Register@baseaddress + 0x230 */ - vuint32_t R; - struct { - vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ - vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ - vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ - vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ - vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ - vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ - vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ - vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ - vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ - vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ - vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ - vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ - vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ - vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ - vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ - vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ - vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ - vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ - vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ - vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ - vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ - vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ - vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ - vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ - vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ - vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ - vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ - vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ - vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ - vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ - vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ - vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ - } B; - } CDTROSR_A; /* ETPU_CDTROSR */ - - int32_t ETPU_reserved_8[3]; - - /* offset 0x0240 */ - union { /* eTPU Channel Interrupt Enable Register (ETPU_CIER)@baseaddress + 0x240 */ - vuint32_t R; - struct { - vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ - vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ - vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ - vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ - vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ - vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ - vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ - vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ - vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ - vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ - vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ - vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ - vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ - vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ - vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ - vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ - vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ - vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ - vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ - vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ - vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ - vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ - vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ - vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ - vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ - vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ - vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ - vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ - vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ - vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ - vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ - vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ - } B; - } CIER_A; /* ETPU_CIER */ - - int32_t ETPU_reserved_9[3]; - - /* offset 0x0250 */ - union { /* eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)@baseaddress + 0x250 */ - vuint32_t R; - struct { - vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ - vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ - vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ - vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ - vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ - vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ - vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ - vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ - vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ - vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ - vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ - vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ - vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ - vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ - vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ - vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ - vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ - vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ - vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ - vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ - vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ - vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ - vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ - vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ - vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ - vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ - vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ - vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ - vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ - vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ - vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ - vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CDTRER_A; /* ETPU_CDTRER */ - - int32_t ETPU_reserved_10[3]; - - /* offset 0x0260 */ - union { /* ETPUWDSR - eTPU Watchdog Status Register */ - vuint32_t R; - struct { - vuint32_t WDS31:1; /* Channel 31 Data Transfer Request Enable */ - vuint32_t WDS30:1; /* Channel 30 Data Transfer Request Enable */ - vuint32_t WDS29:1; /* Channel 29 Data Transfer Request Enable */ - vuint32_t WDS28:1; /* Channel 28 Data Transfer Request Enable */ - vuint32_t WDS27:1; /* Channel 27 Data Transfer Request Enable */ - vuint32_t WDS26:1; /* Channel 26 Data Transfer Request Enable */ - vuint32_t WDS25:1; /* Channel 25 Data Transfer Request Enable */ - vuint32_t WDS24:1; /* Channel 24 Data Transfer Request Enable */ - vuint32_t WDS23:1; /* Channel 23 Data Transfer Request Enable */ - vuint32_t WDS22:1; /* Channel 22 Data Transfer Request Enable */ - vuint32_t WDS21:1; /* Channel 21 Data Transfer Request Enable */ - vuint32_t WDS20:1; /* Channel 20 Data Transfer Request Enable */ - vuint32_t WDS19:1; /* Channel 19 Data Transfer Request Enable */ - vuint32_t WDS18:1; /* Channel 18 Data Transfer Request Enable */ - vuint32_t WDS17:1; /* Channel 17 Data Transfer Request Enable */ - vuint32_t WDS16:1; /* Channel 16 Data Transfer Request Enable */ - vuint32_t WDS15:1; /* Channel 15 Data Transfer Request Enable */ - vuint32_t WDS14:1; /* Channel 14 Data Transfer Request Enable */ - vuint32_t WDS13:1; /* Channel 13 Data Transfer Request Enable */ - vuint32_t WDS12:1; /* Channel 12 Data Transfer Request Enable */ - vuint32_t WDS11:1; /* Channel 11 Data Transfer Request Enable */ - vuint32_t WDS10:1; /* Channel 10 Data Transfer Request Enable */ - vuint32_t WDS9:1; /* Channel 9 Data Transfer Request Enable */ - vuint32_t WDS8:1; /* Channel 8 Data Transfer Request Enable */ - vuint32_t WDS7:1; /* Channel 7 Data Transfer Request Enable */ - vuint32_t WDS6:1; /* Channel 6 Data Transfer Request Enable */ - vuint32_t WDS5:1; /* Channel 5 Data Transfer Request Enable */ - vuint32_t WDS4:1; /* Channel 4 Data Transfer Request Enable */ - vuint32_t WDS3:1; /* Channel 3 Data Transfer Request Enable */ - vuint32_t WDS2:1; /* Channel 2 Data Transfer Request Enable */ - vuint32_t WDS1:1; /* Channel 1 Data Transfer Request Enable */ - vuint32_t WDS0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } WDSR_A; - - int32_t ETPU_reserved_11[7]; - - /* offset 0x0280 */ - union { /* ETPUCPSSR - eTPU Channel Pending Service Status Register */ - vuint32_t R; - struct { - vuint32_t SR31:1; /* Channel 31 Data Transfer Request Enable */ - vuint32_t SR30:1; /* Channel 30 Data Transfer Request Enable */ - vuint32_t SR29:1; /* Channel 29 Data Transfer Request Enable */ - vuint32_t SR28:1; /* Channel 28 Data Transfer Request Enable */ - vuint32_t SR27:1; /* Channel 27 Data Transfer Request Enable */ - vuint32_t SR26:1; /* Channel 26 Data Transfer Request Enable */ - vuint32_t SR25:1; /* Channel 25 Data Transfer Request Enable */ - vuint32_t SR24:1; /* Channel 24 Data Transfer Request Enable */ - vuint32_t SR23:1; /* Channel 23 Data Transfer Request Enable */ - vuint32_t SR22:1; /* Channel 22 Data Transfer Request Enable */ - vuint32_t SR21:1; /* Channel 21 Data Transfer Request Enable */ - vuint32_t SR20:1; /* Channel 20 Data Transfer Request Enable */ - vuint32_t SR19:1; /* Channel 19 Data Transfer Request Enable */ - vuint32_t SR18:1; /* Channel 18 Data Transfer Request Enable */ - vuint32_t SR17:1; /* Channel 17 Data Transfer Request Enable */ - vuint32_t SR16:1; /* Channel 16 Data Transfer Request Enable */ - vuint32_t SR15:1; /* Channel 15 Data Transfer Request Enable */ - vuint32_t SR14:1; /* Channel 14 Data Transfer Request Enable */ - vuint32_t SR13:1; /* Channel 13 Data Transfer Request Enable */ - vuint32_t SR12:1; /* Channel 12 Data Transfer Request Enable */ - vuint32_t SR11:1; /* Channel 11 Data Transfer Request Enable */ - vuint32_t SR10:1; /* Channel 10 Data Transfer Request Enable */ - vuint32_t SR9:1; /* Channel 9 Data Transfer Request Enable */ - vuint32_t SR8:1; /* Channel 8 Data Transfer Request Enable */ - vuint32_t SR7:1; /* Channel 7 Data Transfer Request Enable */ - vuint32_t SR6:1; /* Channel 6 Data Transfer Request Enable */ - vuint32_t SR5:1; /* Channel 5 Data Transfer Request Enable */ - vuint32_t SR4:1; /* Channel 4 Data Transfer Request Enable */ - vuint32_t SR3:1; /* Channel 3 Data Transfer Request Enable */ - vuint32_t SR2:1; /* Channel 2 Data Transfer Request Enable */ - vuint32_t SR1:1; /* Channel 1 Data Transfer Request Enable */ - vuint32_t SR0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CPSSR_A; /* ETPU_CPSSR */ - - int32_t ETPU_reserved_12[3]; - - /* offset 0x0290 */ - union { /* ETPUCSSR - eTPU Channel Service Status Register */ - vuint32_t R; - struct { - vuint32_t SS31:1; /* Channel 31 Data Transfer Request Enable */ - vuint32_t SS30:1; /* Channel 30 Data Transfer Request Enable */ - vuint32_t SS29:1; /* Channel 29 Data Transfer Request Enable */ - vuint32_t SS28:1; /* Channel 28 Data Transfer Request Enable */ - vuint32_t SS27:1; /* Channel 27 Data Transfer Request Enable */ - vuint32_t SS26:1; /* Channel 26 Data Transfer Request Enable */ - vuint32_t SS25:1; /* Channel 25 Data Transfer Request Enable */ - vuint32_t SS24:1; /* Channel 24 Data Transfer Request Enable */ - vuint32_t SS23:1; /* Channel 23 Data Transfer Request Enable */ - vuint32_t SS22:1; /* Channel 22 Data Transfer Request Enable */ - vuint32_t SS21:1; /* Channel 21 Data Transfer Request Enable */ - vuint32_t SS20:1; /* Channel 20 Data Transfer Request Enable */ - vuint32_t SS19:1; /* Channel 19 Data Transfer Request Enable */ - vuint32_t SS18:1; /* Channel 18 Data Transfer Request Enable */ - vuint32_t SS17:1; /* Channel 17 Data Transfer Request Enable */ - vuint32_t SS16:1; /* Channel 16 Data Transfer Request Enable */ - vuint32_t SS15:1; /* Channel 15 Data Transfer Request Enable */ - vuint32_t SS14:1; /* Channel 14 Data Transfer Request Enable */ - vuint32_t SS13:1; /* Channel 13 Data Transfer Request Enable */ - vuint32_t SS12:1; /* Channel 12 Data Transfer Request Enable */ - vuint32_t SS11:1; /* Channel 11 Data Transfer Request Enable */ - vuint32_t SS10:1; /* Channel 10 Data Transfer Request Enable */ - vuint32_t SS9:1; /* Channel 9 Data Transfer Request Enable */ - vuint32_t SS8:1; /* Channel 8 Data Transfer Request Enable */ - vuint32_t SS7:1; /* Channel 7 Data Transfer Request Enable */ - vuint32_t SS6:1; /* Channel 6 Data Transfer Request Enable */ - vuint32_t SS5:1; /* Channel 5 Data Transfer Request Enable */ - vuint32_t SS4:1; /* Channel 4 Data Transfer Request Enable */ - vuint32_t SS3:1; /* Channel 3 Data Transfer Request Enable */ - vuint32_t SS2:1; /* Channel 2 Data Transfer Request Enable */ - vuint32_t SS1:1; /* Channel 1 Data Transfer Request Enable */ - vuint32_t SS0:1; /* Channel 0 Data Transfer Request Enable */ - } B; - } CSSR_A; /* ETPU_CSSR */ - - int32_t ETPU_reserved_13[3]; - int32_t ETPU_reserved_14[88]; - -/***************************** Channels ********************************/ -/* Note not all devices implement all channels or even 2 engines */ -/* Each eTPU engine can implement 64 channels, however most devcies */ -/* only implemnet 32 channels. The eTPU block can implement 1 or 2 */ -/* engines per instantiation */ -/***********************************************************************/ - - struct { - union { /* eTPU Channel n Configuration Register (ETPU_CnCR)@baseaddress + 0x400 */ - vuint32_t R; - struct { - vuint32_t CIE:1; /* Channel Interruput Enable */ - vuint32_t DTRE:1; /* Data Transfer Request Enable */ - vuint32_t CPR:2; /* Channel Priority */ - vuint32_t:2; /* */ - vuint32_t ETPD:1; /* This bit selects which channel signal, input or output, is used in the entry point selection */ - vuint32_t ETCS:1; /* Entry Table Condition Select */ - vuint32_t:3; /* */ - vuint32_t CFS:5; /* Channel Function Select */ - vuint32_t ODIS:1; /* Output disable */ - vuint32_t OPOL:1; /* output polarity */ - vuint32_t:3; /* */ - vuint32_t CPBA:11; /* Channel Parameter Base Address */ - } B; - } CR; /* ETPU_CnCR */ - - union { /* eTPU Channel n Status Control Register (ETPU_CnSCR)@baseaddress + 0x404 */ - vuint32_t R; - struct { - vuint32_t CIS:1; /* Channel Interruput Status */ - vuint32_t CIOS:1; /* Channel Interruput Overflow Status */ - vuint32_t:6; /* */ - vuint32_t DTRS:1; /* Data Transfer Status */ - vuint32_t DTROS:1; /* Data Transfer Overflow Status */ - vuint32_t:6; /* */ - vuint32_t IPS:1; /* Input Pin State */ - vuint32_t OPS:1; /* Output Pin State */ - vuint32_t OBE:1; /* Output Pin State */ - vuint32_t:11; /* */ - vuint32_t FM1:1; /* Function mode */ - vuint32_t FM0:1; /* Function mode */ - } B; - } SCR; /* ETPU_CnSCR */ - - union { /* eTPU channel host service request register (ETPU_CnHSRR)@baseaddress + 0x408 */ - vuint32_t R; - struct { - vuint32_t:29; /* Host Service Request */ - vuint32_t HSR:3; /* */ - } B; - } HSRR; /* ETPU_CnHSRR */ - int32_t ETPU_reserved_18; - - } CHAN[127]; - /**** Note: Not all channels implemented on all devices. Up 64 can be implemented on */ - }; /* end of ETPU_tag */ -/****************************************************************************/ -/* MODULE : XBAR */ -/****************************************************************************/ - struct XBAR_tag { - union { - vuint32_t R; - struct { - vuint32_t:4; /* Master 7 Priority - Not implemented */ - vuint32_t:4; /* Master 6 Priority - Not implemented */ - vuint32_t:4; /* Master 5 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ - vuint32_t:4; /* Master 3 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ - vuint32_t:1; /* */ - vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ - vuint32_t:1; /* */ - vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ - } B; - } MPR0; /* Master Priority Register for Slave port 0 @baseaddress + 0x00 - Flash */ - - int32_t XBAR_reserverd_35[3]; - - union { - vuint32_t R; - struct { - vuint32_t RO:1; /* Read Only */ - vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ - vuint32_t:6; /* Slave General Purpose Control Register Reserved */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:6; /* */ - vuint32_t ARB:2; /* Arbitration Mode */ - vuint32_t:2; /* */ - vuint32_t PCTL:2; /* Parking Control */ - vuint32_t:1; /* */ - vuint32_t PARK:3; /* PARK */ - } B; - } SGPCR0; /* Slave General Purpose Control Register 0 @baseaddress + 0x10 */ - - int32_t XBAR_reserverd_71[59]; - - union { - vuint32_t R; - struct { - vuint32_t:4; /* Master 7 Priority - Not implemented */ - vuint32_t:4; /* Master 6 Priority - Not implemented */ - vuint32_t:4; /* Master 5 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ - vuint32_t:4; /* Master 3 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ - vuint32_t:1; /* */ - vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ - vuint32_t:1; /* */ - vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ - } B; - } MPR1; /* Master Priority Register for Slave port 1 @baseaddress + 0x100 */ - - int32_t XBAR_reserverd_105[3]; - - union { - vuint32_t R; - struct { - vuint32_t RO:1; /* Read Only */ - vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ - vuint32_t:6; /* Slave General Purpose Control Register Reserved */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:6; /* */ - vuint32_t ARB:2; /* Arbitration Mode */ - vuint32_t:2; /* */ - vuint32_t PCTL:2; /* Parking Control */ - vuint32_t:1; /* */ - vuint32_t PARK:3; /* PARK */ - } B; - } SGPCR1; /* Slave General Purpose Control Register 1 @baseaddress + 0x110 */ - - int32_t XBAR_reserverd_141[59]; - -/* Slave General Purpose Control Register 2 @baseaddress + 0x210 - not implemented */ - - int32_t XBAR_reserverd_211[64]; - - union { - vuint32_t R; - struct { - vuint32_t:4; /* Master 7 Priority - Not implemented */ - vuint32_t:4; /* Master 6 Priority - Not implemented */ - vuint32_t:4; /* Master 5 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ - vuint32_t:4; /* Master 3 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ - vuint32_t:1; /* */ - vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ - vuint32_t:1; /* */ - vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ - } B; - } MPR3; /* Master Priority Register for Slave port 3 @baseaddress + 0x300 */ - - int32_t XBAR_reserverd_245[3]; - - union { - vuint32_t R; - struct { - vuint32_t RO:1; /* Read Only */ - vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ - vuint32_t:6; /* Slave General Purpose Control Register Reserved */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:6; /* */ - vuint32_t ARB:2; /* Arbitration Mode */ - vuint32_t:2; /* */ - vuint32_t PCTL:2; /* Parking Control */ - vuint32_t:1; /* */ - vuint32_t PARK:3; /* PARK */ - } B; - } SGPCR3; /* Slave General Purpose Control Register 3 @baseaddress + 0x310 */ - - int32_t XBAR_reserverd_281[59]; - - /* Slave General Purpose Control Register 4 @baseaddress + 0x410 - not implemented */ - - int32_t XBAR_reserverd_351[64]; - - /* Slave XBAR Port 5 Not implemented @baseaddress + 0x510 */ - - int32_t XBAR_reserverd_421[64]; - - /* Slave Port 6 not implemented @baseaddress + 0x610 */ - - int32_t XBAR_reserverd_491[64]; - - union { - vuint32_t R; - struct { - vuint32_t:4; /* Master 7 Priority - Not implemented */ - vuint32_t:4; /* Master 6 Priority - Not implemented */ - vuint32_t:4; /* Master 5 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR4:3; /* Master 4 Priority - Core load/store & Nexus port */ - vuint32_t:4; /* Master 3 Priority - Not implemented */ - vuint32_t:1; /* */ - vuint32_t MSTR2:3; /* Master 2 Priority - Unused implemented master port */ - vuint32_t:1; /* */ - vuint32_t MSTR1:3; /* Master 1 Priority - eDMA */ - vuint32_t:1; /* */ - vuint32_t MSTR0:3; /* Master 0 Priority - e200z335 core Instruction */ - } B; - } MPR7; /* Master Priority Register for Slave port 7 @baseaddress + 0x700 */ - - int32_t XBAR_reserverd_525[3]; - - union { - vuint32_t R; - struct { - vuint32_t RO:1; /* Read Only */ - vuint32_t HLP:1; /* Halt Low Priority (new in MPC563xM) */ - vuint32_t:6; /* Slave General Purpose Control Register Reserved */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE4:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:1; /* High Priority Enable (new in MPC563xM - not implemented) */ - vuint32_t HPE2:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE1:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t HPE0:1; /* High Priority Enable (new in MPC563xM) */ - vuint32_t:6; /* */ - vuint32_t ARB:2; /* Arbitration Mode */ - vuint32_t:2; /* */ - vuint32_t PCTL:2; /* Parking Control */ - vuint32_t:1; /* */ - vuint32_t PARK:3; /* PARK */ - } B; - } SGPCR7; /* Slave General Purpose Control Register 7 @baseaddress + 0x710 */ - - int32_t XBAR_reserverd_561[59]; - - union { - vuint32_t R; - struct { - vuint32_t:29; /* */ - vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ - } B; - } MGPCR0; /* Master General Purpose Control Register 0 @baseaddress + 0x800 */ - - int32_t XBAR_reserverd_564[63]; - - union { - vuint32_t R; - struct { - vuint32_t:29; /* */ - vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ - } B; - } MGPCR1; /* Master General Purpose Control Register 1 @baseaddress + 0x900 */ - - int32_t XBAR_reserverd_567[63]; - - union { - vuint32_t R; - struct { - vuint32_t:29; /* */ - vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ - } B; - } MGPCR2; /* Master General Purpose Control Register 2 @baseaddress + 0xA00 */ - - int32_t XBAR_reserverd_570[63]; - - /* Master General Purpose Control Register 3 not implemented @baseaddress + 0xB00 */ - - int32_t XBAR_reserverd_573[64]; - - union { - vuint32_t R; - struct { - vuint32_t:29; /* */ - vuint32_t AULB:3; /* Arbitrate on Undefined Length Bursts */ - } B; - } MGPCR4; /* Master General Purpose Control Register 4 @baseaddress + 0xC00 */ - - int32_t XBAR_reserverd_576[64]; - - /* Master General Purpose Control Register 5 not implemented @baseaddress + 0xD00 */ - - int32_t XBAR_reserverd_579[64]; - - /* Master General Purpose Control Register 6 not implemented @baseaddress + 0xE00 */ - - int32_t XBAR_reserverd_582[64]; - - /* Master General Purpose Control Register 7 not implemented @baseaddress + 0xF00 */ - - }; /* end of XBAR_tag */ -/****************************************************************************/ -/* MODULE : ECSM */ -/****************************************************************************/ - struct ECSM_tag { - /* SWTCR, SWTSR and SWTIR don't exist in MPC563xM */ - uint32_t ecsm_reserved1[16]; - - uint8_t ecsm_reserved3[3]; /* base + 0x40 */ - - union { - vuint8_t R; - struct { - vuint8_t:6; - vuint8_t ERNCR:1; /* EPRNCR */ - vuint8_t EFNCR:1; /* EPFNCR */ - } B; - } ECR; /* ECC Configuration Register */ - - uint8_t ecsm_reserved4[3]; /* base + 0x44 */ - - union { - vuint8_t R; - struct { - vuint8_t:6; - vuint8_t RNCE:1; /* PRNCE */ - vuint8_t FNCE:1; /* PFNCE */ - } B; - } ESR; /* ECC Status Register */ - - /* EEGR don't exist in MPC563xM */ - uint32_t ecsm_reserved4a[2]; - - union { - vuint32_t R; - struct { - vuint32_t FEAR:32; /* PFEAR */ - } B; - } FEAR; /* Flash ECC Address Register PFEAR - 0x50 */ - - uint16_t ecsm_reserved4b; - - union { - vuint8_t R; - struct { - vuint8_t:4; - vuint8_t FEMR:4; /* PFEMR */ - } B; - } FEMR; /* Flash ECC Master Register PFEMR */ - - union { - vuint8_t R; - struct { - vuint8_t WRITE:1; - vuint8_t SIZE:3; - vuint8_t PROT0:1; /* PROTECTION */ - vuint8_t PROT1:1; /* PROTECTION */ - vuint8_t PROT2:1; /* PROTECTION */ - vuint8_t PROT3:1; /* PROTECTION */ - } B; - } FEAT; /* Flash ECC Attributes Register PFEAT */ - - union { - vuint32_t R; - struct { - vuint32_t FEDH:32; /* PFEDR */ - } B; - } FEDRH; /* Flash ECC Data High Register PFEDRH */ - - union { - vuint32_t R; - struct { - vuint32_t FEDL:32; /* PFEDR */ - } B; - } FEDRL; /* Flash ECC Data Low Register PFEDRL */ - - union { - vuint32_t R; - struct { - vuint32_t REAR:32; /* PREAR */ - } B; - } REAR; /* RAM ECC Address PREAR */ - - uint8_t ecsm_reserved5; - - union { - vuint8_t R; - struct { - vuint8_t PRESR:8; - } B; - } PRESR; /* RAM ECC Syndrome (new in MPC563xM) */ - - union { - vuint8_t R; - struct { - vuint8_t:4; - vuint8_t REMR:4; /* PREMR */ - } B; - } REMR; /* RAM ECC Master PREMR */ - - union { - vuint8_t R; - struct { - vuint8_t WRITE:1; - vuint8_t SIZE:3; - vuint8_t PROT0:1; /* PROTECTION */ - vuint8_t PROT1:1; /* PROTECTION */ - vuint8_t PROT2:1; /* PROTECTION */ - vuint8_t PROT3:1; /* PROTECTION */ - } B; - } REAT; /* RAM ECC Attributes Register PREAT */ - - union { - vuint32_t R; - struct { - vuint32_t REDH:32; /* PREDR */ - } B; - } REDRH; /* RAM ECC Data High Register PREDRH */ - - union { - vuint32_t R; - struct { - vuint32_t REDL:32; /* PREDR */ - } B; - } REDRL; /* RAMECC Data Low Register PREDRL */ - - }; -/****************************************************************************/ -/* MODULE : EDMA */ -/****************************************************************************/ - struct EDMA_tag { - union { - vuint32_t R; - struct { - vuint32_t:14; /* Reserved */ - vuint32_t CX:1; /* Cancel Transfer (new in MPC563xM) */ - vuint32_t ECX:1; /* Error Cancel Transfer (new in MPC563xM) */ - vuint32_t GRP3PRI:2; /* Channel Group 3 Priority (new in MPC563xM) */ - vuint32_t GRP2PRI:2; /* Channel Group 2 Priority (new in MPC563xM) */ - vuint32_t GRP1PRI:2; /* Channel Group 1 Priority */ - vuint32_t GRP0PRI:2; /* Channel Group 0 Priority */ - vuint32_t EMLM:1; /* Enable Minor Loop Mapping (new in MPC563xM) */ - vuint32_t CLM:1; /* Continuous Link Mode (new in MPC563xM) */ - vuint32_t HALT:1; /* Halt DMA Operations (new in MPC563xM) */ - vuint32_t HOE:1; /* Halt On Error (new in MPC563xM) */ - vuint32_t ERGA:1; /* Enable Round Robin Group Arbitration */ - vuint32_t ERCA:1; /* Enable Round Robin Channel Arbitration */ - vuint32_t EDBG:1; /* Enable Debug */ - vuint32_t EBW:1; /* Enable Buffered Writes */ - } B; - } CR; /* DMA Control Register DMACR @baseaddress + 0x0 */ - - union { - vuint32_t R; - struct { - vuint32_t VLD:1; /* Logical OR of all DMAERRH */ - - vuint32_t:14; /* Reserved */ - vuint32_t ECX:1; /* (new in MPC563xM) */ - vuint32_t GPE:1; /* Group Priority Error */ - vuint32_t CPE:1; /* Channel Priority Error */ - vuint32_t ERRCHN:6; /* ERRCHN[5:0] Error Channel Number or The channel number of the last recorded error */ - vuint32_t SAE:1; /* Source Address Error 0 */ - vuint32_t SOE:1; /* Source Offset Error */ - vuint32_t DAE:1; /* Destination Address Error */ - vuint32_t DOE:1; /* Destination Offset Error */ - vuint32_t NCE:1; /* Nbytes/Citer Configuration Error */ - vuint32_t SGE:1; /* Scatter/Gather Configuration Error */ - vuint32_t SBE:1; /* Source Bus Error */ - vuint32_t DBE:1; /* Destination Bus Error */ - - } B; - } ESR; /* DMAES Error Status Register */ - - uint32_t edma_reserved_erqrh; - - union { - vuint32_t R; - struct { - vuint32_t ERQ31:1; - vuint32_t ERQ30:1; - vuint32_t ERQ29:1; - vuint32_t ERQ28:1; - vuint32_t ERQ27:1; - vuint32_t ERQ26:1; - vuint32_t ERQ25:1; - vuint32_t ERQ24:1; - vuint32_t ERQ23:1; - vuint32_t ERQ22:1; - vuint32_t ERQ21:1; - vuint32_t ERQ20:1; - vuint32_t ERQ19:1; - vuint32_t ERQ18:1; - vuint32_t ERQ17:1; - vuint32_t ERQ16:1; - vuint32_t ERQ15:1; - vuint32_t ERQ14:1; - vuint32_t ERQ13:1; - vuint32_t ERQ12:1; - vuint32_t ERQ11:1; - vuint32_t ERQ10:1; - vuint32_t ERQ09:1; - vuint32_t ERQ08:1; - vuint32_t ERQ07:1; - vuint32_t ERQ06:1; - vuint32_t ERQ05:1; - vuint32_t ERQ04:1; - vuint32_t ERQ03:1; - vuint32_t ERQ02:1; - vuint32_t ERQ01:1; - vuint32_t ERQ00:1; - } B; - } ERQRL; /* DMAERQL ,DMA Enable Request Register Low */ - - uint32_t edma_reserved_eeirh; - - union { - vuint32_t R; - struct { - vuint32_t EEI31:1; - vuint32_t EEI30:1; - vuint32_t EEI29:1; - vuint32_t EEI28:1; - vuint32_t EEI27:1; - vuint32_t EEI26:1; - vuint32_t EEI25:1; - vuint32_t EEI24:1; - vuint32_t EEI23:1; - vuint32_t EEI22:1; - vuint32_t EEI21:1; - vuint32_t EEI20:1; - vuint32_t EEI19:1; - vuint32_t EEI18:1; - vuint32_t EEI17:1; - vuint32_t EEI16:1; - vuint32_t EEI15:1; - vuint32_t EEI14:1; - vuint32_t EEI13:1; - vuint32_t EEI12:1; - vuint32_t EEI11:1; - vuint32_t EEI10:1; - vuint32_t EEI09:1; - vuint32_t EEI08:1; - vuint32_t EEI07:1; - vuint32_t EEI06:1; - vuint32_t EEI05:1; - vuint32_t EEI04:1; - vuint32_t EEI03:1; - vuint32_t EEI02:1; - vuint32_t EEI01:1; - vuint32_t EEI00:1; - } B; - } EEIRL; /* DMAEEIL , DMA Enable Error Interrupt Register Low */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 SERQ:7 */ - } SERQR; /* DMASERQ , DMA Set Enable Request Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 CERQ:7 */ - } CERQR; /* DMACERQ , DMA Clear Enable Request Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 SEEI:7 */ - } SEEIR; /* DMASEEI , DMA Set Enable Error Interrupt Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 CEEI:7 */ - } CEEIR; /* DMACEEI , DMA Clear Enable Error Interrupt Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 CINT:7 */ - } CIRQR; /* DMACINT , DMA Clear Interrupt Request Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 CERR:7 */ - } CER; /* DMACERR , DMA Clear error Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 SSRT:7 */ - } SSBR; /* DMASSRT , Set Start Bit Register */ - - union { - vuint8_t R; - vuint8_t B; /* NOP:1 CDNE:7 */ - } CDSBR; /* DMACDNE , Clear Done Status Bit Register */ - - uint32_t edma_reserved_irqrh; - - union { - vuint32_t R; - struct { - vuint32_t INT31:1; - vuint32_t INT30:1; - vuint32_t INT29:1; - vuint32_t INT28:1; - vuint32_t INT27:1; - vuint32_t INT26:1; - vuint32_t INT25:1; - vuint32_t INT24:1; - vuint32_t INT23:1; - vuint32_t INT22:1; - vuint32_t INT21:1; - vuint32_t INT20:1; - vuint32_t INT19:1; - vuint32_t INT18:1; - vuint32_t INT17:1; - vuint32_t INT16:1; - vuint32_t INT15:1; - vuint32_t INT14:1; - vuint32_t INT13:1; - vuint32_t INT12:1; - vuint32_t INT11:1; - vuint32_t INT10:1; - vuint32_t INT09:1; - vuint32_t INT08:1; - vuint32_t INT07:1; - vuint32_t INT06:1; - vuint32_t INT05:1; - vuint32_t INT04:1; - vuint32_t INT03:1; - vuint32_t INT02:1; - vuint32_t INT01:1; - vuint32_t INT00:1; - } B; - } IRQRL; /* DMAINTL , DMA Interrupt Request Low */ - - uint32_t edma_reserved_erh; - - union { - vuint32_t R; - struct { - vuint32_t ERR31:1; - vuint32_t ERR30:1; - vuint32_t ERR29:1; - vuint32_t ERR28:1; - vuint32_t ERR27:1; - vuint32_t ERR26:1; - vuint32_t ERR25:1; - vuint32_t ERR24:1; - vuint32_t ERR23:1; - vuint32_t ERR22:1; - vuint32_t ERR21:1; - vuint32_t ERR20:1; - vuint32_t ERR19:1; - vuint32_t ERR18:1; - vuint32_t ERR17:1; - vuint32_t ERR16:1; - vuint32_t ERR15:1; - vuint32_t ERR14:1; - vuint32_t ERR13:1; - vuint32_t ERR12:1; - vuint32_t ERR11:1; - vuint32_t ERR10:1; - vuint32_t ERR09:1; - vuint32_t ERR08:1; - vuint32_t ERR07:1; - vuint32_t ERR06:1; - vuint32_t ERR05:1; - vuint32_t ERR04:1; - vuint32_t ERR03:1; - vuint32_t ERR02:1; - vuint32_t ERR01:1; - vuint32_t ERR00:1; - } B; - } ERL; /* DMAERRL , DMA Error Low */ - - int32_t edma_reserverd_hrsh[1]; - - int32_t edma_reserverd_hrsl[1]; - - int32_t edma_reserverd_gpor[1]; - - int32_t EDMA_reserverd_223[49]; - - union { - vuint8_t R; - struct { - vuint8_t ECP:1; - vuint8_t DPA:1; - vuint8_t GRPPRI:2; - vuint8_t CHPRI:4; - } B; - } CPR[64]; /* DCHPRI [32] , Channel n Priority */ - - uint32_t edma_reserved2[944]; - -/****************************************************************************/ -/* DMA2 Transfer Control Descriptor */ -/****************************************************************************/ - - struct tcd_t { /*for "standard" format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=0 && EDMA.EMLM=0 ) */ - vuint32_t SADDR; /* source address */ - - vuint16_t SMOD:5; /* source address modulo */ - vuint16_t SSIZE:3; /* source transfer size */ - vuint16_t DMOD:5; /* destination address modulo */ - vuint16_t DSIZE:3; /* destination transfer size */ - vint16_t SOFF; /* signed source address offset */ - vuint32_t NBYTES; /* inner (“minor”) byte count */ - vint32_t SLAST; /* last destination address adjustment, or - - scatter/gather address (if e_sg = 1) */ - vuint32_t DADDR; /* destination address */ - vuint16_t CITERE_LINK:1; - vuint16_t CITER:15; - vint16_t DOFF; /* signed destination address offset */ - vint32_t DLAST_SGA; - vuint16_t BITERE_LINK:1; /* beginning ("major") iteration count */ - vuint16_t BITER:15; - vuint16_t BWC:2; /* bandwidth control */ - vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ - vuint16_t DONE:1; /* channel done */ - vuint16_t ACTIVE:1; /* channel active */ - vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ - vuint16_t E_SG:1; /* enable scatter/gather descriptor */ - vuint16_t D_REQ:1; /* disable ipd_req when done */ - vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ - vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ - vuint16_t START:1; /* explicit channel start */ - } TCD[64]; /* TCD [32] , transfer_control_descriptor */ - }; - - struct EDMA_TCD_alt1_tag { /*for alternate format TCDs (when EDMA.TCD[x].CITER.E_LINK==BITER.E_LINK=1 ) */ - - struct tcd_alt1_t { - vuint32_t SADDR; /* source address */ - - vuint16_t SMOD:5; /* source address modulo */ - vuint16_t SSIZE:3; /* source transfer size */ - vuint16_t DMOD:5; /* destination address modulo */ - vuint16_t DSIZE:3; /* destination transfer size */ - vint16_t SOFF; /* signed source address offset */ - vuint32_t NBYTES; /* inner (“minor”) byte count */ - vint32_t SLAST; /* last destination address adjustment, or - - scatter/gather address (if e_sg = 1) */ - vuint32_t DADDR; /* destination address */ - vuint16_t CITERE_LINK:1; - vuint16_t CITERLINKCH:6; - vuint16_t CITER:9; - vint16_t DOFF; /* signed destination address offset */ - vint32_t DLAST_SGA; - vuint16_t BITERE_LINK:1; /* beginning (“major”) iteration count */ - vuint16_t BITERLINKCH:6; - vuint16_t BITER:9; - vuint16_t BWC:2; /* bandwidth control */ - vuint16_t MAJORLINKCH:6; /* enable channel-to-channel link */ - vuint16_t DONE:1; /* channel done */ - vuint16_t ACTIVE:1; /* channel active */ - vuint16_t MAJORE_LINK:1; /* enable channel-to-channel link */ - vuint16_t E_SG:1; /* enable scatter/gather descriptor */ - vuint16_t D_REQ:1; /* disable ipd_req when done */ - vuint16_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ - vuint16_t INT_MAJ:1; /* interrupt on major loop completion */ - vuint16_t START:1; /* explicit channel start */ - } TCD[64]; /* TCD [32] , transfer_control_descriptor */ - }; - -/****************************************************************************/ -/* MODULE : INTC */ -/****************************************************************************/ - struct INTC_tag { - union { - vuint32_t R; - struct { - vuint32_t:18; /* Reserved */ - vuint32_t VTES_PRC1:1; /* Vector Table Entry Size for PRC1 (new in MPC563xM) */ - vuint32_t:4; /* Reserved */ - vuint32_t HVEN_PRC1:1; /* Hardware Vector Enable for PRC1 (new in MPC563xM) */ - vuint32_t:2; /* Reserved */ - vuint32_t VTES:1; /* Vector Table Entry Size for PRC0 VTES_PRC0 */ - vuint32_t:4; /* Reserved */ - vuint32_t HVEN:1; /* Hardware Vector Enable for PRC0 HVEN_PRC0 */ - } B; - } MCR; /* INTC Module Configuration Register (MCR) INTC_BCR @baseaddress + 0x00 */ - int32_t INTC_reserverd_10[1]; - - union { - vuint32_t R; - struct { - vuint32_t:28; /* Reserved */ - vuint32_t PRI:4; /* Priority */ - } B; - } CPR; /* INTC Current Priority Register for Processor 0 (CPR) INTC_CPR_PRC0 @baseaddress + 0x08 */ - - int32_t INTC_reserved_1; /* CPR_PRC1 - INTC Current Priority Register for Processor 1 (CPR_PRC1) INTC_CPR_PRC1 @baseaddress + 0x0c */ - - union { - vuint32_t R; - struct { - vuint32_t VTBA:21; /* Vector Table Base Address VTBA_PRC0 */ - vuint32_t INTVEC:9; /* Interrupt Vector INTVEC_PRC0 */ - vuint32_t:2; /* Reserved */ - } B; - } IACKR; /* INTC Interrupt Acknowledge Register for Processor 0 (IACKR) INTC_IACKR_PRC0 @baseaddress + 0x10 */ - - int32_t INTC_reserverd_2; /* IACKR_PRC1 - INTC Interrupt Acknowledge Register for Processor 1 (IACKR_PRC1) INTC_IACKR_PRC1 @baseaddress + 0x14 */ - - union { - vuint32_t R; - } EOIR; /* INTC End of Interrupt Register for Processor 0 (EOIR) INTC_EOIR_PRC0 @baseaddress + 0x18 */ - - int32_t INTC_reserverd_3; /* EOIR_PRC1 - INTC End of Interrupt Register for Processor 1 (EOIR_PRC1) INTC_EOIR_PRC1 @baseaddress + 0x1C */ - - union { - vuint8_t R; - struct { - vuint8_t:6; /* Reserved */ - vuint8_t SET:1; /* Set Flag bits */ - vuint8_t CLR:1; /* Clear Flag bits */ - } B; - } SSCIR[8]; /* INTC Software Set/Clear Interrupt Registers (SSCIR) INTC_SSCIRn @baseaddress + 0x20 */ - - int32_t INTC_reserverd_32[6]; - - union { - vuint8_t R; - struct { - vuint8_t PRC_SEL:2; /* Processor Select (new in MPC563xM) */ - vuint8_t:2; /* Reserved */ - vuint8_t PRI:4; /* Priority Select */ - } B; - } PSR[512]; /* INTC Priority Select Registers (PSR) INTC_PSR @baseaddress + 0x40 */ - - }; /* end of INTC_tag */ -/****************************************************************************/ -/* MODULE : EQADC */ -/****************************************************************************/ - struct EQADC_tag { - union { - vuint32_t R; - struct { - vuint32_t:24; - vuint32_t ICEA0:1; - vuint32_t ICEA1:1; - vuint32_t:1; - vuint32_t ESSIE:2; - vuint32_t:1; - vuint32_t DBG:2; - } B; - } MCR; /* Module Configuration Register EQADC_MCR */ - - int32_t EQADC_reserved00; - - union { - vuint32_t R; - struct { - vuint32_t:6; - vuint32_t NMF:26; - } B; - } NMSFR; /* Null Message Send Format Register EQADC_NMSFR */ - - union { - vuint32_t R; - struct { - vuint32_t:28; - vuint32_t DFL:4; - } B; - } ETDFR; /* External Trigger Digital Filter Register EQADC_ETDFR */ - - union { - vuint32_t R; - struct { - vuint32_t CFPUSH:32; /* CF_PUSH */ - } B; - } CFPR[6]; /* CFIFO Push Registers EQADC_CFPR */ - - uint32_t eqadc_reserved1; - - uint32_t eqadc_reserved2; - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t RFPOP:16; /* RF_POP */ - } B; - } RFPR[6]; /* Result FIFO Pop Registers EQADC_RFPR */ - - uint32_t eqadc_reserved3; - - uint32_t eqadc_reserved4; - - union { - vuint16_t R; - struct { - vuint16_t:3; - vuint16_t CFEE0:1; - vuint16_t STRME0:1; - vuint16_t SSE:1; - vuint16_t CFINV:1; - vuint16_t:1; - vuint16_t MODE:4; - vuint16_t AMODE0:4; /* CFIFO0 only */ - } B; - } CFCR[6]; /* CFIFO Control Registers EQADC_CFCR */ - - uint32_t eqadc_reserved5; - - union { - vuint16_t R; - struct { - vuint16_t NCIE:1; - vuint16_t TORIE:1; - vuint16_t PIE:1; - vuint16_t EOQIE:1; - vuint16_t CFUIE:1; - vuint16_t:1; - vuint16_t CFFE:1; - vuint16_t CFFS:1; - vuint16_t:4; - vuint16_t RFOIE:1; - vuint16_t:1; - vuint16_t RFDE:1; - vuint16_t RFDS:1; - } B; - } IDCR[6]; /* Interrupt and DMA Control Registers EQADC_IDCR */ - - uint32_t eqadc_reserved6; - - union { - vuint32_t R; - struct { - vuint32_t NCF:1; - vuint32_t TORF:1; - vuint32_t PF:1; - vuint32_t EOQF:1; - vuint32_t CFUF:1; - vuint32_t SSS:1; - vuint32_t CFFF:1; - vuint32_t:5; - vuint32_t RFOF:1; - vuint32_t:1; - vuint32_t RFDF:1; - vuint32_t:1; - vuint32_t CFCTR:4; - vuint32_t TNXTPTR:4; - vuint32_t RFCTR:4; - vuint32_t POPNXTPTR:4; - } B; - } FISR[6]; /* FIFO and Interrupt Status Registers EQADC_FISR */ - - uint32_t eqadc_reserved7; - - uint32_t eqadc_reserved8; - - union { - vuint16_t R; - struct { - vuint16_t:5; - vuint16_t TCCF:11; /* TC_CF */ - } B; - } CFTCR[6]; /* CFIFO Transfer Counter Registers EQADC_CFTCR */ - - uint32_t eqadc_reserved9; - - union { - vuint32_t R; - struct { - vuint32_t CFS0:2; /* CFS0_TCB0 */ - vuint32_t CFS1:2; /* CFS1_TCB0 */ - vuint32_t CFS2:2; /* CFS2_TCB0 */ - vuint32_t CFS3:2; /* CFS3_TCB0 */ - vuint32_t CFS4:2; /* CFS4_TCB0 */ - vuint32_t CFS5:2; /* CFS5_TCB0 */ - vuint32_t:5; - vuint32_t LCFTCB0:4; - vuint32_t TC_LCFTCB0:11; - } B; - } CFSSR0; /* CFIFO Status Register 0 EQADC_CFSSR0 */ - - union { - vuint32_t R; - struct { - vuint32_t CFS0:2; /* CFS0_TCB1 */ - vuint32_t CFS1:2; /* CFS1_TCB1 */ - vuint32_t CFS2:2; /* CFS2_TCB1 */ - vuint32_t CFS3:2; /* CFS3_TCB1 */ - vuint32_t CFS4:2; /* CFS4_TCB1 */ - vuint32_t CFS5:2; /* CFS5_TCB1 */ - vuint32_t:5; - vuint32_t LCFTCB1:4; - vuint32_t TC_LCFTCB1:11; - } B; - } CFSSR1; /* CFIFO Status Register 1 EQADC_CFSSR1 */ - - union { - vuint32_t R; - struct { - vuint32_t CFS0:2; /* CFS0_TSSI */ - vuint32_t CFS1:2; /* CFS1_TSSI */ - vuint32_t CFS2:2; /* CFS2_TSSI */ - vuint32_t CFS3:2; /* CFS3_TSSI */ - vuint32_t CFS4:2; /* CFS4_TSSI */ - vuint32_t CFS5:2; /* CFS5_TSSI */ - vuint32_t:4; - vuint32_t ECBNI:1; - vuint32_t LCFTSSI:4; - vuint32_t TC_LCFTSSI:11; - } B; - } CFSSR2; /* CFIFO Status Register 2 EQADC_CFSSR2 */ - - union { - vuint32_t R; - struct { - vuint32_t CFS0:2; - vuint32_t CFS1:2; - vuint32_t CFS2:2; - vuint32_t CFS3:2; - vuint32_t CFS4:2; - vuint32_t CFS5:2; - vuint32_t:20; - } B; - } CFSR; /* EQADC_CFSR */ - - uint32_t eqadc_reserved11; - - union { - vuint32_t R; - struct { - vuint32_t:21; - vuint32_t MDT:3; - vuint32_t:4; - vuint32_t BR:4; - } B; - } SSICR; /* SSI Control Register EQADC_SSICR */ - - union { - vuint32_t R; - struct { - vuint32_t RDV:1; - vuint32_t:5; - vuint32_t RDATA:26; - } B; - } SSIRDR; /* SSI Recieve Data Register EQADC_SSIRDR @ baseaddress + 0xB8 */ - - uint32_t eqadc_reserved11b[5]; - - uint32_t eqadc_reserved15; /* EQADC Red Line Client Configuration Register @ baseaddress + 0xD0 */ - /* REDLCCR is not implemented in the MPC563xM */ - - uint32_t eqadc_reserved12[11]; - - struct { - union { - vuint32_t R; - - /*B.CFIFOx_DATAw */ - - } R[4]; /*EQADC_CFxRw */ - - union { - vuint32_t R; - /*B.CFIFOx_EDATAw */ - } EDATA[4]; /*EQADC_CFxERw (new in MPC563xM) */ - - uint32_t eqadc_reserved13[8]; - - } CF[6]; - - uint32_t eqadc_reserved14[32]; - - struct { - union { - vuint32_t R; - /*RFIFOx_DATAw */ - } R[4]; /*EQADC_RFxRw */ - - uint32_t eqadc_reserved15[12]; - - } RF[6]; - - }; - /****************************************************************************/ -/* MODULE : DSPI */ -/****************************************************************************/ - struct DSPI_tag { - union { - vuint32_t R; - struct { - vuint32_t MSTR:1; - vuint32_t CONT_SCKE:1; - vuint32_t DCONF:2; - vuint32_t FRZ:1; - vuint32_t MTFE:1; - vuint32_t PCSSE:1; - vuint32_t ROOE:1; - vuint32_t PCSIS7:1; /* new in MPC563xM */ - vuint32_t PCSIS6:1; /* new in MPC563xM */ - vuint32_t PCSIS5:1; - vuint32_t PCSIS4:1; - vuint32_t PCSIS3:1; - vuint32_t PCSIS2:1; - vuint32_t PCSIS1:1; - vuint32_t PCSIS0:1; - vuint32_t DOZE:1; - vuint32_t MDIS:1; - vuint32_t DIS_TXF:1; - vuint32_t DIS_RXF:1; - vuint32_t CLR_TXF:1; - vuint32_t CLR_RXF:1; - vuint32_t SMPL_PT:2; - vuint32_t:7; - vuint32_t HALT:1; - } B; - } MCR; /* Module Configuration Register DSPI_MCR @baseaddress + 0x00 */ - - uint32_t dspi_reserved1; - - union { - vuint32_t R; - struct { - vuint32_t TCNT:16; /* SPI_TCNT */ - vuint32_t:16; - } B; - } TCR; /* DSPI Transfer Count Register DSPI_TCR @baseaddress + 0x08 */ - - union { - vuint32_t R; - struct { - vuint32_t DBR:1; - vuint32_t FMSZ:4; - vuint32_t CPOL:1; - vuint32_t CPHA:1; - vuint32_t LSBFE:1; - vuint32_t PCSSCK:2; - vuint32_t PASC:2; - vuint32_t PDT:2; - vuint32_t PBR:2; - vuint32_t CSSCK:4; - vuint32_t ASC:4; - vuint32_t DT:4; - vuint32_t BR:4; - } B; - } CTAR[8]; /* Clock and Transfer Attributes Registers DSPI_CTARx @baseaddress + 0x0C - 0x28 */ - - union { - vuint32_t R; - struct { - vuint32_t TCF:1; - vuint32_t TXRXS:1; - vuint32_t:1; - vuint32_t EOQF:1; - vuint32_t TFUF:1; - vuint32_t:1; - vuint32_t TFFF:1; - vuint32_t:5; - vuint32_t RFOF:1; - vuint32_t:1; - vuint32_t RFDF:1; - vuint32_t:1; - vuint32_t TXCTR:4; - vuint32_t TXNXTPTR:4; - vuint32_t RXCTR:4; - vuint32_t POPNXTPTR:4; - } B; - } SR; /* Status Register DSPI_SR @baseaddress + 0x2C */ - - union { - vuint32_t R; - struct { - vuint32_t TCFRE:1; /*TCF_RE */ - vuint32_t:2; - vuint32_t EOQFRE:1; /*EQQF_RE */ - vuint32_t TFUFRE:1; /*TFUF_RE */ - vuint32_t:1; - vuint32_t TFFFRE:1; /*TFFF_RE */ - vuint32_t TFFFDIRS:1; /*TFFF_DIRS */ - vuint32_t:4; - vuint32_t RFOFRE:1; /*RFOF_RE */ - vuint32_t:1; - vuint32_t RFDFRE:1; /*RFDF_RE */ - vuint32_t RFDFDIRS:1; /*RFDF_DIRS */ - vuint32_t:16; - } B; - } RSER; /* DMA/Interrupt Request Select and Enable Register DSPI_RSER @baseaddress + 0x30 */ - - union { - vuint32_t R; - struct { - vuint32_t CONT:1; - vuint32_t CTAS:3; - vuint32_t EOQ:1; - vuint32_t CTCNT:1; - vuint32_t:2; - vuint32_t PCS7:1; /* new in MPC563xM */ - vuint32_t PCS6:1; /* new in MPC563xM */ - vuint32_t PCS5:1; - vuint32_t PCS4:1; - vuint32_t PCS3:1; - vuint32_t PCS2:1; - vuint32_t PCS1:1; - vuint32_t PCS0:1; - vuint32_t TXDATA:16; - } B; - } PUSHR; /* PUSH TX FIFO Register DSPI_PUSHR @baseaddress + 0x34 */ - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t RXDATA:16; - } B; - } POPR; /* POP RX FIFO Register DSPI_POPR @baseaddress + 0x38 */ - - union { - vuint32_t R; - struct { - vuint32_t TXCMD:16; - vuint32_t TXDATA:16; - } B; - } TXFR[4]; /* Transmit FIFO Registers DSPI_TXFRx @baseaddress + 0x3c - 0x78 */ - - vuint32_t DSPI_reserved_txf[12]; - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t RXDATA:16; - } B; - } RXFR[4]; /* Transmit FIFO Registers DSPI_RXFRx @baseaddress + 0x7c - 0xB8 */ - - vuint32_t DSPI_reserved_rxf[12]; - - union { - vuint32_t R; - struct { - vuint32_t MTOE:1; - vuint32_t:1; - vuint32_t MTOCNT:6; - vuint32_t:3; - vuint32_t TSBC:1; - vuint32_t TXSS:1; - vuint32_t TPOL:1; - vuint32_t TRRE:1; - vuint32_t CID:1; - vuint32_t DCONT:1; - vuint32_t DSICTAS:3; - vuint32_t:4; - vuint32_t DPCS7:1; - vuint32_t DPCS6:1; - vuint32_t DPCS5:1; - vuint32_t DPCS4:1; - vuint32_t DPCS3:1; - vuint32_t DPCS2:1; - vuint32_t DPCS1:1; - vuint32_t DPCS0:1; - } B; - } DSICR; /* DSI Configuration Register DSPI_DSICR @baseaddress + 0xBC */ - - union { - vuint32_t R; - struct { - vuint32_t SER_DATA:32; /* 32bit instead of 16 in MPC563xM */ - } B; - } SDR; /* DSI Serialization Data Register DSPI_SDR @baseaddress + 0xC0 */ - - union { - vuint32_t R; - struct { - vuint32_t ASER_DATA:32; /* 32bit instead of 16 in MPC563xM */ - } B; - } ASDR; /* DSI Alternate Serialization Data Register DSPI_ASDR @baseaddress + 0xC4 */ - - union { - vuint32_t R; - struct { - vuint32_t COMP_DATA:32; /* 32bit instead of 16 in MPC563xM */ - } B; - } COMPR; /* DSI Transmit Comparison Register DSPI_COMPR @baseaddress + 0xC8 */ - - union { - vuint32_t R; - struct { - vuint32_t DESER_DATA:32; /* 32bit instead of 16 in MPC563xM */ - } B; - } DDR; /* DSI deserialization Data Register DSPI_DDR @baseaddress + 0xCC */ - - union { - vuint32_t R; - struct { - vuint32_t:3; - vuint32_t TSBCNT:5; - vuint32_t:16; - vuint32_t DPCS1_7:1; - vuint32_t DPCS1_6:1; - vuint32_t DPCS1_5:1; - vuint32_t DPCS1_4:1; - vuint32_t DPCS1_3:1; - vuint32_t DPCS1_2:1; - vuint32_t DPCS1_1:1; - vuint32_t DPCS1_0:1; - } B; - } DSICR1; /* DSI Configuration Register 1 DSPI_DSICR1 @baseaddress + 0xD0 */ - - }; -/****************************************************************************/ -/* MODULE : eSCI */ -/****************************************************************************/ - struct ESCI_tag { - union { - vuint32_t R; - struct { - vuint32_t:3; - vuint32_t SBR:13; - vuint32_t LOOPS:1; - vuint32_t:1; /* Reserved in MPC563xM */ - vuint32_t RSRC:1; - vuint32_t M:1; - vuint32_t WAKE:1; - vuint32_t ILT:1; - vuint32_t PE:1; - vuint32_t PT:1; - vuint32_t TIE:1; - vuint32_t TCIE:1; - vuint32_t RIE:1; - vuint32_t ILIE:1; - vuint32_t TE:1; - vuint32_t RE:1; - vuint32_t RWU:1; - vuint32_t SBK:1; - } B; - } CR1; /* Control Register 1 SCIBDH, SCIBDL, SCICR1, SCICR2 @baseaddress + 0x00 */ - - union { - vuint16_t R; - struct { - vuint16_t MDIS:1; - vuint16_t FBR:1; - vuint16_t BSTP:1; - vuint16_t IEBERR:1; /* BERIE */ - vuint16_t RXDMA:1; - vuint16_t TXDMA:1; - vuint16_t BRK13:1; /* BRCL */ - vuint16_t TXDIR:1; - vuint16_t BESM13:1; /* BESM */ - vuint16_t SBSTP:1; /* BESTP */ - vuint16_t RXPOL:1; - vuint16_t PMSK:1; - vuint16_t ORIE:1; - vuint16_t NFIE:1; - vuint16_t FEIE:1; - vuint16_t PFIE:1; - } B; - } CR2; /* Control Register 2 SCICR3, SCICR4 @baseaddress + 0x04 */ - - union { - vuint16_t R; - struct { - vuint16_t R8:1; /* RN */ - vuint16_t T8:1; /* TN */ - vuint16_t ERR:1; - vuint16_t:1; - vuint16_t R:4; - vuint8_t D; - } B; - } DR; /* Data Register SCIDRH, SCIDRL @baseaddress + 0x06 */ - - union { - vuint32_t R; - struct { - vuint32_t TDRE:1; - vuint32_t TC:1; - vuint32_t RDRF:1; - vuint32_t IDLE:1; - vuint32_t OR:1; - vuint32_t NF:1; - vuint32_t FE:1; - vuint32_t PF:1; - vuint32_t:3; - vuint32_t BERR:1; - vuint32_t:2; - vuint32_t TACT:1; - vuint32_t RAF:1; /* RACT */ - vuint32_t RXRDY:1; - vuint32_t TXRDY:1; - vuint32_t LWAKE:1; - vuint32_t STO:1; - vuint32_t PBERR:1; - vuint32_t CERR:1; - vuint32_t CKERR:1; - vuint32_t FRC:1; - vuint32_t:6; - vuint32_t UREQ:1; - vuint32_t OVFL:1; - } B; - } SR; /* Status Register SCISR1, SCIRSR2, LINSTAT1, LINSTAT2 @baseaddress + 0x08 */ - - union { - vuint32_t R; - struct { - vuint32_t LRES:1; - vuint32_t WU:1; - vuint32_t WUD0:1; - vuint32_t WUD1:1; - vuint32_t:2; /* reserved: LDBG and DSF not longer supported */ - vuint32_t PRTY:1; - vuint32_t LIN:1; - vuint32_t RXIE:1; - vuint32_t TXIE:1; - vuint32_t WUIE:1; - vuint32_t STIE:1; - vuint32_t PBIE:1; - vuint32_t CIE:1; - vuint32_t CKIE:1; - vuint32_t FCIE:1; - vuint32_t:6; - vuint32_t UQIE:1; - vuint32_t OFIE:1; - vuint32_t:8; - } B; - } LCR; /* LIN Control Register LINCTRL1, LINCTRL2, LINCTRL3 @baseaddress + 0x0C */ - - union { - vuint32_t R; - } LTR; /* LIN Transmit Register LINTX @baseaddress + 0x10 */ - - union { - vuint32_t R; - } LRR; /* LIN Recieve Register LINRX @baseaddress + 0x14 */ - - union { - vuint32_t R; - struct { - vuint32_t P:16; - vuint32_t:3; - vuint32_t SYNM:1; - vuint32_t EROE:1; - vuint32_t ERFE:1; - vuint32_t ERPE:1; - vuint32_t M2:1; - vuint32_t:8; - } B; - } LPR; /* LIN CRC Polynom Register LINCRCP1, LINCRCP2, SCICR5 @baseaddress + 0x18 */ - - }; -/****************************************************************************/ -/* MODULE : eSCI */ -/****************************************************************************/ - struct ESCI_12_13_bit_tag { - union { - vuint16_t R; - struct { - vuint16_t R8:1; - vuint16_t T8:1; - vuint16_t ERR:1; - vuint16_t:1; - vuint16_t D:12; - } B; - } DR; /* Data Register */ - }; -/****************************************************************************/ -/* MODULE : FlexCAN */ -/****************************************************************************/ - struct FLEXCAN_BUF_t { - union { - vuint32_t R; - struct { - vuint32_t:4; - vuint32_t CODE:4; - vuint32_t:1; - vuint32_t SRR:1; - vuint32_t IDE:1; - vuint32_t RTR:1; - vuint32_t LENGTH:4; - vuint32_t TIMESTAMP:16; - } B; - } CS; - - union { - vuint32_t R; - struct { - vuint32_t PRIO:3; - vuint32_t STD_ID:11; - vuint32_t EXT_ID:18; - } B; - } ID; - - union { - /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ - /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ - vuint32_t W[2]; /* Data buffer in words (32 bits) */ - /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ - } DATA; - - }; /* end of FLEXCAN_BUF_t */ - - struct FLEXCAN_RXFIFO_t { - union { - vuint32_t R; - struct { - vuint32_t:9; - vuint32_t SRR:1; - vuint32_t IDE:1; - vuint32_t RTR:1; - vuint32_t LENGTH:4; - vuint32_t TIMESTAMP:16; - } B; - } CS; - - union { - vuint32_t R; - struct { - vuint32_t:3; - vuint32_t STD_ID:11; - vuint32_t EXT_ID:18; - } B; - } ID; - - union { - /*vuint8_t B[8]; *//* Data buffer in Bytes (8 bits) *//* Not used in MPC563xM */ - /*vuint16_t H[4]; *//* Data buffer in Half-words (16 bits) *//* Not used in MPC563xM */ - vuint32_t W[2]; /* Data buffer in words (32 bits) */ - /*vuint32_t R[2]; *//* Data buffer in words (32 bits) *//* Not used in MPC563xM */ - } DATA; - - uint32_t FLEXCAN_RXFIFO_reserved[20]; /* {0x00E0-0x0090}/0x4 = 0x14 */ - - union { - vuint32_t R; - } IDTABLE[8]; - - }; /* end of FLEXCAN_RXFIFO_t */ - - struct FLEXCAN2_tag { - union { - vuint32_t R; - struct { - vuint32_t MDIS:1; - vuint32_t FRZ:1; - vuint32_t FEN:1; /* new in MPC563xM */ - vuint32_t HALT:1; - vuint32_t NOTRDY:1; /* NOT_RDY */ - vuint32_t WAK_MSK:1; /* new in MPC563xM */ - vuint32_t SOFTRST:1; /* SOFT_RST */ - vuint32_t FRZACK:1; /* FRZ_ACK */ - vuint32_t SUPV:1; /* new in MPC563xM */ - vuint32_t SLF_WAK:1; /* new in MPC563xM */ - - vuint32_t WRNEN:1; /* WRN_EN */ - - vuint32_t MDISACK:1; /* LPM_ACK */ - vuint32_t WAK_SRC:1; /* new in MPC563xM */ - vuint32_t DOZE:1; /* new in MPC563xM */ - - vuint32_t SRXDIS:1; /* SRX_DIS */ - vuint32_t MBFEN:1; /* BCC */ - vuint32_t:2; - - vuint32_t LPRIO_EN:1; /* new in MPC563xM */ - vuint32_t AEN:1; /* new in MPC563xM */ - vuint32_t:2; - vuint32_t IDAM:2; /* new in MPC563xM */ - vuint32_t:2; - - vuint32_t MAXMB:6; - } B; - } MCR; /* Module Configuration Register */ - - union { - vuint32_t R; - struct { - vuint32_t PRESDIV:8; - vuint32_t RJW:2; - vuint32_t PSEG1:3; - vuint32_t PSEG2:3; - vuint32_t BOFFMSK:1; /* BOFF_MSK */ - vuint32_t ERRMSK:1; /* ERR_MSK */ - vuint32_t CLKSRC:1; /* CLK_SRC */ - vuint32_t LPB:1; - vuint32_t TWRNMSK:1; /* TWRN_MSK */ - vuint32_t RWRNMSK:1; /* RWRN_MSK */ - vuint32_t:2; - vuint32_t SMP:1; - vuint32_t BOFFREC:1; /* BOFF_REC */ - vuint32_t TSYN:1; - vuint32_t LBUF:1; - vuint32_t LOM:1; - vuint32_t PROPSEG:3; - } B; /* Control Register */ - } CR; /* CTRL */ - - union { - vuint32_t R; - } TIMER; /* Free Running Timer */ - - int32_t FLEXCAN_reserved00; - - union { - vuint32_t R; - struct { - vuint32_t:3; - vuint32_t MI:29; - } B; - } RXGMASK; /* RX Global Mask */ - - union { - vuint32_t R; - struct { - vuint32_t:3; - vuint32_t MI:29; - } B; - } RX14MASK; /* RX 14 Mask */ - - union { - vuint32_t R; - struct { - vuint32_t:3; - vuint32_t MI:29; - } B; - } RX15MASK; /* RX 15 Mask */ - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t RXECNT:8; - vuint32_t TXECNT:8; - } B; - } ECR; /* Error Counter Register */ - - union { - vuint32_t R; - struct { - vuint32_t:14; - vuint32_t TWRNINT:1; /* TWRN_INT */ - vuint32_t RWRNINT:1; /* RWRN_INT */ - vuint32_t BIT1ERR:1; /* BIT1_ERR */ - vuint32_t BIT0ERR:1; /* BIT0_ERR */ - vuint32_t ACKERR:1; /* ACK_ERR */ - vuint32_t CRCERR:1; /* CRC_ERR */ - vuint32_t FRMERR:1; /* FRM_ERR */ - vuint32_t STFERR:1; /* STF_ERR */ - vuint32_t TXWRN:1; /* TX_WRN */ - vuint32_t RXWRN:1; /* RX_WRN */ - vuint32_t IDLE:1; - vuint32_t TXRX:1; - vuint32_t FLTCONF:2; /* FLT_CONF */ - vuint32_t:1; - vuint32_t BOFFINT:1; /* BOFF_INT */ - vuint32_t ERRINT:1; /* ERR_INT */ - vuint32_t WAK_INT:1; /* new in MPC563xM */ - } B; - } ESR; /* Error and Status Register */ - - union { - vuint32_t R; - struct { - vuint32_t BUF63M:1; - vuint32_t BUF62M:1; - vuint32_t BUF61M:1; - vuint32_t BUF60M:1; - vuint32_t BUF59M:1; - vuint32_t BUF58M:1; - vuint32_t BUF57M:1; - vuint32_t BUF56M:1; - vuint32_t BUF55M:1; - vuint32_t BUF54M:1; - vuint32_t BUF53M:1; - vuint32_t BUF52M:1; - vuint32_t BUF51M:1; - vuint32_t BUF50M:1; - vuint32_t BUF49M:1; - vuint32_t BUF48M:1; - vuint32_t BUF47M:1; - vuint32_t BUF46M:1; - vuint32_t BUF45M:1; - vuint32_t BUF44M:1; - vuint32_t BUF43M:1; - vuint32_t BUF42M:1; - vuint32_t BUF41M:1; - vuint32_t BUF40M:1; - vuint32_t BUF39M:1; - vuint32_t BUF38M:1; - vuint32_t BUF37M:1; - vuint32_t BUF36M:1; - vuint32_t BUF35M:1; - vuint32_t BUF34M:1; - vuint32_t BUF33M:1; - vuint32_t BUF32M:1; - } B; /* Interruput Masks Register */ - } IMRH; /* IMASK2 */ - - union { - vuint32_t R; - struct { - vuint32_t BUF31M:1; - vuint32_t BUF30M:1; - vuint32_t BUF29M:1; - vuint32_t BUF28M:1; - vuint32_t BUF27M:1; - vuint32_t BUF26M:1; - vuint32_t BUF25M:1; - vuint32_t BUF24M:1; - vuint32_t BUF23M:1; - vuint32_t BUF22M:1; - vuint32_t BUF21M:1; - vuint32_t BUF20M:1; - vuint32_t BUF19M:1; - vuint32_t BUF18M:1; - vuint32_t BUF17M:1; - vuint32_t BUF16M:1; - vuint32_t BUF15M:1; - vuint32_t BUF14M:1; - vuint32_t BUF13M:1; - vuint32_t BUF12M:1; - vuint32_t BUF11M:1; - vuint32_t BUF10M:1; - vuint32_t BUF09M:1; - vuint32_t BUF08M:1; - vuint32_t BUF07M:1; - vuint32_t BUF06M:1; - vuint32_t BUF05M:1; - vuint32_t BUF04M:1; - vuint32_t BUF03M:1; - vuint32_t BUF02M:1; - vuint32_t BUF01M:1; - vuint32_t BUF00M:1; - } B; /* Interruput Masks Register */ - } IMRL; /* IMASK1 */ - - union { - vuint32_t R; - struct { - vuint32_t BUF63I:1; - vuint32_t BUF62I:1; - vuint32_t BUF61I:1; - vuint32_t BUF60I:1; - vuint32_t BUF59I:1; - vuint32_t BUF58I:1; - vuint32_t BUF57I:1; - vuint32_t BUF56I:1; - vuint32_t BUF55I:1; - vuint32_t BUF54I:1; - vuint32_t BUF53I:1; - vuint32_t BUF52I:1; - vuint32_t BUF51I:1; - vuint32_t BUF50I:1; - vuint32_t BUF49I:1; - vuint32_t BUF48I:1; - vuint32_t BUF47I:1; - vuint32_t BUF46I:1; - vuint32_t BUF45I:1; - vuint32_t BUF44I:1; - vuint32_t BUF43I:1; - vuint32_t BUF42I:1; - vuint32_t BUF41I:1; - vuint32_t BUF40I:1; - vuint32_t BUF39I:1; - vuint32_t BUF38I:1; - vuint32_t BUF37I:1; - vuint32_t BUF36I:1; - vuint32_t BUF35I:1; - vuint32_t BUF34I:1; - vuint32_t BUF33I:1; - vuint32_t BUF32I:1; - } B; /* Interruput Flag Register */ - } IFRH; /* IFLAG2 */ - - union { - vuint32_t R; - struct { - vuint32_t BUF31I:1; - vuint32_t BUF30I:1; - vuint32_t BUF29I:1; - vuint32_t BUF28I:1; - vuint32_t BUF27I:1; - vuint32_t BUF26I:1; - vuint32_t BUF25I:1; - vuint32_t BUF24I:1; - vuint32_t BUF23I:1; - vuint32_t BUF22I:1; - vuint32_t BUF21I:1; - vuint32_t BUF20I:1; - vuint32_t BUF19I:1; - vuint32_t BUF18I:1; - vuint32_t BUF17I:1; - vuint32_t BUF16I:1; - vuint32_t BUF15I:1; - vuint32_t BUF14I:1; - vuint32_t BUF13I:1; - vuint32_t BUF12I:1; - vuint32_t BUF11I:1; - vuint32_t BUF10I:1; - vuint32_t BUF09I:1; - vuint32_t BUF08I:1; - vuint32_t BUF07I:1; - vuint32_t BUF06I:1; - vuint32_t BUF05I:1; - vuint32_t BUF04I:1; - vuint32_t BUF03I:1; - vuint32_t BUF02I:1; - vuint32_t BUF01I:1; - vuint32_t BUF00I:1; - } B; /* Interruput Flag Register */ - } IFRL; /* IFLAG1 */ - - uint32_t flexcan2_reserved2[19]; - -/****************************************************************************/ -/* Use either Standard Buffer Structure OR RX FIFO and Buffer Structure */ -/****************************************************************************/ - /* Standard Buffer Structure */ - struct FLEXCAN_BUF_t BUF[64]; - - /* RX FIFO and Buffer Structure *//* New options in MPC563xM */ - /*struct FLEXCAN_RXFIFO_t RXFIFO; */ - /*struct FLEXCAN_BUF_t BUF[56]; */ -/****************************************************************************/ - - uint32_t FLEXCAN_reserved3[256]; /* {0x0880-0x0480}/0x4 = 0x100 *//* (New in MPC563xM) Address Base + 0x0034 */ - - union { - vuint32_t R; - struct { - vuint32_t MI:32; - } B; /* RX Individual Mask Registers */ - } RXIMR[64]; /* (New in MPC563xM) Address Base + 0x0880 */ - - }; /* end of FLEXCAN_tag */ -/****************************************************************************/ -/* MODULE : Decimation Filter (DECFIL) */ -/****************************************************************************/ - struct DECFIL_tag { - union { - vuint32_t R; - struct { - vuint32_t MDIS:1; - vuint32_t FREN:1; - vuint32_t:1; - vuint32_t FRZ:1; - vuint32_t SRES:1; - vuint32_t:2; /* CASCD not supported in MPC563xM */ - vuint32_t IDEN:1; - vuint32_t ODEN:1; - vuint32_t ERREN:1; - vuint32_t:1; - vuint32_t FTYPE:2; - vuint32_t:1; - vuint32_t SCAL:2; - vuint32_t:1; - vuint32_t SAT:1; - vuint32_t ISEL:1; - vuint32_t:1; /* MIXM does not appear to be implemented on the MPC563xM */ - vuint32_t DEC_RATE:4; - vuint32_t:1; /* SDIE not supported in MPC563xM */ - vuint32_t DSEL:1; - vuint32_t IBIE:1; - vuint32_t OBIE:1; - vuint32_t EDME:1; - vuint32_t TORE:1; - vuint32_t TMODE:2; /* the LSB of TMODE is always 0 on the MPC563xM */ - } B; - } MCR; /* Configuration Register DECFILTER_MCR @baseaddress + 0x00 */ - - union { - vuint32_t R; - struct { - vuint32_t BSY:1; - vuint32_t:1; - vuint32_t DEC_COUNTER:4; - vuint32_t IDFC:1; - vuint32_t ODFC:1; - vuint32_t SDFC:1; /* SDFC not supported in MPC563xM */ - vuint32_t IBIC:1; - vuint32_t OBIC:1; - vuint32_t SVRC:1; /* SVRC not supported in MPC563xM */ - vuint32_t DIVRC:1; - vuint32_t OVFC:1; - vuint32_t OVRC:1; - vuint32_t IVRC:1; - vuint32_t:6; - vuint32_t IDF:1; - vuint32_t ODF:1; - vuint32_t SDF:1; /* SDF not supported in MPC563xM */ - vuint32_t IBIF:1; - vuint32_t OBIF:1; - vuint32_t SVR:1; /* SVR not supported in MPC563xM */ - vuint32_t DIVR:1; - vuint32_t OVF:1; - vuint32_t OVR:1; - vuint32_t IVR:1; - } B; - } MSR; /* Status Register DECFILTER_MSR @baseaddress + 0x04 */ - - /* Module Extended Config.Register - not siupported on the MPC563xM DECFILTER_MXCR @baseaddress + 0x08 */ - - uint32_t decfil_reserved1[2]; - - union { - vuint32_t R; - struct { - vuint32_t:4; - vuint32_t INTAG:4; - vuint32_t:6; - vuint32_t PREFILL:1; - vuint32_t FLUSH:1; - vuint32_t INPBUF:16; - } B; - } IB; /* Interface Input Buffer DECFILTER_IB @baseaddress + 0x10 */ - - union { - vuint32_t R; - struct { - vuint32_t:12; - vuint32_t OUTTAG:4; - vuint32_t OUTBUF:16; - } B; - } OB; /* Interface Output Buffer DECFILTER_OB @baseaddress + 0x14 */ - - uint32_t decfil_reserved2[2]; - - union { - vuint32_t R; - struct { - vuint32_t:8; - vuint32_t COEF:24; - } B; - } COEF[9]; /* Filter Coefficient Registers DECFILTER_COEFx @baseaddress + 0x20 - 0x40 */ - - uint32_t decfil_reserved3[13]; - - union { - vuint32_t R; - struct { - vuint32_t:8; - vuint32_t TAP:24; - } B; - } TAP[8]; /* Filter TAP Registers DECFILTER_TAPx @baseaddress + 0x78 - 0x94 */ - - uint32_t decfil_reserved4[14]; - - /* 0x0D0 */ - union { - vuint16_t R; - struct { - vuint32_t:16; - vuint32_t SAMP_DATA:16; - } B; - } EDID; /* Filter EDID Registers DECFILTER_EDID @baseaddress + 0xD0 */ - - uint32_t decfil_reserved5[3]; - - /* 0x0E0 */ - uint32_t decfil_reserved6; - /* Filter FINTVAL Registers - Not supported on MPC563xM DECFILTER_FINTVAL @baseaddress + 0xE0 */ - - /* 0x0E4 */ - uint32_t decfil_reserved7; - /* Filter FINTCNT Registers - Not supported on MPC563xM DECFILTER_FINTCNT @baseaddress + 0xE4 */ - - /* 0x0E8 */ - uint32_t decfil_reserved8; - /* Filter CINTVAL Registers - Not supported on MPC563xM DECFILTER_CINTVAL @baseaddress + 0xE8 */ - - /* 0x0EC */ - uint32_t decfil_reserved9; - /* Filter CINTCNT Registers - Not supported on MPC563xM DECFILTER_CINTCNT @baseaddress + 0xEC */ - - }; -/****************************************************************************/ -/* MODULE : Periodic Interval Timer (PIT) */ -/****************************************************************************/ - struct PIT_tag { - - union { - vuint32_t R; - struct { - vuint32_t:29; - vuint32_t MDIS_RTI:1; - vuint32_t MDIS:1; - vuint32_t FRZ:1; - } B; - } PITMCR; /* PIT Module Control Register */ - - uint32_t pit_reserved1[59]; - - struct { - union { - vuint32_t R; /* TSVn */ - } LDVAL; /* Timer Load Value Register */ - - union { - vuint32_t R; /* TVLn */ - } CVAL; /* Current Timer Value Register */ - - union { - vuint32_t R; - struct { - vuint32_t:30; - vuint32_t TIE:1; - vuint32_t TEN:1; - } B; - } TCTRL; /* Timer Control Register */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t TIF:1; - } B; - } TFLG; /* Timer Flag Register */ - } RTI; /* RTI Channel */ - - struct { - union { - vuint32_t R; - } LDVAL; /* Timer Load Value Register */ - - union { - vuint32_t R; - } CVAL; /* Current Timer Value Register */ - - union { - vuint32_t R; - struct { - vuint32_t:30; - vuint32_t TIE:1; - vuint32_t TEN:1; - } B; - } TCTRL; /* Timer Control Register */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t TIF:1; - } B; - } TFLG; /* Timer Flag Register */ - } TIMER[4]; /* Timer Channels */ - - }; -/****************************************************************************/ -/* MODULE : System Timer Module (STM) */ -/****************************************************************************/ - struct STM_tag { - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t CPS:8; - vuint32_t:6; - vuint32_t FRZ:1; - vuint32_t TEN:1; - } B; - } CR; /* STM Control Register STM_CR (new in MPC563xM) Offset 0x0000 */ - - union { - vuint32_t R; - } CNT; /* STM Count Register STM_CNT (new in MPC563xM) Offset Offset 0x0004 */ - - uint32_t stm_reserved1[2]; /* Reserved (new in MPC563xM) Offset Offset 0x0008 */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CEN:1; - } B; - } CCR0; /* STM Channel Control Register STM_CCR0 (new in MPC563xM) Offset 0x0010 */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CIF:1; - } B; - } CIR0; /* STM Channel Interrupt Register STM_CIR0 (new in MPC563xM) Offset 0x0014 */ - - union { - vuint32_t R; - } CMP0; /* STM Channel Compare Register STM_CMP0 (new in MPC563xM) Offset Offset 0x0018 */ - - uint32_t stm_reserved2; /* Reserved (new in MPC563xM) Offset Offset 0x001C */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CEN:1; - } B; - } CCR1; /* STM Channel Control Register STM_CCR1 (new in MPC563xM) Offset 0x0020 */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CIF:1; - } B; - } CIR1; /* STM Channel Interrupt Register STM_CIR1 (new in MPC563xM) Offset 0x0024 */ - - union { - vuint32_t R; - } CMP1; /* STM Channel Compare Register STM_CMP1 (new in MPC563xM) Offset Offset 0x0028 */ - - uint32_t stm_reserved3; /* Reserved (new in MPC563xM) Offset Offset 0x002C */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CEN:1; - } B; - } CCR2; /* STM Channel Control Register STM_CCR2 (new in MPC563xM) Offset 0x0030 */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CIF:1; - } B; - } CIR2; /* STM Channel Interrupt Register STM_CIR2 (new in MPC563xM) Offset 0x0034 */ - - union { - vuint32_t R; - } CMP2; /* STM Channel Compare Register STM_CMP2 (new in MPC563xM) Offset Offset 0x0038 */ - - uint32_t stm_reserved4; /* Reserved (new in MPC563xM) Offset Offset 0x003C */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CEN:1; - } B; - } CCR3; /* STM Channel Control Register STM_CCR3 (new in MPC563xM) Offset 0x0040 */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t CIF:1; - } B; - } CIR3; /* STM Channel Interrupt Register STM_CIR3 (new in MPC563xM) Offset 0x0044 */ - - union { - vuint32_t R; - } CMP3; /* STM Channel Compare Register STM_CMP3 (new in MPC563xM) Offset Offset 0x0048 */ - - uint32_t stm_reserved5; /* Reserved (new in MPC563xM) Offset Offset 0x004C */ - }; - -/****************************************************************************/ -/* MODULE : SWT */ -/****************************************************************************/ - - struct SWT_tag { - union { - vuint32_t R; - struct { - vuint32_t MAP0:1; - vuint32_t MAP1:1; - vuint32_t MAP2:1; - vuint32_t MAP3:1; - vuint32_t MAP4:1; - vuint32_t MAP5:1; - vuint32_t MAP6:1; - vuint32_t MAP7:1; - vuint32_t:14; - vuint32_t KEY:1; - vuint32_t RIA:1; - vuint32_t WND:1; - vuint32_t ITR:1; - vuint32_t HLK:1; - vuint32_t SLK:1; - vuint32_t CSL:1; - vuint32_t STP:1; - vuint32_t FRZ:1; - vuint32_t WEN:1; - } B; - } MCR; /*SWT_CR *//* Module Configuration Register */ - - union { - vuint32_t R; - struct { - vuint32_t:31; - vuint32_t TIF:1; - } B; - } IR; /* Interrupt register SWT_IR */ - - union { - vuint32_t R; - struct { - vuint32_t WTO:32; - } B; - } TO; /* Timeout register SWT_TO */ - - union { - vuint32_t R; - struct { - vuint32_t WST:32; - - } B; - } WN; /* Window register SWT_WN */ - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t WSC:16; - } B; - } SR; /* Service register SWT_SR */ - - union { - vuint32_t R; - struct { - vuint32_t CNT:32; - } B; - } CO; /* Counter output register SWT_CO */ - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t SK:16; - } B; - } SK; /* Service key register SWT_SK */ - }; -/****************************************************************************/ -/* MODULE : Power Management Controller (PMC) */ -/****************************************************************************/ - struct PMC_tag { - union { - vuint32_t R; - struct { - vuint32_t LVRER:1; /* LVIRR */ - vuint32_t LVREH:1; /* LVIHR */ - vuint32_t LVRE50:1; /* LVI5R */ - vuint32_t LVRE33:1; /* LVI3R */ - vuint32_t LVREC:1; /* LVI1R */ - vuint32_t:3; - vuint32_t LVIER:1; /* LVIRE */ - vuint32_t LVIEH:1; /* LVIHE */ - vuint32_t LVIE50:1; /* LVI5E */ - vuint32_t LVIE33:1; /* LVI3E */ - vuint32_t LVIC:1; /* LVI1E */ - vuint32_t:2; - vuint32_t TLK:1; - vuint32_t:16; - } B; - } MCR; /* Module Configuration register CFGR */ - - union { - vuint32_t R; - struct { - vuint32_t:12; - vuint32_t LVDREGTRIM:4; /* LVI50TRIM */ - vuint32_t VDD33TRIM:4; /* BV33TRIM */ - vuint32_t LVD33TRIM:4; /* LVI33TRIM */ - vuint32_t VDDCTRIM:4; /* V12TRIM */ - vuint32_t LVDCTRIM:4; /* LVI33TRIM */ - } B; - } TRIMR; /* Trimming register */ - - union { - vuint32_t R; - struct { - vuint32_t:5; - vuint32_t LVFVSTBY:1; - vuint32_t BGRDY:1; /* BGS1 */ - vuint32_t BGTS:1; /* BGS2 */ - vuint32_t:5; - vuint32_t LVFCSTBY:1; - vuint32_t:1; - vuint32_t V33DIS:1; /* 3.3V Regulator Disable V33S */ - vuint32_t LVFCR:1; /* Clear LVFR LVIRC */ - vuint32_t LVFCH:1; /* Clear LVFH LVIHC */ - vuint32_t LVFC50:1; /* Clear LVF5 LVI5 */ - vuint32_t LVFC33:1; /* Clear LVF3 LVI3 */ - vuint32_t LVFCC:1; /* Clear LVFC LVI1 */ - vuint32_t:3; - vuint32_t LVFR:1; /* Low Voltage Flag Reset Supply LVIRF */ - vuint32_t LVFH:1; /* Low Voltage Flag VDDEH Supply LVIHF */ - vuint32_t LVF50:1; /* Low Voltage Flag 5V Supply LVI5F */ - vuint32_t LVF33:1; /* Low Voltage Flag 3.3V Supply LVI3F */ - vuint32_t LVFC:1; /* Low Voltage Flag Core (1.2V) LVI1F */ - vuint32_t:3; - - } B; - } SR; /* status register */ - }; -/****************************************************************************/ -/* MODULE : TSENS (Temperature Sensor) */ -/****************************************************************************/ - - struct TSENS_tag { - - union { - vuint32_t R; - struct { - vuint32_t TSCV2:16; - vuint32_t TSCV1:16; - } B; - } TCCR0; /* Temperature Sensor Calibration B @baseaddress + 0x00 */ - - union { - vuint32_t R; - struct { - vuint32_t:16; - vuint32_t TSCV3:16; - } B; - } TCCR1; /* Temperature Sensor Calibration A @baseaddress + 0x04 */ - - uint32_t TSENS_reserved0008[16382]; /* 0x0008-0xFFFF */ - - }; - -/* Define memories */ -/* Comments need to be moved for different memory sizes */ - -#define SRAM_START 0x40000000 - /*#define SRAM_SIZE 0xC000 48K SRAM */ - /*#define SRAM_SIZE 0x10000 64K SRAM */ -#define SRAM_SIZE 0x17800 /* 94K SRAM */ - /*#define SRAM_END 0x4000BFFF 48K SRAM */ - /*#define SRAM_END 0x4000FFFF 64K SRAM */ -#define SRAM_END 0x400177FF /* 94K SRAM */ - -#define FLASH_START 0x0 - /*#define FLASH_SIZE 0x100000 1M Flash */ -#define FLASH_SIZE 0x180000 /* 1.5M Flash */ - /*#define FLASH_END 0xFFFFF 1M Flash */ -#define FLASH_END 0x17FFFF /* 1.5M Flash */ - -/* Shadow Flash start and end address */ -#define FLASH_SHADOW_START 0x00FFC000 -#define FLASH_SHADOW_SIZE 0x4000 -#define FLASH_SHADOW_END 0x00FFFFFF - -/* Define instances of modules */ -#define FMPLL (*( volatile struct FMPLL_tag *) 0xC3F80000) -#define EBI (*( volatile struct EBI_tag *) 0xC3F84000) -#define CFLASH0 (*( volatile struct FLASH_tag *) 0xC3F88000) -#define CFLASH1 (*( volatile struct FLASH_tag *) 0xC3FB0000) -#define CFLASH2 (*( volatile struct FLASH_tag *) 0xC3FB4000) -#define SIU (*( volatile struct SIU_tag *) 0xC3F90000) - -#define EMIOS (*( volatile struct EMIOS_tag *) 0xC3FA0000) -#define PMC (*( volatile struct PMC_tag *) 0xC3FBC000) -#define ETPU (*( volatile struct ETPU_tag *) 0xC3FC0000) -#define ETPU_DATA_RAM (*( uint32_t *) 0xC3FC8000) -#define ETPU_DATA_RAM_EXT (*( uint32_t *) 0xC3FCC000) -#define ETPU_DATA_RAM_END 0xC3FC8BFC -#define CODE_RAM (*( uint32_t *) 0xC3FD0000) -#define ETPU_CODE_RAM (*( uint32_t *) 0xC3FD0000) -#define PIT (*( volatile struct PIT_tag *) 0xC3FF0000) - -#define XBAR (*( volatile struct XBAR_tag *) 0xFFF04000) -#define SWT (*( volatile struct SWT_tag *) 0xFFF38000) -#define STM (*( volatile struct STM_tag *) 0xFFF3C000) -#define ECSM (*( volatile struct ECSM_tag *) 0xFFF40000) -#define EDMA (*( volatile struct EDMA_tag *) 0xFFF44000) -#define INTC (*( volatile struct INTC_tag *) 0xFFF48000) - -#define EQADC (*( volatile struct EQADC_tag *) 0xFFF80000) -#define DECFIL (*( volatile struct DECFIL_tag *) 0xFFF88000) - -#define DSPI_B (*( volatile struct DSPI_tag *) 0xFFF94000) -#define DSPI_C (*( volatile struct DSPI_tag *) 0xFFF98000) - -#define ESCI_A (*( volatile struct ESCI_tag *) 0xFFFB0000) -#define ESCI_A_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB0006) -#define ESCI_B (*( volatile struct ESCI_tag *) 0xFFFB4000) -#define ESCI_B_12_13 (*( volatile struct ESCI_12_13_bit_tag *) 0xFFFB4006) - -#define CAN_A (*( volatile struct FLEXCAN2_tag *) 0xFFFC0000) -#define CAN_C (*( volatile struct FLEXCAN2_tag *) 0xFFFC8000) - -#define TSENS (*( volatile struct TSENS_tag *) 0xFFFEC000) - -#ifdef __MWERKS__ -#pragma pop -#endif /* - */ - -#ifdef __cplusplus -} -#endif /* - */ - -#endif /* ifdef _MPC563M_H */ -/********************************************************************* - * - * Copyright: - * Freescale Semiconductor, INC. All Rights Reserved. - * You are hereby granted a copyright license to use, modify, and - * distribute the SOFTWARE so long as this entire notice is - * retained without alteration in any modified and/or redistributed - * versions, and that such modified versions are clearly identified - * as such. No licenses are granted by implication, estoppel or - * otherwise under any patents or trademarks of Freescale - * Semiconductor, Inc. This software is provided on an "AS IS" - * basis and without warranty. - * - * To the maximum extent permitted by applicable law, Freescale - * Semiconductor DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, - * INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A - * PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH - * REGARD TO THE SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) - * AND ANY ACCOMPANYING WRITTEN MATERIALS. - * - * To the maximum extent permitted by applicable law, IN NO EVENT - * SHALL Freescale Semiconductor BE LIABLE FOR ANY DAMAGES WHATSOEVER - * (INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, - * BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER - * PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. - * - * Freescale Semiconductor assumes no responsibility for the - * maintenance and support of this software - * - ********************************************************************/ - diff --git a/os/hal/platforms/SPC56x/platform.dox b/os/hal/platforms/SPC56x/platform.dox deleted file mode 100644 index 9b8eec901..000000000 --- a/os/hal/platforms/SPC56x/platform.dox +++ /dev/null @@ -1,70 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @defgroup SPC563 SPC563Mx Drivers - * @details This section describes all the supported drivers on the - * SPC563Mx/MPC563xM platform and the implementation details - * of the single drivers. - * - * @ingroup platforms - */ - -/** - * @defgroup SPC563_HAL SPC563Mx Initialization Support - * @details The SPC563Mx/MPC563xM HAL support is responsible for system - * initialization. - * - * @section spc563_hal_1 Supported HW resources - * - FMPLL. - * - INTC. - * - XBAR. - * - CFLASH0. - * . - * @section spc563_hal_2 SPC563Mx HAL driver implementation features - * - FMPLL startup and stabilization. - * - Clock tree initialization. - * - Clock source selection. - * - Flash wait states initialization based on the selected clock options. - * - SYSTICK initialization based on current clock and kernel required rate. - * - DMA support initialization. - * . - * @ingroup SPC563 - */ - -/** - * @defgroup SPC563_SERIAL SPC563Mx Serial Support - * @details The SPC563Mx/MPC563xM Serial driver uses the ESCI peripherals - * in a buffered, interrupt driven, implementation. - * - * @section spc563_serial_1 Supported HW resources - * The serial driver can support any of the following hardware resources: - * - ESCIA. - * - ESCIB. - * . - * @section spc563_serial_2 SPC563Mx Serial driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Each ESCI can be independently enabled and programmed. Unused - * peripherals are left in low power mode. - * - Fully interrupt driven. - * - Programmable priority levels for each ESCI. - * . - * @ingroup SPC563 - */ diff --git a/os/hal/platforms/SPC56x/platform.mk b/os/hal/platforms/SPC56x/platform.mk deleted file mode 100644 index 6069e7dc6..000000000 --- a/os/hal/platforms/SPC56x/platform.mk +++ /dev/null @@ -1,6 +0,0 @@ -# List of all the SPC56x platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC56x/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/SPC56x/serial_lld.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC56x diff --git a/os/hal/platforms/SPC56x/serial_lld.c b/os/hal/platforms/SPC56x/serial_lld.c deleted file mode 100644 index e562b6c2d..000000000 --- a/os/hal/platforms/SPC56x/serial_lld.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file SPC56x/serial_lld.c - * @brief SPC563 low level serial driver code. - * - * @addtogroup SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief eSCI-A serial driver identifier. - */ -#if USE_SPC563_ESCIA || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/** - * @brief eSCI-B serial driver identifier. - */ -#if USE_SPC563_ESCIB || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief Driver default configuration. - */ -static const SerialConfig default_config = { - SERIAL_DEFAULT_BITRATE, - SD_MODE_NORMAL | SD_MODE_PARITY_NONE -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief eSCI initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration - */ -static void esci_init(SerialDriver *sdp, const SerialConfig *config) { - volatile struct ESCI_tag *escip = sdp->escip; - uint8_t mode = config->sc_mode; - - escip->CR2.R = 0; /* MDIS off. */ - escip->CR1.R = 0; - escip->LCR.R = 0; - escip->CR1.B.SBR = SPC563_SYSCLK / (16 * config->sc_speed); - if (mode & SD_MODE_LOOPBACK) - escip->CR1.B.LOOPS = 1; - switch (mode & SD_MODE_PARITY) { - case SD_MODE_PARITY_ODD: - escip->CR1.B.PT = 1; - case SD_MODE_PARITY_EVEN: - escip->CR1.B.PE = 1; - escip->CR1.B.M = 1; /* Makes it 8 bits data + 1 bit parity. */ - default: - ; - } - escip->LPR.R = 0; - escip->CR1.R |= 0x0000002C; /* RIE, TE, RE to 1. */ - escip->CR2.R |= 0x000F; /* ORIE, NFIE, FEIE, PFIE to 1. */ -} - -/** - * @brief eSCI de-initialization. - * @details This function must be invoked with interrupts disabled. - * - * @param[in] escip pointer to an eSCI I/O block - */ -static void esci_deinit(volatile struct ESCI_tag *escip) { - - escip->LPR.R = 0; - escip->SR.R = 0xFFFFFFFF; - escip->CR1.R = 0; - escip->CR2.R = 0x8000; /* MDIS on. */ -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] sr eSCI SR register value - */ -static void set_error(SerialDriver *sdp, uint32_t sr) { - flagsmask_t sts = 0; - - if (sr & 0x08000000) - sts |= SD_OVERRUN_ERROR; - if (sr & 0x04000000) - sts |= SD_NOISE_ERROR; - if (sr & 0x02000000) - sts |= SD_FRAMING_ERROR; - if (sr & 0x01000000) - sts |= SD_PARITY_ERROR; -/* if (sr & 0x00000000) - sts |= SD_BREAK_DETECTED;*/ - chSysLockFromIsr(); - chnAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -/** - * @brief Common IRQ handler. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -static void serve_interrupt(SerialDriver *sdp) { - volatile struct ESCI_tag *escip = sdp->escip; - - uint32_t sr = escip->SR.R; - escip->SR.R = 0x3FFFFFFF; /* Does not clear TDRE | TC.*/ - if (sr & 0x0F000000) /* OR | NF | FE | PF. */ - set_error(sdp, sr); - if (sr & 0x20000000) { /* RDRF. */ - chSysLockFromIsr(); - sdIncomingDataI(sdp, escip->DR.B.D); - chSysUnlockFromIsr(); - } - if (escip->CR1.B.TIE && (sr & 0x80000000)) { /* TDRE. */ - msg_t b; - chSysLockFromIsr(); - b = chOQGetI(&sdp->oqueue); - if (b < Q_OK) { - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - escip->CR1.B.TIE = 0; - } - else { - ESCI_A.SR.B.TDRE = 1; - escip->DR.R = (uint16_t)b; - } - chSysUnlockFromIsr(); - } -} - -#if USE_SPC563_ESCIA || defined(__DOXYGEN__) -static void notify1(GenericQueue *qp) { - - (void)qp; - if (ESCI_A.SR.B.TDRE) { - msg_t b = sdRequestDataI(&SD1); - if (b != Q_EMPTY) { - ESCI_A.SR.B.TDRE = 1; - ESCI_A.CR1.B.TIE = 1; - ESCI_A.DR.R = (uint16_t)b; - } - } -} -#endif - -#if USE_SPC563_ESCIB || defined(__DOXYGEN__) -static void notify2(GenericQueue *qp) { - - (void)qp; - if (ESCI_B.SR.B.TDRE) { - msg_t b = sdRequestDataI(&SD2); - if (b != Q_EMPTY) { - ESCI_B.SR.B.TDRE = 1; - ESCI_B.CR1.B.TIE = 1; - ESCI_B.DR.R = (uint16_t)b; - } - } -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if USE_SPC563_ESCIA || defined(__DOXYGEN__) -/** - * @brief eSCI-A interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(vector146) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD1); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if USE_SPC563_ESCIB || defined(__DOXYGEN__) -/** - * @brief eSCI-B interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(vector149) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD2); - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - * - * @notapi - */ -void sd_lld_init(void) { - -#if USE_SPC563_ESCIA - sdObjectInit(&SD1, NULL, notify1); - SD1.escip = &ESCI_A; - ESCI_A.CR2.R = 0x8000; /* MDIS ON. */ - INTC.PSR[146].R = SPC563_ESCIA_PRIORITY; -#endif - -#if USE_SPC563_ESCIB - sdObjectInit(&SD2, NULL, notify2); - SD2.escip = &ESCI_B; - ESCI_B.CR2.R = 0x8000; /* MDIS ON. */ - INTC.PSR[149].R = SPC563_ESCIB_PRIORITY; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - * - * @notapi - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - esci_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * - * @param[in] sdp pointer to a @p SerialDriver object - * - * @notapi - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) - esci_deinit(sdp->escip); -} - -#endif /* HAL_USE_SERIAL */ - -/** @} */ diff --git a/os/hal/platforms/SPC56x/serial_lld.h b/os/hal/platforms/SPC56x/serial_lld.h deleted file mode 100644 index b02b160b1..000000000 --- a/os/hal/platforms/SPC56x/serial_lld.h +++ /dev/null @@ -1,157 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file SPC56x/serial_lld.h - * @brief SPC563 low level serial driver header. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define SD_MODE_PARITY_MASK 0x03 /**< @brief Parity field mask. */ -#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ -#define SD_MODE_PARITY_EVEN 0x01 /**< @brief Even parity. */ -#define SD_MODE_PARITY_ODD 0x02 /**< @brief Odd parity. */ - -#define SD_MODE_NORMAL 0x00 /**< @brief Normal operations. */ -#define SD_MODE_LOOPBACK 0x80 /**< @brief Internal loopback. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief eSCI-A driver enable switch. - * @details If set to @p TRUE the support for eSCI-A is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_SPC563_ESCIA) || defined(__DOXYGEN__) -#define USE_SPC563_ESCIA TRUE -#endif - -/** - * @brief eSCI-B driver enable switch. - * @details If set to @p TRUE the support for eSCI-B is included. - * @note The default is @p TRUE. - */ -#if !defined(USE_SPC563_ESCIB) || defined(__DOXYGEN__) -#define USE_SPC563_ESCIB TRUE -#endif - -/** - * @brief eSCI-A interrupt priority level setting. - */ -#if !defined(SPC563_ESCIA_PRIORITY) || defined(__DOXYGEN__) -#define SPC563_ESCIA_PRIORITY 8 -#endif - -/** - * @brief eSCI-B interrupt priority level setting. - */ -#if !defined(SPC563_ESCIB_PRIORITY) || defined(__DOXYGEN__) -#define SPC563_ESCIB_PRIORITY 8 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Generic Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t sc_speed; - /** - * @brief Mode flags. - */ - uint8_t sc_mode; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the volatile eSCI registers block.*/ \ - volatile struct ESCI_tag *escip; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if USE_SPC563_ESCIA && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if USE_SPC563_ESCIB && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/SPC56x/typedefs.h b/os/hal/platforms/SPC56x/typedefs.h deleted file mode 100644 index 5947e0f37..000000000 --- a/os/hal/platforms/SPC56x/typedefs.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -/** - * @file SPC56x/typedefs.h - * @brief Dummy typedefs file. - */ - -#ifndef _TYPEDEFS_H_ -#define _TYPEDEFS_H_ - -#include "chtypes.h" - -#endif /* _TYPEDEFS_H_ */ diff --git a/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c b/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c new file mode 100644 index 000000000..ca90d0d56 --- /dev/null +++ b/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.c @@ -0,0 +1,288 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file SPC5xx/ESCI_v1/serial_lld.c + * @brief SPC5xx low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief eSCI-A serial driver identifier. + */ +#if SPC_USE_ESCIA || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief eSCI-B serial driver identifier. + */ +#if SPC_USE_ESCIB || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + SD_MODE_NORMAL | SD_MODE_PARITY_NONE +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief eSCI initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration + */ +static void esci_init(SerialDriver *sdp, const SerialConfig *config) { + volatile struct ESCI_tag *escip = sdp->escip; + uint8_t mode = config->sc_mode; + + escip->CR2.R = 0; /* MDIS off. */ + escip->CR1.R = 0; + escip->LCR.R = 0; + escip->CR1.B.SBR = SPC_SYSCLK / (16 * config->sc_speed); + if (mode & SD_MODE_LOOPBACK) + escip->CR1.B.LOOPS = 1; + switch (mode & SD_MODE_PARITY) { + case SD_MODE_PARITY_ODD: + escip->CR1.B.PT = 1; + case SD_MODE_PARITY_EVEN: + escip->CR1.B.PE = 1; + escip->CR1.B.M = 1; /* Makes it 8 bits data + 1 bit parity. */ + default: + ; + } + escip->LPR.R = 0; + escip->CR1.R |= 0x0000002C; /* RIE, TE, RE to 1. */ + escip->CR2.R |= 0x000F; /* ORIE, NFIE, FEIE, PFIE to 1. */ +} + +/** + * @brief eSCI de-initialization. + * @details This function must be invoked with interrupts disabled. + * + * @param[in] escip pointer to an eSCI I/O block + */ +static void esci_deinit(volatile struct ESCI_tag *escip) { + + escip->LPR.R = 0; + escip->SR.R = 0xFFFFFFFF; + escip->CR1.R = 0; + escip->CR2.R = 0x8000; /* MDIS on. */ +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] sr eSCI SR register value + */ +static void set_error(SerialDriver *sdp, uint32_t sr) { + flagsmask_t sts = 0; + + if (sr & 0x08000000) + sts |= SD_OVERRUN_ERROR; + if (sr & 0x04000000) + sts |= SD_NOISE_ERROR; + if (sr & 0x02000000) + sts |= SD_FRAMING_ERROR; + if (sr & 0x01000000) + sts |= SD_PARITY_ERROR; +/* if (sr & 0x00000000) + sts |= SD_BREAK_DETECTED;*/ + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +static void serve_interrupt(SerialDriver *sdp) { + volatile struct ESCI_tag *escip = sdp->escip; + + uint32_t sr = escip->SR.R; + escip->SR.R = 0x3FFFFFFF; /* Does not clear TDRE | TC.*/ + if (sr & 0x0F000000) /* OR | NF | FE | PF. */ + set_error(sdp, sr); + if (sr & 0x20000000) { /* RDRF. */ + chSysLockFromIsr(); + sdIncomingDataI(sdp, escip->DR.B.D); + chSysUnlockFromIsr(); + } + if (escip->CR1.B.TIE && (sr & 0x80000000)) { /* TDRE. */ + msg_t b; + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + escip->CR1.B.TIE = 0; + } + else { + ESCI_A.SR.B.TDRE = 1; + escip->DR.R = (uint16_t)b; + } + chSysUnlockFromIsr(); + } +} + +#if SPC_USE_ESCIA || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + if (ESCI_A.SR.B.TDRE) { + msg_t b = sdRequestDataI(&SD1); + if (b != Q_EMPTY) { + ESCI_A.SR.B.TDRE = 1; + ESCI_A.CR1.B.TIE = 1; + ESCI_A.DR.R = (uint16_t)b; + } + } +} +#endif + +#if SPC_USE_ESCIB || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + if (ESCI_B.SR.B.TDRE) { + msg_t b = sdRequestDataI(&SD2); + if (b != Q_EMPTY) { + ESCI_B.SR.B.TDRE = 1; + ESCI_B.CR1.B.TIE = 1; + ESCI_B.DR.R = (uint16_t)b; + } + } +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if SPC_USE_ESCIA || defined(__DOXYGEN__) +/** + * @brief eSCI-A interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(vector146) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if SPC_USE_ESCIB || defined(__DOXYGEN__) +/** + * @brief eSCI-B interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(vector149) { + + CH_IRQ_PROLOGUE(); + + serve_interrupt(&SD2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if SPC_USE_ESCIA + sdObjectInit(&SD1, NULL, notify1); + SD1.escip = &ESCI_A; + ESCI_A.CR2.R = 0x8000; /* MDIS ON. */ + INTC.PSR[146].R = SPC_ESCIA_PRIORITY; +#endif + +#if SPC_USE_ESCIB + sdObjectInit(&SD2, NULL, notify2); + SD2.escip = &ESCI_B; + ESCI_B.CR2.R = 0x8000; /* MDIS ON. */ + INTC.PSR[149].R = SPC_ESCIB_PRIORITY; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + esci_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + + if (sdp->state == SD_READY) + esci_deinit(sdp->escip); +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h b/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h new file mode 100644 index 000000000..606344d9f --- /dev/null +++ b/os/hal/platforms/SPC5xx/ESCI_v1/serial_lld.h @@ -0,0 +1,156 @@ +/* + * Licensed under ST Liberty SW License Agreement V2, (the "License"); + * You may not use this file except in compliance with the License. + * You may obtain a copy of the License at: + * + * http://www.st.com/software_license_agreement_liberty_v2 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @file SPC5xx/ESCI_v1/serial_lld.c + * @brief SPC5xx low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Serial port modes + * @{ + */ +#define SD_MODE_PARITY_MASK 0x03 /**< @brief Parity field mask. */ +#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ +#define SD_MODE_PARITY_EVEN 0x01 /**< @brief Even parity. */ +#define SD_MODE_PARITY_ODD 0x02 /**< @brief Odd parity. */ + +#define SD_MODE_NORMAL 0x00 /**< @brief Normal operations. */ +#define SD_MODE_LOOPBACK 0x80 /**< @brief Internal loopback. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief eSCI-A driver enable switch. + * @details If set to @p TRUE the support for eSCI-A is included. + * @note The default is @p TRUE. + */ +#if !defined(SPC_USE_ESCIA) || defined(__DOXYGEN__) +#define SPC_USE_ESCIA TRUE +#endif + +/** + * @brief eSCI-B driver enable switch. + * @details If set to @p TRUE the support for eSCI-B is included. + * @note The default is @p TRUE. + */ +#if !defined(SPC_USE_ESCIB) || defined(__DOXYGEN__) +#define SPC_USE_ESCIB TRUE +#endif + +/** + * @brief eSCI-A interrupt priority level setting. + */ +#if !defined(SPC_ESCIA_PRIORITY) || defined(__DOXYGEN__) +#define SPC_ESCIA_PRIORITY 8 +#endif + +/** + * @brief eSCI-B interrupt priority level setting. + */ +#if !defined(SPC_ESCIB_PRIORITY) || defined(__DOXYGEN__) +#define SPC_ESCIB_PRIORITY 8 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Mode flags. + */ + uint8_t sc_mode; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the volatile eSCI registers block.*/ \ + volatile struct ESCI_tag *escip; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if SPC_USE_ESCIA && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if SPC_USE_ESCIB && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c index 4334c03d4..b666a65ae 100644 --- a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c +++ b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c @@ -13,7 +13,7 @@ */ /** - * @file SPC5xx/serial_lld.c + * @file SPC5xx/LINFlex_v1/serial_lld.c * @brief SPC5xx low level serial driver code. * * @addtogroup SERIAL diff --git a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h index 85dc1345b..0b1873f30 100644 --- a/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h +++ b/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.h @@ -13,7 +13,7 @@ */ /** - * @file SPC5xx/serial_lld.h + * @file SPC5xx/LINFlex_v1/serial_lld.h * @brief SPC5xx low level serial driver header. * * @addtogroup SERIAL diff --git a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c index a0aee25f5..8cd8b2bd3 100644 --- a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c +++ b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c @@ -13,7 +13,7 @@ */ /** - * @file SPC5xx/SIU_v1/pal_lld.c + * @file SPC5xx/SIUL_v1/pal_lld.c * @brief SPC5xx SIU/SIUL low level driver code. * * @addtogroup PAL diff --git a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h index e15bdf441..32b54d260 100644 --- a/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h +++ b/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.h @@ -13,7 +13,7 @@ */ /** - * @file SPC5xx/SIU_v1//pal_lld.h + * @file SPC5xx/SIUL_v1/pal_lld.h * @brief SPC5xx SIU/SIUL low level driver header. * * @addtogroup PAL -- cgit v1.2.3