From 17f9264b099705e80822be875a0dbc0658ad05fd Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 14 Jan 2012 13:30:33 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3810 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/hal_lld.c | 1 + os/hal/platforms/STM32F2xx/hal_lld.c | 18 ++++++++++-------- os/hal/platforms/STM32F4xx/hal_lld.c | 18 ++++++++++-------- os/hal/platforms/STM32L1xx/hal_lld.c | 22 ++++++++++++---------- 4 files changed, 33 insertions(+), 26 deletions(-) (limited to 'os/hal/platforms') diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c index 75afa0a84..d6de13b5c 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.c +++ b/os/hal/platforms/STM32F1xx/hal_lld.c @@ -53,6 +53,7 @@ static void hal_lld_backup_domain_init(void) { /* Reset BKP domain if different clock source selected.*/ if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){ + /* Backup domain reset.*/ RCC->BDCR = RCC_BDCR_BDRST; RCC->BDCR = 0; } diff --git a/os/hal/platforms/STM32F2xx/hal_lld.c b/os/hal/platforms/STM32F2xx/hal_lld.c index 8dc079187..050fa21d8 100644 --- a/os/hal/platforms/STM32F2xx/hal_lld.c +++ b/os/hal/platforms/STM32F2xx/hal_lld.c @@ -47,18 +47,20 @@ static void hal_lld_backup_domain_init(void) { /* Backup domain access enabled and left open.*/ - PWR->CR = PWR_CR_DBP; + PWR->CR |= PWR_CR_DBP; - /* If enabled then the LSE is started.*/ -#if STM32_LSE_ENABLED - if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) { + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){ /* Backup domain reset.*/ RCC->BDCR = RCC_BDCR_BDRST; RCC->BDCR = 0; - RCC->BDCR = RCC_BDCR_LSEON; - while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) - ; /* Waits until LSE is stable. */ } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED + RCC->BDCR |= RCC_BDCR_LSEON; + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ #endif #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK @@ -66,7 +68,7 @@ static void hal_lld_backup_domain_init(void) { initialization.*/ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { /* Selects clock source.*/ - RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL; + RCC->BDCR |= STM32_RTCSEL; /* RTC clock enabled.*/ RCC->BDCR |= RCC_BDCR_RTCEN; diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c index 3dd520c2c..9fbd34b08 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.c +++ b/os/hal/platforms/STM32F4xx/hal_lld.c @@ -47,18 +47,20 @@ static void hal_lld_backup_domain_init(void) { /* Backup domain access enabled and left open.*/ - PWR->CR = PWR_CR_DBP; + PWR->CR |= PWR_CR_DBP; - /* If enabled then the LSE is started.*/ -#if STM32_LSE_ENABLED - if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) { + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){ /* Backup domain reset.*/ RCC->BDCR = RCC_BDCR_BDRST; RCC->BDCR = 0; - RCC->BDCR = RCC_BDCR_LSEON; - while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) - ; /* Waits until LSE is stable. */ } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED + RCC->BDCR |= RCC_BDCR_LSEON; + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ #endif #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK @@ -66,7 +68,7 @@ static void hal_lld_backup_domain_init(void) { initialization.*/ if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { /* Selects clock source.*/ - RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL; + RCC->BDCR |= STM32_RTCSEL; /* RTC clock enabled.*/ RCC->BDCR |= RCC_BDCR_RTCEN; diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c index e4b21ede3..ecde8c0e8 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.c +++ b/os/hal/platforms/STM32L1xx/hal_lld.c @@ -47,18 +47,20 @@ static void hal_lld_backup_domain_init(void) { /* Backup domain access enabled and left open.*/ - PWR->CR = PWR_CR_DBP; + PWR->CR |= PWR_CR_DBP; - /* If enabled then the LSE is started.*/ -#if STM32_LSE_ENABLED - if ((RCC->CSR & RCC_CSR_LSEON) == 0) { + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->CSR & STM32_RTCSEL_MSK) != STM32_RTCSEL){ /* Backup domain reset.*/ RCC->CSR |= RCC_CSR_RTCRST; RCC->CSR &= ~RCC_CSR_RTCRST; - RCC->CSR |= RCC_CSR_LSEON; - while ((RCC->CSR & RCC_CSR_LSERDY) == 0) - ; /* Waits until LSE is stable. */ } + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED + RCC->CSR |= RCC_CSR_LSEON; + while ((RCC->CSR & RCC_CSR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ #endif #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK @@ -66,7 +68,7 @@ static void hal_lld_backup_domain_init(void) { initialization.*/ if ((RCC->CSR & RCC_CSR_RTCEN) == 0) { /* Selects clock source.*/ - RCC->CSR = (RCC->CSR & ~RCC_CSR_RTCSEL) | STM32_RTCSEL; + RCC->CSR |= STM32_RTCSEL; /* RTC clock enabled.*/ RCC->CSR |= RCC_CSR_RTCEN; @@ -200,7 +202,7 @@ void stm32_clock_init(void) { STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; RCC->CSR |= STM32_RTCSEL; - /* Flash setup and final clock selection. */ + /* Flash setup and final clock selection.*/ #if defined(STM32_FLASHBITS1) FLASH->ACR = STM32_FLASHBITS1; #endif @@ -210,7 +212,7 @@ void stm32_clock_init(void) { /* Switching to the configured clock source if it is different from MSI.*/ #if (STM32_SW != STM32_SW_MSI) - RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) ; #endif -- cgit v1.2.3