From c506b8f2b1bf2446442040cd3f00f8750754d5aa Mon Sep 17 00:00:00 2001 From: barthess Date: Wed, 4 Jan 2012 20:03:49 +0000 Subject: PVD. Checked compilability on F1x, L1x, F4x. Testhal fro F1x git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/pvd2_dev@3732 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/hal_lld.c | 6 ++++++ os/hal/platforms/STM32F1xx/hal_lld.h | 27 +++++++++++++++++++++++++++ os/hal/platforms/STM32F1xx/stm32_rcc.h | 32 ++++++++++++++++++++++++++++++++ os/hal/platforms/STM32F2xx/hal_lld.c | 11 ++++++----- os/hal/platforms/STM32F2xx/stm32_rcc.h | 32 ++++++++++++++++++++++++++++++++ os/hal/platforms/STM32F4xx/hal_lld.c | 11 ++++++----- os/hal/platforms/STM32F4xx/stm32_rcc.h | 32 ++++++++++++++++++++++++++++++++ os/hal/platforms/STM32L1xx/hal_lld.c | 6 ++++++ os/hal/platforms/STM32L1xx/hal_lld.h | 24 ++++++++++++++++++++++++ os/hal/platforms/STM32L1xx/stm32_rcc.h | 32 ++++++++++++++++++++++++++++++++ 10 files changed, 203 insertions(+), 10 deletions(-) (limited to 'os/hal/platforms') diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c index 0f2d490d6..8afaf39a2 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.c +++ b/os/hal/platforms/STM32F1xx/hal_lld.c @@ -73,6 +73,12 @@ void hal_lld_init(void) { #if defined(STM32_DMA_REQUIRED) dmaInit(); #endif + + /* Programmable voltage detector enable. */ +#if STM32_PVD_ENABLE + rccEnablePWRInterface(FALSE); + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ } /** diff --git a/os/hal/platforms/STM32F1xx/hal_lld.h b/os/hal/platforms/STM32F1xx/hal_lld.h index 4e1ca3f35..cf8e09cbe 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.h +++ b/os/hal/platforms/STM32F1xx/hal_lld.h @@ -48,10 +48,37 @@ /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ +/** + * @name PWR_CR register bits definitions + * @{ + */ +#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 0. */ +/** @} */ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h index aa55d4fca..41cf725cb 100644 --- a/os/hal/platforms/STM32F1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h @@ -243,6 +243,38 @@ #define rccResetBKP() (RCC->BDCR |= RCC_BDCR_BDRST) /** @} */ +/** + * @brief PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST) +/** @} */ + /** * @brief CAN peripherals specific RCC operations * @{ diff --git a/os/hal/platforms/STM32F2xx/hal_lld.c b/os/hal/platforms/STM32F2xx/hal_lld.c index 2344d161f..a56051a05 100644 --- a/os/hal/platforms/STM32F2xx/hal_lld.c +++ b/os/hal/platforms/STM32F2xx/hal_lld.c @@ -74,14 +74,15 @@ void hal_lld_init(void) { /* DWT cycle counter enable.*/ DWT_CTRL |= DWT_CTRL_CYCCNTENA; -#if STM32_PVD_ENABLE - /* Programmable voltage detector initialization */ - PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); -#endif /* STM32_PVD_ENABLE */ - #if defined(STM32_DMA_REQUIRED) dmaInit(); #endif + + /* Programmable voltage detector enable. */ +#if STM32_PVD_ENABLE + rccEnablePWRInterface(FALSE); + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ } /** diff --git a/os/hal/platforms/STM32F2xx/stm32_rcc.h b/os/hal/platforms/STM32F2xx/stm32_rcc.h index 19ad4484d..39d674bd0 100644 --- a/os/hal/platforms/STM32F2xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F2xx/stm32_rcc.h @@ -390,6 +390,38 @@ #define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST) /** @} */ +/** + * @brief PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST) +/** @} */ + /** * @brief I2C peripherals specific RCC operations * @{ diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c index d9bf8374e..71b8ad219 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.c +++ b/os/hal/platforms/STM32F4xx/hal_lld.c @@ -74,14 +74,15 @@ void hal_lld_init(void) { /* DWT cycle counter enable.*/ DWT_CTRL |= DWT_CTRL_CYCCNTENA; -#if STM32_PVD_ENABLE - /* Programmable voltage detector initialization */ - PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); -#endif /* STM32_PVD_ENABLE */ - #if defined(STM32_DMA_REQUIRED) dmaInit(); #endif + + /* Programmable voltage detector enable. */ +#if STM32_PVD_ENABLE + rccEnablePWRInterface(FALSE); + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ } /** diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h index 4971a71c5..a20274b26 100644 --- a/os/hal/platforms/STM32F4xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h @@ -390,6 +390,38 @@ #define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST) /** @} */ +/** + * @brief PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST) +/** @} */ + /** * @brief I2C peripherals specific RCC operations * @{ diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c index 54d67b9d0..69619dead 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.c +++ b/os/hal/platforms/STM32L1xx/hal_lld.c @@ -74,6 +74,12 @@ void hal_lld_init(void) { #if defined(STM32_DMA_REQUIRED) dmaInit(); #endif + + /* Programmable voltage detector enable. */ +#if STM32_PVD_ENABLE + rccEnablePWRInterface(FALSE); + PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ } /** diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 4bbe2fe76..c11c9ccd8 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -66,6 +66,16 @@ #define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */ #define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */ #define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */ + +#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 0. */ /** @} */ /** @@ -386,6 +396,20 @@ #define STM32_VOS STM32_VOS_1P8 #endif +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + /** * @brief Enables or disables the HSI clock source. */ diff --git a/os/hal/platforms/STM32L1xx/stm32_rcc.h b/os/hal/platforms/STM32L1xx/stm32_rcc.h index 9ffcc07b4..9068adc5a 100644 --- a/os/hal/platforms/STM32L1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32L1xx/stm32_rcc.h @@ -236,6 +236,38 @@ #define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST) /** @} */ +/** + * @brief PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST) +/** @} */ + /** * @brief I2C peripherals specific RCC operations * @{ -- cgit v1.2.3