From 5f707f937719d7642952404f435a2eb5e7485eb0 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 17 Nov 2010 13:57:15 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2380 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM8S/hal_lld.c | 110 ++ os/hal/platforms/STM8S/hal_lld.h | 220 +++ os/hal/platforms/STM8S/pal_lld.c | 110 ++ os/hal/platforms/STM8S/pal_lld.h | 236 ++++ os/hal/platforms/STM8S/platform.dox | 124 ++ os/hal/platforms/STM8S/serial_lld.c | 446 ++++++ os/hal/platforms/STM8S/serial_lld.h | 173 +++ os/hal/platforms/STM8S/spi_lld.c | 290 ++++ os/hal/platforms/STM8S/spi_lld.h | 193 +++ os/hal/platforms/STM8S/stm8.h | 36 + os/hal/platforms/STM8S/stm8s.h | 2567 +++++++++++++++++++++++++++++++++++ os/hal/platforms/STM8S/stm8s_type.h | 103 ++ 12 files changed, 4608 insertions(+) create mode 100644 os/hal/platforms/STM8S/hal_lld.c create mode 100644 os/hal/platforms/STM8S/hal_lld.h create mode 100644 os/hal/platforms/STM8S/pal_lld.c create mode 100644 os/hal/platforms/STM8S/pal_lld.h create mode 100644 os/hal/platforms/STM8S/platform.dox create mode 100644 os/hal/platforms/STM8S/serial_lld.c create mode 100644 os/hal/platforms/STM8S/serial_lld.h create mode 100644 os/hal/platforms/STM8S/spi_lld.c create mode 100644 os/hal/platforms/STM8S/spi_lld.h create mode 100644 os/hal/platforms/STM8S/stm8.h create mode 100644 os/hal/platforms/STM8S/stm8s.h create mode 100644 os/hal/platforms/STM8S/stm8s_type.h (limited to 'os/hal/platforms/STM8S') diff --git a/os/hal/platforms/STM8S/hal_lld.c b/os/hal/platforms/STM8S/hal_lld.c new file mode 100644 index 000000000..87010481c --- /dev/null +++ b/os/hal/platforms/STM8S/hal_lld.c @@ -0,0 +1,110 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM8/hal_lld.c + * @brief STM8 HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * @details Clock sources initialization, HSI is assumed to be already + * started after reset. + * @note If the @p STM8_CLOCK_INIT option is set to @p FALSE then the + * initialization is not performed and is left to the application. + * + * @notapi + */ +void hal_lld_init(void) { + +#if !STM8_NO_CLOCK_INIT + /* Makes sure that HSI is stable before proceeding.*/ + CLK->ICKR |= CLK_ICKR_HSIRDY; + while ((CLK->ICKR & CLK_ICKR_HSIRDY) == 0) + ; + + /* LSI startup and stabilization if required.*/ +#if STM8_LSI_ENABLED + CLK->ICKR |= CLK_ICKR_LSIEN; + while ((CLK->ICKR & CLK_ICKR_LSIRDY) == 0) + ; +#endif + + /* HSE startup and stabilization if required.*/ +#if STM8_HSE_ENABLED + CLK->ECKR |= CLK_ECKR_HSEEN; + while ((CLK->ECKR & CLK_ECKR_HSERDY) == 0) + ; +#endif + + /* Setting up clock dividers.*/ + CLK->CKDIVR = (STM8_HSI_DIVIDER << 3) | (STM8_CPU_DIVIDER << 0); + + /* SYSCLK switch to the selected source, not necessary if it is HSI.*/ +#if STM8_SYSCLK_SOURCE != CLK_SYSSEL_HSI + /* Switching clock (manual switch mode).*/ + CLK->SWR = STM8_SYSCLK_SOURCE; + while ((CLK->SWCR & CLK_SWCR_SWIF) == 0) + ; + CLK->SWCR = CLK_SWCR_SWEN; +#endif + + /* Clocks initially all disabled.*/ + CLK->PCKENR1 = 0; + CLK->PCKENR2 = 0; + + /* Other clock related initializations.*/ + CLK->CSSR = 0; + CLK->CCOR = 0; + CLK->CANCCR = STM8_CAN_DIVIDER_VALUE; + + /* HSI disabled if it is no more required.*/ +#if !STM8_HSI_ENABLED + CLK->ICKR &= ~CLK_ICKR_HSIEN; +#endif +#endif /* !STM8_NO_CLOCK_INIT */ +} + +/** @} */ diff --git a/os/hal/platforms/STM8S/hal_lld.h b/os/hal/platforms/STM8S/hal_lld.h new file mode 100644 index 000000000..6e2c585d2 --- /dev/null +++ b/os/hal/platforms/STM8S/hal_lld.h @@ -0,0 +1,220 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM8/hal_lld.h + * @brief STM8 HAL subsystem low level driver source. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - HSECLK (@p 0 if disabled or frequency in Hertz). + * . + * One of the following macros must also be defined: + * - STM8S103. + * - STM8S105. + * - STM8S207. + * - STM8S208. + * - STM8S903. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "stm8.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "STM8S" + +#define LSICLK 128000 /**< Low speed internal clock. */ +#define HSICLK 16000000 /**< High speed internal clock. */ + +#define CLK_SYSSEL_HSI 0xE1 /**< HSI clock selector. */ +#define CLK_SYSSEL_LSI 0xD2 /**< LSI clock selector. */ +#define CLK_SYSSEL_HSE 0xB4 /**< HSE clock selector. */ + +#define CLK_HSI_DIV1 0 /**< HSI clock divided by 1. */ +#define CLK_HSI_DIV2 1 /**< HSI clock divided by 2. */ +#define CLK_HSI_DIV4 2 /**< HSI clock divided by 4. */ +#define CLK_HSI_DIV8 3 /**< HSI clock divided by 8. */ + +#define CLK_CPU_DIV1 0 /**< CPU clock divided by 1. */ +#define CLK_CPU_DIV2 1 /**< CPU clock divided by 2. */ +#define CLK_CPU_DIV4 2 /**< CPU clock divided by 4. */ +#define CLK_CPU_DIV8 3 /**< CPU clock divided by 8. */ +#define CLK_CPU_DIV16 4 /**< CPU clock divided by 16. */ +#define CLK_CPU_DIV32 5 /**< CPU clock divided by 32. */ +#define CLK_CPU_DIV64 6 /**< CPU clock divided by 64. */ +#define CLK_CPU_DIV128 7 /**< CPU clock divided by 128. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief Disables the clock initialization in the HAL. + */ +#if !defined(STM8_NO_CLOCK_INIT) || defined(__DOXYGEN__) +#define STM8_NO_CLOCK_INIT FALSE +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM8_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM8_HSI_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM8_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM8_LSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM8_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM8_HSE_ENABLED TRUE +#endif + +/** + * @brief Clock source setting. + */ +#if !defined(STM8_SYSCLK_SOURCE) || defined(__DOXYGEN__) +#define STM8_SYSCLK_SOURCE CLK_SYSSEL_HSE +#endif + +/** + * @brief HSI clock divider. + */ +#if !defined(STM8_HSI_DIVIDER) || defined(__DOXYGEN__) +#define STM8_HSI_DIVIDER CLK_HSI_DIV8 +#endif + +/** + * @brief CPU clock divider. + */ +#if !defined(STM8_CPU_DIVIDER) || defined(__DOXYGEN__) +#define STM8_CPU_DIVIDER CLK_CPU_DIV1 +#endif + +/** + * @brief bxCAN divider value. + */ +#if !defined(STM8_CAN_DIVIDER_VALUE) || defined(__DOXYGEN__) +#define STM8_CAN_DIVIDER_VALUE 1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (STM8_HSI_DIVIDER != CLK_HSI_DIV1) && \ + (STM8_HSI_DIVIDER != CLK_HSI_DIV2) && \ + (STM8_HSI_DIVIDER != CLK_HSI_DIV4) && \ + (STM8_HSI_DIVIDER != CLK_HSI_DIV8) +#error "specified invalid HSI divider" +#endif + +#if (STM8_CPU_DIVIDER != CLK_CPU_DIV1) && \ + (STM8_CPU_DIVIDER != CLK_CPU_DIV2) && \ + (STM8_CPU_DIVIDER != CLK_CPU_DIV4) && \ + (STM8_CPU_DIVIDER != CLK_CPU_DIV8) && \ + (STM8_CPU_DIVIDER != CLK_CPU_DIV16) && \ + (STM8_CPU_DIVIDER != CLK_CPU_DIV32) && \ + (STM8_CPU_DIVIDER != CLK_CPU_DIV64) && \ + (STM8_CPU_DIVIDER != CLK_CPU_DIV128) +#error "specified invalid CPU divider" +#endif + +#if (STM8_CAN_DIVIDER_VALUE < 1) || (STM8_CAN_DIVIDER_VALUE > 8) +#error "specified invalid CAN divider value" +#endif + +#if STM8_HSE_ENABLED && (HSECLK == 0) +#error "impossible to activate HSE" +#endif + +#if !STM8_HSI_ENABLED && (STM8_SYSCLK_SOURCE == CLK_SYSSEL_HSI) +#error "requested HSI clock is not enabled" +#endif + +#if !STM8_LSI_ENABLED && (STM8_SYSCLK_SOURCE == CLK_SYSSEL_LSI) +#error "requested LSI clock is not enabled" +#endif + +#if !STM8_HSE_ENABLED && (STM8_SYSCLK_SOURCE == CLK_SYSSEL_HSE) +#error "requested HSE clock is not enabled" +#endif + +/** + * @brief System clock. + */ +#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__) +#define SYSCLK (HSICLK / 8) +#elif STM8_SYSCLK_SOURCE == CLK_SYSSEL_HSI +#define SYSCLK (HSICLK / (1 << STM8_HSI_DIVIDER)) +#elif STM8_SYSCLK_SOURCE == CLK_SYSSEL_LSI +#define SYSCLK LSICLK +#elif STM8_SYSCLK_SOURCE == CLK_SYSSEL_HSE +#define SYSCLK HSECLK +#else +#error "specified invalid clock source" +#endif + +/** + * @brief CPU clock. + * @details On the STM8S the CPU clock can be programmed to be a fraction of + * the system clock. + */ +#define CPUCLK (SYSCLK / (1 << STM8_CPU_DIVIDER)) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/pal_lld.c b/os/hal/platforms/STM8S/pal_lld.c new file mode 100644 index 000000000..3296022e7 --- /dev/null +++ b/os/hal/platforms/STM8S/pal_lld.c @@ -0,0 +1,110 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM8/pal_lld.c + * @brief STM8 GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note This function is not meant to be invoked directly by the + * application code. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + uint_fast8_t mode) { + + switch (mode & PAL_MODE_MASK) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT_PULLUP: + port->DDR &= ~mask; + port->CR1 |= mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_INPUT: + case PAL_MODE_INPUT_ANALOG: + port->DDR &= ~mask; + port->CR1 &= ~mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_UNCONNECTED: + case PAL_MODE_OUTPUT_PUSHPULL_SLOW: + port->DDR |= mask; + port->CR1 |= mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_OUTPUT_PUSHPULL: + port->DDR |= mask; + port->CR1 |= mask; + port->CR2 |= mask; + break; + case PAL_MODE_OUTPUT_OPENDRAIN_SLOW: + port->DDR |= mask; + port->CR1 &= ~mask; + port->CR2 &= ~mask; + break; + case PAL_MODE_OUTPUT_OPENDRAIN: + port->DDR |= mask; + port->CR1 &= ~mask; + port->CR2 |= mask; + break; + } +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/pal_lld.h b/os/hal/platforms/STM8S/pal_lld.h new file mode 100644 index 000000000..c8e572d42 --- /dev/null +++ b/os/hal/platforms/STM8S/pal_lld.h @@ -0,0 +1,236 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM8/pal_lld.h + * @brief STM8 GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLDOWN + +/** + * @brief STM8 specific alternate push-pull slow output mode. + */ +#define PAL_MODE_OUTPUT_PUSHPULL_SLOW 16 + +/** + * @brief STM8 specific alternate open-drain slow output mode. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN_SLOW 17 + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief Generic I/O ports static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct { +#if defined(STM8S105) || defined(__DOXYGEN__) + GPIO_TypeDef P[7]; +#elif defined(STM8S207) || defined(STM8S208) + GPIO_TypeDef P[9]; +#else + GPIO_TypeDef P[6]; +#endif +} PALConfig; + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint8_t ioportmask_t; + +/** + * @brief Port Identifier. + */ +typedef GPIO_TypeDef *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO ports as a whole. + */ +#define IOPORTS ((PALConfig *)0x5000) + +/** + * @brief GPIO port A identifier. + */ +#define IOPORT1 GPIOA + +/** + * @brief GPIO port B identifier. + */ +#define IOPORT2 GPIOB + +/** + * @brief GPIO port C identifier. + */ +#define IOPORT3 GPIOC + +/** + * @brief GPIO port D identifier. + */ +#define IOPORT4 GPIOD + +/** + * @brief GPIO port E identifier. + */ +#define IOPORT5 GPIOE + +/** + * @brief GPIO port F identifier. + */ +#define IOPORT6 GPIOF + +#if defined(STM8S207) || defined(STM8S208) || defined(STM8S105) || \ + defined(__DOXYGEN__) +/** + * @brief GPIO port G identifier. + */ +#define IOPORT7 GPIOG +#endif + +#if defined(STM8S207) || defined(STM8S208) || defined(__DOXYGEN__) +/** + * @brief GPIO port H identifier. + */ +#define IOPORT8 GPIOH + +/** + * @brief GPIO port I identifier. + */ +#define IOPORT9 GPIOI +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) *IOPORTS = *(config) + +/** + * @brief Reads the physical I/O port states. + * @note This function is not meant to be invoked directly by the + * application code. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->IDR) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * @note This function is not meant to be invoked directly by the + * application code. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->ODR) + +/** + * @brief Writes a bits mask on a I/O port. + * @note This function is not meant to be invoked directly by the + * application code. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) + + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note This function is not meant to be invoked directly by the + * application code. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, mode) \ + _pal_lld_setgroupmode(port, mask, mode) + +extern ROMCONST PALConfig pal_default_config; + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + uint_fast8_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/platform.dox b/os/hal/platforms/STM8S/platform.dox new file mode 100644 index 000000000..c71063910 --- /dev/null +++ b/os/hal/platforms/STM8S/platform.dox @@ -0,0 +1,124 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup STM8 STM8x Drivers + * @details This section describes all the supported drivers on the STM8S and + * STM8A platforms and the implementation details of the single + * drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup STM8_HAL STM8 Initialization Support + * @details The STM8 HAL support is responsible for system initialization. + * + * @section stm8_hal_1 Supported HW resources + * - CLK. + * . + * @section stm8_hal_2 STM8 HAL driver implementation features + * - Clock tree initialization. + * - Clock source selection. + * . + * @ingroup STM8 + */ + +/** + * @defgroup STM8_PAL STM8 GPIO Support + * @details The STM8 PAL driver uses the GPIO peripherals. + * + * @section stm8_pal_1 Supported HW resources + * - AFIO. + * - GPIOA. + * - GPIOB. + * - GPIOC. + * - GPIOD. + * - GPIOE. + * - GPIOF. + * - GPIOG (where present). + * - GPIOH (where present). + * - GPIOI (where present). + * . + * @section stm8_pal_2 STM8 PAL driver implementation features + * The PAL driver implementation fully supports the following hardware + * capabilities: + * - 8 bits wide ports. + * - Atomic set/reset/toggle functions because special STM8 instruction set. + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section stm8_pal_3 Supported PAL setup modes + * The STM8 PAL driver supports the following I/O modes: + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_INPUT_PULLUP. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * - @p PAL_MODE_OUTPUT_OPENDRAIN. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section stm8_pal_4 Suboptimal behavior + * The STM8 GPIO is less than optimal in several areas, the limitations + * should be taken in account while using the PAL driver: + * - Bus/group writing is not atomic. + * - Pad/group mode setup is not atomic. + * . + * @ingroup STM8 + */ + +/** + * @defgroup STM8_SPI STM8 SPI Support + * @details The SPI driver supports the STM8 SPI peripheral in an interrupt + * driven implementation. + * @note Being the SPI a fast peripheral, much care must be taken to + * not saturate the CPU bandwidth with an excessive IRQ rate. The + * maximum transfer bit rate is likely limited by the IRQ + * handling. + * + * @section stm8_spi_1 Supported HW resources + * - SPI. + * . + * @section stm8_spi_2 STM8 SPI driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * . + * @ingroup STM8 + */ + +/** + * @defgroup STM8_SERIAL STM8 UART Support (buffered) + * @details The STM8 Serial driver uses the UART peripherals in a + * buffered, interrupt driven, implementation. + * + * @section stm8_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - UART1. + * - UART2 (where present). + * - UART3 (where present). + * . + * @section stm8_serial_2 STM8 Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Each UART can be independently enabled and programmed. Unused + * peripherals are left in low power mode. + * - Fully interrupt driven. + * . + * @ingroup STM8 + */ diff --git a/os/hal/platforms/STM8S/serial_lld.c b/os/hal/platforms/STM8S/serial_lld.c new file mode 100644 index 000000000..06f2f482b --- /dev/null +++ b/os/hal/platforms/STM8S/serial_lld.c @@ -0,0 +1,446 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM8/serial_lld.c + * @brief STM8 low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief UART1 serial driver identifier. + */ +#if STM8_SERIAL_USE_UART1 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief UART2 serial driver identifier. + */ +#if STM8_SERIAL_USE_UART2 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/** + * @brief UART3 serial driver identifier. + */ +#if STM8_SERIAL_USE_UART3 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static ROMCONST SerialConfig default_config = { + BBR(SERIAL_DEFAULT_BITRATE), + SD_MODE_PARITY_NONE | SD_MODE_STOP_1 +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void set_error(SerialDriver *sdp, uint8_t sr) { + sdflags_t sts = 0; + + /* Note, SR register bit definitions are equal for all UARTs so using + the UART1 definitions is fine.*/ + if (sr & UART1_SR_OR) + sts |= SD_OVERRUN_ERROR; + if (sr & UART1_SR_NF) + sts |= SD_NOISE_ERROR; + if (sr & UART1_SR_FE) + sts |= SD_FRAMING_ERROR; + if (sr & UART1_SR_PE) + sts |= SD_PARITY_ERROR; + chSysLockFromIsr(); + sdAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +#if STM8_SERIAL_USE_UART1 || defined(__DOXYGEN__) +static void notify1(void) { + + UART1->CR2 |= UART1_CR2_TIEN; +} + +/** + * @brief UART1 initialization. + * + * @param[in] config architecture-dependent serial driver configuration + */ +static void uart1_init(const SerialConfig *config) { + + UART1->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | + ((uint8_t)config->sc_brr & (uint8_t)0x0F)); + UART1->BRR1 = (uint8_t)(config->sc_brr >> 4); + UART1->CR1 = (uint8_t)(config->sc_mode & + SD_MODE_PARITY); /* PIEN included. */ + UART1->CR2 = UART1_CR2_RIEN | UART1_CR2_TEN | UART1_CR2_REN; + UART1->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP); + UART1->CR4 = 0; + UART1->CR5 = 0; + UART1->PSCR = 1; + (void)UART1->SR; + (void)UART1->DR; +} + +/** + * @brief UART1 de-initialization. + */ +static void uart1_deinit(void) { + + UART1->CR1 = UART1_CR1_UARTD; + UART1->CR2 = 0; + UART1->CR3 = 0; + UART1->CR4 = 0; + UART1->CR5 = 0; + UART1->PSCR = 0; +} +#endif /* STM8_SERIAL_USE_UART1 */ + +#if STM8_SERIAL_USE_UART2 || defined(__DOXYGEN__) +static void notify2(void) { + + UART2->CR2 |= UART2_CR2_TIEN; +} + +/** + * @brief UART2 initialization. + * + * @param[in] config architecture-dependent serial driver configuration + */ +static void uart2_init(const SerialConfig *config) { + + UART2->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | + ((uint8_t)config->sc_brr & (uint8_t)0x0F)); + UART2->BRR1 = (uint8_t)(config->sc_brr >> 4); + UART2->CR1 = (uint8_t)(config->sc_mode & + SD_MODE_PARITY); /* PIEN included. */ + UART2->CR2 = UART2_CR2_RIEN | UART2_CR2_TEN | UART2_CR2_REN; + UART2->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP); + UART2->CR4 = 0; + UART2->CR5 = 0; + UART2->CR6 = 0; + UART2->PSCR = 1; + (void)UART2->SR; + (void)UART2->DR; +} + +/** + * @brief UART1 de-initialization. + */ +static void uart2_deinit(void) { + + UART2->CR1 = UART2_CR1_UARTD; + UART2->CR2 = 0; + UART2->CR3 = 0; + UART2->CR4 = 0; + UART2->CR5 = 0; + UART2->CR6 = 0; + UART2->PSCR = 0; +} +#endif /* STM8_SERIAL_USE_UART1 */ + +#if STM8_SERIAL_USE_UART3 || defined(__DOXYGEN__) +static void notify3(void) { + + UART3->CR2 |= UART3_CR2_TIEN; +} + +/** + * @brief UART3 initialization. + * + * @param[in] config architecture-dependent serial driver configuration + */ +static void uart3_init(const SerialConfig *config) { + + UART3->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | + ((uint8_t)config->sc_brr & (uint8_t)0x0F)); + UART3->BRR1 = (uint8_t)(config->sc_brr >> 4); + UART3->CR1 = (uint8_t)(config->sc_mode & + SD_MODE_PARITY); /* PIEN included. */ + UART3->CR2 = UART3_CR2_RIEN | UART3_CR2_TEN | UART3_CR2_REN; + UART3->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP); + UART3->CR4 = 0; + UART3->CR6 = 0; + (void)UART3->SR; + (void)UART3->DR; +} + +/** + * @brief UART3 de-initialization. + */ +static void uart3_deinit(void) { + + UART3->CR1 = UART3_CR1_UARTD; + UART3->CR2 = 0; + UART3->CR3 = 0; + UART3->CR4 = 0; + UART3->CR6 = 0; +} +#endif /* STM8_SERIAL_USE_UART3 */ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM8_SERIAL_USE_UART1 || defined(__DOXYGEN__) +/** + * @brief IRQ 17 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(17) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD1); + chSysUnlockFromIsr(); + if (b < Q_OK) + UART1->CR2 &= (uint8_t)~UART1_CR2_TIEN; + else + UART1->DR = (uint8_t)b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief IRQ 18 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(18) { + uint8_t sr = UART1->SR; + + CH_IRQ_PROLOGUE(); + + if ((sr = UART1->SR) & (UART1_SR_OR | UART1_SR_NF | + UART1_SR_FE | UART1_SR_PE)) + set_error(&SD1, sr); + chSysLockFromIsr(); + sdIncomingDataI(&SD1, UART1->DR); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM8_SERIAL_USE_UART1 */ + +#if STM8_SERIAL_USE_UART2 || defined(__DOXYGEN__) +/** + * @brief IRQ 20 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(20) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD2); + chSysUnlockFromIsr(); + if (b < Q_OK) + UART2->CR2 &= (uint8_t)~UART2_CR2_TIEN; + else + UART2->DR = (uint8_t)b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief IRQ 21 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(21) { + uint8_t sr = UART2->SR; + + CH_IRQ_PROLOGUE(); + + if ((sr = UART2->SR) & (UART2_SR_OR | UART2_SR_NF | + UART2_SR_FE | UART2_SR_PE)) + set_error(&SD2, sr); + chSysLockFromIsr(); + sdIncomingDataI(&SD2, UART2->DR); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM8_SERIAL_USE_UART2 */ + +#if STM8_SERIAL_USE_UART3 || defined(__DOXYGEN__) +/** + * @brief IRQ 20 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(20) { + msg_t b; + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + b = sdRequestDataI(&SD3); + chSysUnlockFromIsr(); + if (b < Q_OK) + UART3->CR2 &= (uint8_t)~UART3_CR2_TIEN; + else + UART3->DR = (uint8_t)b; + + CH_IRQ_EPILOGUE(); +} + +/** + * @brief IRQ 21 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(21) { + uint8_t sr = UART3->SR; + + CH_IRQ_PROLOGUE(); + + if ((sr = UART3->SR) & (UART3_SR_OR | UART3_SR_NF | + UART3_SR_FE | UART3_SR_PE)) + set_error(&SD3, sr); + chSysLockFromIsr(); + sdIncomingDataI(&SD3, UART3->DR); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} +#endif /* STM8_SERIAL_USE_UART3 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if STM8_SERIAL_USE_UART1 + sdObjectInit(&SD1, NULL, notify1); + CLK->PCKENR1 |= CLK_PCKENR1_UART1; /* PCKEN12, clock source. */ + UART1->CR1 = UART1_CR1_UARTD; /* UARTD (low power). */ +#endif + +#if STM8_SERIAL_USE_UART2 + sdObjectInit(&SD2, NULL, notify2); + CLK->PCKENR1 |= CLK_PCKENR1_UART2; /* PCKEN13, clock source. */ + UART2->CR1 = UART2_CR1_UARTD; /* UARTD (low power). */ +#endif + +#if STM8_SERIAL_USE_UART3 + sdObjectInit(&SD3, NULL, notify3); + CLK->PCKENR1 |= CLK_PCKENR1_UART3; /* PCKEN13, clock source. */ + UART3->CR1 = UART3_CR1_UARTD; /* UARTD (low power). */ +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { + + if (config == NULL) + config = &default_config; + +#if STM8_SERIAL_USE_UART1 + if (&SD1 == sdp) { + uart1_init(config); + return; + } +#endif +#if STM8_SERIAL_USE_UART2 + if (&SD2 == sdp) { + uart2_init(config); + return; + } +#endif +#if STM8_SERIAL_USE_UART3 + if (&SD3 == sdp) { + uart3_init(config); + return; + } +#endif +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the USART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop(SerialDriver *sdp) { + +#if STM8_SERIAL_USE_UART1 + if (&SD1 == sdp) { + uart1_deinit(); + return; + } +#endif +#if STM8_SERIAL_USE_UART2 + if (&SD2 == sdp) { + uart2_deinit(); + return; + } +#endif +#if STM8_SERIAL_USE_UART3 + if (&SD3 == sdp) { + uart3_deinit(); + return; + } +#endif +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/serial_lld.h b/os/hal/platforms/STM8S/serial_lld.h new file mode 100644 index 000000000..fe6b9bcaa --- /dev/null +++ b/os/hal/platforms/STM8S/serial_lld.h @@ -0,0 +1,173 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM8/serial_lld.h + * @brief STM8 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define SD_MODE_PARITY 0x07 /**< @brief Parity field mask. */ +#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ +#define SD_MODE_PARITY_EVEN 0x05 /**< @brief Even parity. */ +#define SD_MODE_PARITY_ODD 0x07 /**< @brief Odd parity. */ + +#define SD_MODE_STOP 0x30 /**< @brief Stop bits mask. */ +#define SD_MODE_STOP_1 0x00 /**< @brief One stop bit. */ +#define SD_MODE_STOP_2 0x20 /**< @brief Two stop bits. */ +#define SD_MODE_STOP_1P5 0x30 /**< @brief 1.5 stop bits. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8_SERIAL_USE_UART1) || defined(__DOXYGEN__) +#define STM8_SERIAL_USE_UART1 TRUE +#endif + +/** + * @brief UART2 driver enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8_SERIAL_USE_UART2) || defined(__DOXYGEN__) +#define STM8_SERIAL_USE_UART2 TRUE +#endif + +/** + * @brief UART3 driver enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8_SERIAL_USE_UART3) || defined(__DOXYGEN__) +#define STM8_SERIAL_USE_UART3 TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if STM8_SERIAL_USE_UART2 && STM8_SERIAL_USE_UART3 +#error "STM8 UART2 and UART3 cannot be used together" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Serial Driver condition flags type. + */ +typedef uint8_t sdflags_t; + +/** + * @brief Generic Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate register. + */ + uint16_t sc_brr; + /** + * @brief Mode flags. + */ + uint8_t sc_mode; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Status Change @p EventSource.*/ \ + EventSource sevent; \ + /* I/O driver status flags.*/ \ + sdflags_t flags; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Macro for baud rate computation. + * @note Make sure the final baud rate is within tolerance. + */ +#define BBR(b) (SYSCLK / (b)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM8_SERIAL_USE_UART1 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif +#if STM8_SERIAL_USE_UART2 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif +#if STM8_SERIAL_USE_UART3 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/spi_lld.c b/os/hal/platforms/STM8S/spi_lld.c new file mode 100644 index 000000000..4accd6cd0 --- /dev/null +++ b/os/hal/platforms/STM8S/spi_lld.c @@ -0,0 +1,290 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM8/spi_lld.c + * @brief STM8 low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if STM8_SPI_USE_SPI || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM8_SPI_USE_SPI || defined(__DOXYGEN__) +/** + * @brief IRQ 10 service routine. + * + * @isr + */ +CH_IRQ_HANDLER(10) { + + CH_IRQ_PROLOGUE(); + + if ((SPI->SR & SPI_SR_OVR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + STM8_SPI_ERROR_HOOK(&SPID1); + } + /* Handling the DR register like it is a FIFO with depth>1 in order to + handle the case where a frame arrives immediately after reading the + DR register.*/ + while ((SPI->SR & SPI_SR_RXNE) != 0) { + if (SPID1.spd_rxptr != NULL) + *SPID1.spd_rxptr++ = SPI->DR; + else + (void)SPI->DR; + if (--SPID1.spd_rxcnt == 0) { + chDbgAssert(SPID1.spd_txcnt == 0, + "IRQ10, #1", "counter out of synch"); + /* Stops all the IRQ sources.*/ + SPI->ICR = 0; + /* Portable SPI ISR code defined in the high level driver, note, it + is a macro.*/ + _spi_isr_code(&SPID1); + /* Goto because it is mandatory to go through the epilogue, cannot + just return.*/ + goto exit_isr; + } + } + /* Loading the DR register.*/ + if ((SPI->SR & SPI_SR_TXE) != 0) { + if (SPID1.spd_txptr != NULL) + SPI->DR = *SPID1.spd_txptr++; + else + SPI->DR = 0xFF; + } + +exit_isr: + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if STM8_SPI_USE_SPI + spiObjectInit(&SPID1); +#endif /* STM8_SPI_USE_SPI */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + /* Clock activation.*/ + CLK->PCKENR1 |= CLK_PCKENR1_SPI; /* PCKEN11, clock source. */ + + /* Configuration.*/ + SPI->CR2 = 0; + SPI->CR1 = spip->spd_config->spc_cr1 | SPI_CR1_MSTR | SPI_CR1_SPE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + (void)spip; + + /* Reset state.*/ + SPI->CR1 = 0; + SPI->CR2 = 0; + SPI->ICR = 0; + + /* Clock de-activation.*/ + CLK->PCKENR1 &= (uint8_t)~CLK_PCKENR1_SPI; /* PCKEN11, clock source. */ +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->spd_config->spc_ssport, spip->spd_config->spc_sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->spd_config->spc_ssport, spip->spd_config->spc_sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->spd_rxptr = NULL; + spip->spd_txptr = NULL; + spip->spd_rxcnt = spip->spd_txcnt = n; + SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->spd_rxptr = rxbuf; + spip->spd_txptr = txbuf; + spip->spd_rxcnt = spip->spd_txcnt = n; + SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->spd_rxptr = NULL; + spip->spd_txptr = txbuf; + spip->spd_rxcnt = spip->spd_txcnt = n; + SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->spd_rxptr = rxbuf; + spip->spd_txptr = NULL; + spip->spd_rxcnt = spip->spd_txcnt = n; + SPI->ICR = SPI_ICR_TXEI | SPI_ICR_RXEI | SPI_ICR_ERRIE; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame) { + + (void)spip; + + SPI->DR = (uint32_t)frame; + while ((SPI->SR & SPI_SR_RXNE) == 0) + ; + return (uint16_t)SPI->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/spi_lld.h b/os/hal/platforms/STM8S/spi_lld.h new file mode 100644 index 000000000..a1b56694e --- /dev/null +++ b/os/hal/platforms/STM8S/spi_lld.h @@ -0,0 +1,193 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC13xx/spi_lld.h + * @brief LPC13xx low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for device SSP0 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM8_SPI_USE_SPI) || defined(__DOXYGEN__) +#define STM8_SPI_USE_SPI TRUE +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(STM8_SPI_SPI_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM8_SPI_ERROR_HOOK(spip) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM8_SPI_USE_SPI +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + * @note In order to use synchronous functions this field must be set to + * @p NULL, callbacks and synchronous operations are mutually + * exclusive. + */ + spicallback_t spc_endcb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t spc_ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t spc_sspad; + /** + * @brief SPI initialization data. + */ + uint8_t spc_cr1; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t spd_state; + /** + * @brief Current configuration data. + */ + const SPIConfig *spd_config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *spd_thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex spd_mutex; +#elif CH_USE_SEMAPHORES + Semaphore spd_semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Number of bytes yet to be received. + */ + uint16_t spd_rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + uint8_t *spd_rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint16_t spd_txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const uint8_t *spd_txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM8_SPI_USE_SPI && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/STM8S/stm8.h b/os/hal/platforms/STM8S/stm8.h new file mode 100644 index 000000000..d0ef215a4 --- /dev/null +++ b/os/hal/platforms/STM8S/stm8.h @@ -0,0 +1,36 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _STM8_H_ +#define _STM8_H_ + +#undef FALSE +#undef TRUE + +#if defined(STM8S208) || defined(STM8S207) || defined(STM8S105) || \ + defined(STM8S103) || defined (STM8S903) +#include "stm8s.h" +#else +#error "unsupported or invalid STM8 platform" +#endif + +#define FALSE 0 +#define TRUE (!FALSE) + +#endif /* _STM8_H_ */ diff --git a/os/hal/platforms/STM8S/stm8s.h b/os/hal/platforms/STM8S/stm8s.h new file mode 100644 index 000000000..c210092c3 --- /dev/null +++ b/os/hal/platforms/STM8S/stm8s.h @@ -0,0 +1,2567 @@ +/** + ****************************************************************************** + * @file stm8s.h + * @brief This file contains all HW registers definitions and memory mapping. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_H +#define __STM8S_H + +/******************************************************************************/ +/* Library configuration section */ +/******************************************************************************/ +/* Check the used compiler */ +#if defined(__CSMC__) + #undef _RAISONANCE_ + #define _COSMIC_ +#elif defined(__RCST7__) + #undef _COSMIC_ + #define _RAISONANCE_ +#else + #error "Unsupported Compiler!" /* Compiler defines not found */ +#endif + +/* Uncomment the line below according to the target STM8S device used in your + application. + Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. */ +#if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && !defined (STM8S103) && !defined (STM8S903) + #define STM8S208 + /* #define STM8S207 */ + /* #define STM8S105 */ + /* #define STM8S103 */ + /* #define STM8S903 */ +#endif + + +#if !defined USE_STDPERIPH_DRIVER +/* Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will be + based on direct access to peripherals registers */ +/* #define USE_STDPERIPH_DRIVER*/ +#endif + +/* For FLASH routines, select whether pointer will be declared as near (2 bytes, handle + code smaller than 64KB) or far (3 bytes, handle code larger than 64K) */ +/*#define PointerAttr_Near 1 */ /*!< Used with memory Models for code smaller than 64K */ +#define PointerAttr_Far 2 /*!< Used with memory Models for code larger than 64K */ + +#ifdef _COSMIC_ + #define FAR @far + #define NEAR @near + #define TINY @tiny + #define __CONST const +#else /* __RCST7__ */ + #define FAR far + #define NEAR data + #define TINY page0 + #define __CONST code +#endif /* __CSMC__ */ + +#ifdef PointerAttr_Far + #define PointerAttr FAR +#else /* PointerAttr_Near */ + #define PointerAttr NEAR +#endif /* PointerAttr_Far */ + + +/* Uncomment the line below to use the cosmic section */ +#if defined(_COSMIC_) +/* #define USE_COSMIC_SECTIONS (1)*/ +#endif + +/******************************************************************************/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm8s_type.h" + +/* Exported types and constants-----------------------------------------------*/ +/** @addtogroup MAP_FILE_Exported_Types_and_Constants + * @{ + */ + +/******************************************************************************/ +/* IP registers structures */ +/******************************************************************************/ +/*----------------------------------------------------------------------------*/ +/** + * @brief General Purpose I/Os (GPIO) + */ + +typedef struct GPIO_struct +{ + vu8 ODR; /*!< Output Data Register */ + vu8 IDR; /*!< Input Data Register */ + vu8 DDR; /*!< Data Direction Register */ + vu8 CR1; /*!< Configuration Register 1 */ + vu8 CR2; /*!< Configuration Register 2 */ +} +GPIO_TypeDef; + +/** @addtogroup GPIO_Registers_Reset_Value + * @{ + */ + +#define GPIO_ODR_RESET_VALUE ((u8)0x00) +#define GPIO_DDR_RESET_VALUE ((u8)0x00) +#define GPIO_CR1_RESET_VALUE ((u8)0x00) +#define GPIO_CR2_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +#if defined(STM8S105) || defined(STM8S103) || defined(STM8S903) +/** + * @brief Analog to Digital Converter (ADC1) + */ +typedef struct ADC1_struct +{ + vu8 DB0RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB0RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB1RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB1RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB2RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB2RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB3RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB3RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB4RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB4RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB5RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB5RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB6RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB6RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB7RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB7RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB8RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB8RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 DB9RH; /*!< ADC1 Data Buffer Register (MSB) */ + vu8 DB9RL; /*!< ADC1 Data Buffer Register (LSB) */ + vu8 RESERVED[12]; /*!< Reserved byte */ + vu8 CSR; /*!< ADC1 control status register */ + vu8 CR1; /*!< ADC1 configuration register 1 */ + vu8 CR2; /*!< ADC1 configuration register 2 */ + vu8 CR3; /*!< ADC1 configuration register 3 */ + vu8 DRH; /*!< ADC1 Data high */ + vu8 DRL; /*!< ADC1 Data low */ + vu8 TDRH; /*!< ADC1 Schmitt trigger disable register high */ + vu8 TDRL; /*!< ADC1 Schmitt trigger disable register low */ + vu8 HTRH; /*!< ADC1 high threshold register High*/ + vu8 HTRL; /*!< ADC1 high threshold register Low*/ + vu8 LTRH; /*!< ADC1 low threshold register high */ + vu8 LTRL; /*!< ADC1 low threshold register low */ + vu8 AWSRH; /*!< ADC1 watchdog status register high */ + vu8 AWSRL; /*!< ADC1 watchdog status register low */ + vu8 AWCRH; /*!< ADC1 watchdog control register high */ + vu8 AWCRL; /*!< ADC1 watchdog control register low */ +} +ADC1_TypeDef; + +/** @addtogroup ADC1_Registers_Reset_Value + * @{ + */ + +#define ADC1_CSR_RESET_VALUE ((u8)0x00) +#define ADC1_CR1_RESET_VALUE ((u8)0x00) +#define ADC1_CR2_RESET_VALUE ((u8)0x00) +#define ADC1_CR3_RESET_VALUE ((u8)0x00) +#define ADC1_TDRL_RESET_VALUE ((u8)0x00) +#define ADC1_TDRH_RESET_VALUE ((u8)0x00) +#define ADC1_HTRL_RESET_VALUE ((u8)0x03) +#define ADC1_HTRH_RESET_VALUE ((u8)0xFF) +#define ADC1_LTRH_RESET_VALUE ((u8)0x00) +#define ADC1_LTRL_RESET_VALUE ((u8)0x00) +#define ADC1_AWCRH_RESET_VALUE ((u8)0x00) +#define ADC1_AWCRL_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup ADC1_Registers_Bits_Definition + * @{ + */ + +#define ADC1_CSR_EOC ((u8)0x80) /*!< End of Conversion mask */ +#define ADC1_CSR_AWD ((u8)0x40) /*!< Analog Watch Dog Status mask */ +#define ADC1_CSR_EOCIE ((u8)0x20) /*!< Interrupt Enable for EOC mask */ +#define ADC1_CSR_AWDIE ((u8)0x10) /*!< Analog Watchdog interrupt enable mask */ +#define ADC1_CSR_CH ((u8)0x0F) /*!< Channel selection bits mask */ + +#define ADC1_CR1_SPSEL ((u8)0x70) /*!< Prescaler selectiont mask */ +#define ADC1_CR1_CONT ((u8)0x02) /*!< Continuous conversion mask */ +#define ADC1_CR1_ADON ((u8)0x01) /*!< A/D Converter on/off mask */ + +#define ADC1_CR2_EXTTRIG ((u8)0x40) /*!< External trigger enable mask */ +#define ADC1_CR2_EXTSEL ((u8)0x30) /*!< External event selection mask */ +#define ADC1_CR2_ALIGN ((u8)0x08) /*!< Data Alignment mask */ +#define ADC1_CR2_SCAN ((u8)0x02) /*!< Scan mode mask */ + +#define ADC1_CR3_DBUF ((u8)0x80) /*!< Data Buffer Enable mask */ +#define ADC1_CR3_OVR ((u8)0x40) /*!< Overrun Status Flag mask */ + +#endif /* (STM8S105) ||(STM8S103) || (STM8S903) */ +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief Analog to Digital Converter (ADC2) + */ +#if defined(STM8S208) || defined(STM8S207) +typedef struct ADC2_struct +{ + vu8 CSR; /*!< ADC2 control status register */ + vu8 CR1; /*!< ADC2 configuration register 1 */ + vu8 CR2; /*!< ADC2 configuration register 2 */ + vu8 RESERVED; /*!< Reserved byte */ + vu8 DRH; /*!< ADC2 Data high */ + vu8 DRL; /*!< ADC2 Data low */ + vu8 TDRH; /*!< ADC2 Schmitt trigger disable register high */ + vu8 TDRL; /*!< ADC2 Schmitt trigger disable register low */ +} +ADC2_TypeDef; + +/** @addtogroup ADC2_Registers_Reset_Value + * @{ + */ + +#define ADC2_CSR_RESET_VALUE ((u8)0x00) +#define ADC2_CR1_RESET_VALUE ((u8)0x00) +#define ADC2_CR2_RESET_VALUE ((u8)0x00) +#define ADC2_TDRL_RESET_VALUE ((u8)0x00) +#define ADC2_TDRH_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup ADC2_Registers_Bits_Definition + * @{ + */ + +#define ADC2_CSR_EOC ((u8)0x80) /*!< End of Conversion mask */ +#define ADC2_CSR_EOCIE ((u8)0x20) /*!< Interrupt Enable for EOC mask */ +#define ADC2_CSR_CH ((u8)0x0F) /*!< Channel selection bits mask */ + +#define ADC2_CR1_SPSEL ((u8)0x70) /*!< Prescaler selectiont mask */ +#define ADC2_CR1_CONT ((u8)0x02) /*!< Continuous conversion mask */ +#define ADC2_CR1_ADON ((u8)0x01) /*!< A/D Converter on/off mask */ + +#define ADC2_CR2_EXTTRIG ((u8)0x40) /*!< External trigger enable mask */ +#define ADC2_CR2_EXTSEL ((u8)0x30) /*!< External event selection mask */ +#define ADC2_CR2_ALIGN ((u8)0x08) /*!< Data Alignment mask */ + +#endif /* (STM8S208) ||(STM8S207) */ +/** + * @} + */ +/*----------------------------------------------------------------------------*/ +/** + * @brief Auto Wake Up (AWU) peripheral registers. + */ + +typedef struct AWU_struct +{ + vu8 CSR; /*!< AWU Control status register */ + vu8 APR; /*!< AWU Asynchronous prescalar buffer */ + vu8 TBR; /*!< AWU Time base selection register */ +} +AWU_TypeDef; + +/** @addtogroup AWU_Registers_Reset_Value + * @{ + */ + +#define AWU_CSR_RESET_VALUE ((u8)0x00) +#define AWU_APR_RESET_VALUE ((u8)0x3F) +#define AWU_TBR_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup AWU_Registers_Bits_Definition + * @{ + */ + +#define AWU_CSR_AWUF ((u8)0x20) /*!< Interrupt flag mask */ +#define AWU_CSR_AWUEN ((u8)0x10) /*!< Auto Wake-up enable mask */ +#define AWU_CSR_MR ((u8)0x02) /*!< Master Reset mask */ +#define AWU_CSR_MSR ((u8)0x01) /*!< Measurement enable mask */ + +#define AWU_APR_APR ((u8)0x3F) /*!< Asynchronous Prescaler divider mask */ + +#define AWU_TBR_AWUTB ((u8)0x0F) /*!< Timebase selection mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief Beeper (BEEP) peripheral registers. + */ + +typedef struct BEEP_struct +{ + vu8 CSR; /*!< BEEP Control status register */ +} +BEEP_TypeDef; + +/** @addtogroup BEEP_Registers_Reset_Value + * @{ + */ + +#define BEEP_CSR_RESET_VALUE ((u8)0x1F) + +/** + * @} + */ + +/** @addtogroup BEEP_Registers_Bits_Definition + * @{ + */ + +#define BEEP_CSR_BEEPSEL ((u8)0xC0) /*!< Beeper frequency selection mask */ +#define BEEP_CSR_BEEPEN ((u8)0x20) /*!< Beeper enable mask */ +#define BEEP_CSR_BEEPDIV ((u8)0x1F) /*!< Beeper Divider prescalar mask */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief Clock Controller (CLK) + */ + +typedef struct CLK_struct +{ + vu8 ICKR; /*!< Internal Clocks Control Register */ + vu8 ECKR; /*!< External Clocks Control Register */ + u8 RESERVED; /*!< Reserved byte */ + vu8 CMSR; /*!< Clock Master Status Register */ + vu8 SWR; /*!< Clock Master Switch Register */ + vu8 SWCR; /*!< Switch Control Register */ + vu8 CKDIVR; /*!< Clock Divider Register */ + vu8 PCKENR1; /*!< Peripheral Clock Gating Register 1 */ + vu8 CSSR; /*!< Clock Security Sytem Register */ + vu8 CCOR; /*!< Configurable Clock Output Register */ + vu8 PCKENR2; /*!< Peripheral Clock Gating Register 2 */ + vu8 CANCCR; /*!< CAN external clock control Register (exist only in STM8S208 otherwise it is reserved) */ + vu8 HSITRIMR; /*!< HSI Calibration Trimmer Register */ + vu8 SWIMCCR; /*!< SWIM clock control register */ +} +CLK_TypeDef; + +/** @addtogroup CLK_Registers_Reset_Value + * @{ + */ + +#define CLK_ICKR_RESET_VALUE ((u8)0x01) +#define CLK_ECKR_RESET_VALUE ((u8)0x00) +#define CLK_CMSR_RESET_VALUE ((u8)0xE1) +#define CLK_SWR_RESET_VALUE ((u8)0xE1) +#define CLK_SWCR_RESET_VALUE ((u8)0x00) +#define CLK_CKDIVR_RESET_VALUE ((u8)0x18) +#define CLK_PCKENR1_RESET_VALUE ((u8)0xFF) +#define CLK_PCKENR2_RESET_VALUE ((u8)0xFF) +#define CLK_CSSR_RESET_VALUE ((u8)0x00) +#define CLK_CCOR_RESET_VALUE ((u8)0x00) +#define CLK_CANCCR_RESET_VALUE ((u8)0x00) +#define CLK_HSITRIMR_RESET_VALUE ((u8)0x00) +#define CLK_SWIMCCR_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup CLK_Registers_Bits_Definition + * @{ + */ + +#define CLK_ICKR_SWUAH ((u8)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */ +#define CLK_ICKR_LSIRDY ((u8)0x10) /*!< Low speed internal oscillator ready */ +#define CLK_ICKR_LSIEN ((u8)0x08) /*!< Low speed internal RC oscillator enable */ +#define CLK_ICKR_FHWU ((u8)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */ +#define CLK_ICKR_HSIRDY ((u8)0x02) /*!< High speed internal RC oscillator ready */ +#define CLK_ICKR_HSIEN ((u8)0x01) /*!< High speed internal RC oscillator enable */ + +#define CLK_ECKR_HSERDY ((u8)0x02) /*!< High speed external crystal oscillator ready */ +#define CLK_ECKR_HSEEN ((u8)0x01) /*!< High speed external crystal oscillator enable */ + +#define CLK_CMSR_CKM ((u8)0xFF) /*!< Clock master status bits */ + +#define CLK_SWR_SWI ((u8)0xFF) /*!< Clock master selection bits */ + +#define CLK_SWCR_SWIF ((u8)0x08) /*!< Clock switch interrupt flag */ +#define CLK_SWCR_SWIEN ((u8)0x04) /*!< Clock switch interrupt enable */ +#define CLK_SWCR_SWEN ((u8)0x02) /*!< Switch start/stop */ +#define CLK_SWCR_SWBSY ((u8)0x01) /*!< Switch busy */ + +#define CLK_CKDIVR_HSIDIV ((u8)0x18) /*!< High speed internal clock prescaler */ +#define CLK_CKDIVR_CPUDIV ((u8)0x07) /*!< CPU clock prescaler */ + +#define CLK_PCKENR1_TIM1 ((u8)0x80) /*!< Timer 1 clock enable */ +#define CLK_PCKENR1_TIM3 ((u8)0x40) /*!< Timer 3 clock enable */ +#define CLK_PCKENR1_TIM2 ((u8)0x20) /*!< Timer 2 clock enable */ +#define CLK_PCKENR1_TIM5 ((u8)0x20) /*!< Timer 5 clock enable */ +#define CLK_PCKENR1_TIM4 ((u8)0x10) /*!< Timer 4 clock enable */ +#define CLK_PCKENR1_TIM6 ((u8)0x10) /*!< Timer 6 clock enable */ +#define CLK_PCKENR1_UART3 ((u8)0x08) /*!< UART3 clock enable */ +#define CLK_PCKENR1_UART2 ((u8)0x08) /*!< UART2 clock enable */ +#define CLK_PCKENR1_UART1 ((u8)0x04) /*!< UART1 clock enable */ +#define CLK_PCKENR1_SPI ((u8)0x02) /*!< SPI clock enable */ +#define CLK_PCKENR1_I2C ((u8)0x01) /*!< I2C clock enable */ + +#define CLK_PCKENR2_CAN ((u8)0x80) /*!< CAN clock enable */ +#define CLK_PCKENR2_ADC ((u8)0x08) /*!< ADC clock enable */ +#define CLK_PCKENR2_AWU ((u8)0x04) /*!< AWU clock enable */ + +#define CLK_CSSR_CSSD ((u8)0x08) /*!< Clock security sytem detection */ +#define CLK_CSSR_CSSDIE ((u8)0x04) /*!< Clock security system detection interrupt enable */ +#define CLK_CSSR_AUX ((u8)0x02) /*!< Auxiliary oscillator connected to master clock */ +#define CLK_CSSR_CSSEN ((u8)0x01) /*!< Clock security system enable */ + +#define CLK_CCOR_CCOBSY ((u8)0x40) /*!< Configurable clock output busy */ +#define CLK_CCOR_CCORDY ((u8)0x20) /*!< Configurable clock output ready */ +#define CLK_CCOR_CCOSEL ((u8)0x1E) /*!< Configurable clock output selection */ +#define CLK_CCOR_CCOEN ((u8)0x01) /*!< Configurable clock output enable */ + +#define CLK_CANCCR_CANDIV ((u8)0x07) /*!< External CAN clock divider */ + +#define CLK_HSITRIMR_HSITRIM ((u8)0x07) /*!< High speed internal oscillator trimmer */ + +#define CLK_SWIMCCR_SWIMDIV ((u8)0x01) /*!< SWIM Clock Dividing Factor */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer with complementary PWM outputs (TIM1) + */ + +typedef struct TIM1_struct +{ + vu8 CR1; /*!< control register 1 */ + vu8 CR2; /*!< control register 2 */ + vu8 SMCR; /*!< Synchro mode control register */ + vu8 ETR; /*!< external trigger register */ + vu8 IER; /*!< interrupt enable register*/ + vu8 SR1; /*!< status register 1 */ + vu8 SR2; /*!< status register 2 */ + vu8 EGR; /*!< event generation register */ + vu8 CCMR1; /*!< CC mode register 1 */ + vu8 CCMR2; /*!< CC mode register 2 */ + vu8 CCMR3; /*!< CC mode register 3 */ + vu8 CCMR4; /*!< CC mode register 4 */ + vu8 CCER1; /*!< CC enable register 1 */ + vu8 CCER2; /*!< CC enable register 2 */ + vu8 CNTRH; /*!< counter high */ + vu8 CNTRL; /*!< counter low */ + vu8 PSCRH; /*!< prescaler high */ + vu8 PSCRL; /*!< prescaler low */ + vu8 ARRH; /*!< auto-reload register high */ + vu8 ARRL; /*!< auto-reload register low */ + vu8 RCR; /*!< Repetition Counter register */ + vu8 CCR1H; /*!< capture/compare register 1 high */ + vu8 CCR1L; /*!< capture/compare register 1 low */ + vu8 CCR2H; /*!< capture/compare register 2 high */ + vu8 CCR2L; /*!< capture/compare register 2 low */ + vu8 CCR3H; /*!< capture/compare register 3 high */ + vu8 CCR3L; /*!< capture/compare register 3 low */ + vu8 CCR4H; /*!< capture/compare register 3 high */ + vu8 CCR4L; /*!< capture/compare register 3 low */ + vu8 BKR; /*!< Break Register */ + vu8 DTR; /*!< dead-time register */ + vu8 OISR; /*!< Output idle register */ +} +TIM1_TypeDef; + +/** @addtogroup TIM1_Registers_Reset_Value + * @{ + */ + +#define TIM1_CR1_RESET_VALUE ((u8)0x00) +#define TIM1_CR2_RESET_VALUE ((u8)0x00) +#define TIM1_SMCR_RESET_VALUE ((u8)0x00) +#define TIM1_ETR_RESET_VALUE ((u8)0x00) +#define TIM1_IER_RESET_VALUE ((u8)0x00) +#define TIM1_SR1_RESET_VALUE ((u8)0x00) +#define TIM1_SR2_RESET_VALUE ((u8)0x00) +#define TIM1_EGR_RESET_VALUE ((u8)0x00) +#define TIM1_CCMR1_RESET_VALUE ((u8)0x00) +#define TIM1_CCMR2_RESET_VALUE ((u8)0x00) +#define TIM1_CCMR3_RESET_VALUE ((u8)0x00) +#define TIM1_CCMR4_RESET_VALUE ((u8)0x00) +#define TIM1_CCER1_RESET_VALUE ((u8)0x00) +#define TIM1_CCER2_RESET_VALUE ((u8)0x00) +#define TIM1_CNTRH_RESET_VALUE ((u8)0x00) +#define TIM1_CNTRL_RESET_VALUE ((u8)0x00) +#define TIM1_PSCRH_RESET_VALUE ((u8)0x00) +#define TIM1_PSCRL_RESET_VALUE ((u8)0x00) +#define TIM1_ARRH_RESET_VALUE ((u8)0xFF) +#define TIM1_ARRL_RESET_VALUE ((u8)0xFF) +#define TIM1_RCR_RESET_VALUE ((u8)0x00) +#define TIM1_CCR1H_RESET_VALUE ((u8)0x00) +#define TIM1_CCR1L_RESET_VALUE ((u8)0x00) +#define TIM1_CCR2H_RESET_VALUE ((u8)0x00) +#define TIM1_CCR2L_RESET_VALUE ((u8)0x00) +#define TIM1_CCR3H_RESET_VALUE ((u8)0x00) +#define TIM1_CCR3L_RESET_VALUE ((u8)0x00) +#define TIM1_CCR4H_RESET_VALUE ((u8)0x00) +#define TIM1_CCR4L_RESET_VALUE ((u8)0x00) +#define TIM1_BKR_RESET_VALUE ((u8)0x00) +#define TIM1_DTR_RESET_VALUE ((u8)0x00) +#define TIM1_OISR_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup TIM1_Registers_Bits_Definition + * @{ + */ +/* CR1*/ +#define TIM1_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM1_CR1_CMS ((u8)0x60) /*!< Center-aligned Mode Selection mask. */ +#define TIM1_CR1_DIR ((u8)0x10) /*!< Direction mask. */ +#define TIM1_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */ +#define TIM1_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */ +#define TIM1_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */ +#define TIM1_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */ +/* CR2*/ +#define TIM1_CR2_TI1S ((u8)0x80) /*!< TI1S Selection mask. */ +#define TIM1_CR2_MMS ((u8)0x70) /*!< MMS Selection mask. */ +#define TIM1_CR2_COMS ((u8)0x04) /*!< Capture/Compare Control Update Selection mask. */ +#define TIM1_CR2_CCPC ((u8)0x01) /*!< Capture/Compare Preloaded Control mask. */ +/* SMCR*/ +#define TIM1_SMCR_MSM ((u8)0x80) /*!< Master/Slave Mode mask. */ +#define TIM1_SMCR_TS ((u8)0x70) /*!< Trigger Selection mask. */ +#define TIM1_SMCR_SMS ((u8)0x07) /*!< Slave Mode Selection mask. */ +/*ETR*/ +#define TIM1_ETR_ETP ((u8)0x80) /*!< External Trigger Polarity mask. */ +#define TIM1_ETR_ECE ((u8)0x40)/*!< External Clock mask. */ +#define TIM1_ETR_ETPS ((u8)0x30) /*!< External Trigger Prescaler mask. */ +#define TIM1_ETR_ETF ((u8)0x0F) /*!< External Trigger Filter mask. */ +/*IER*/ +#define TIM1_IER_BIE ((u8)0x80) /*!< Break Interrupt Enable mask. */ +#define TIM1_IER_TIE ((u8)0x40) /*!< Trigger Interrupt Enable mask. */ +#define TIM1_IER_COMIE ((u8)0x20) /*!< Commutation Interrupt Enable mask.*/ +#define TIM1_IER_CC4IE ((u8)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */ +#define TIM1_IER_CC3IE ((u8)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ +#define TIM1_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ +#define TIM1_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ +#define TIM1_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM1_SR1_BIF ((u8)0x80) /*!< Break Interrupt Flag mask. */ +#define TIM1_SR1_TIF ((u8)0x40) /*!< Trigger Interrupt Flag mask. */ +#define TIM1_SR1_COMIF ((u8)0x20) /*!< Commutation Interrupt Flag mask. */ +#define TIM1_SR1_CC4IF ((u8)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */ +#define TIM1_SR1_CC3IF ((u8)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ +#define TIM1_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ +#define TIM1_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ +#define TIM1_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */ +/*SR2*/ +#define TIM1_SR2_CC4OF ((u8)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */ +#define TIM1_SR2_CC3OF ((u8)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ +#define TIM1_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ +#define TIM1_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ +/*EGR*/ +#define TIM1_EGR_BG ((u8)0x80) /*!< Break Generation mask. */ +#define TIM1_EGR_TG ((u8)0x40) /*!< Trigger Generation mask. */ +#define TIM1_EGR_COMG ((u8)0x20) /*!< Capture/Compare Control Update Generation mask. */ +#define TIM1_EGR_CC4G ((u8)0x10) /*!< Capture/Compare 4 Generation mask. */ +#define TIM1_EGR_CC3G ((u8)0x08) /*!< Capture/Compare 3 Generation mask. */ +#define TIM1_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */ +#define TIM1_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */ +#define TIM1_EGR_UG ((u8)0x01) /*!< Update Generation mask. */ +/*CCMR*/ +#define TIM1_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */ +#define TIM1_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */ +#define TIM1_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */ +#define TIM1_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */ +#define TIM1_CCMR_OCxFE ((u8)0x04) /*!< Output Compare x Fast Enable mask. */ +#define TIM1_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */ + +#define CCMR_TIxDirect_Set ((u8)0x01) +/*CCER1*/ +#define TIM1_CCER1_CC2NP ((u8)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */ +#define TIM1_CCER1_CC2NE ((u8)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */ +#define TIM1_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */ +#define TIM1_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */ +#define TIM1_CCER1_CC1NP ((u8)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */ +#define TIM1_CCER1_CC1NE ((u8)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */ +#define TIM1_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */ +#define TIM1_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */ +/*CCER2*/ +#define TIM1_CCER2_CC4P ((u8)0x20) /*!< Capture/Compare 4 output Polarity mask. */ +#define TIM1_CCER2_CC4E ((u8)0x10) /*!< Capture/Compare 4 output enable mask. */ +#define TIM1_CCER2_CC3NP ((u8)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */ +#define TIM1_CCER2_CC3NE ((u8)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */ +#define TIM1_CCER2_CC3P ((u8)0x02) /*!< Capture/Compare 3 output Polarity mask. */ +#define TIM1_CCER2_CC3E ((u8)0x01) /*!< Capture/Compare 3 output enable mask. */ +/*CNTRH*/ +#define TIM1_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */ +/*CNTRL*/ +#define TIM1_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCH*/ +#define TIM1_PSCH_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */ +/*PSCL*/ +#define TIM1_PSCL_PSC ((u8)0xFF) /*!< Prescaler Value (LSB) mask. */ +/*ARR*/ +#define TIM1_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */ +#define TIM1_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */ +/*RCR*/ +#define TIM1_RCR_REP ((u8)0xFF) /*!< Repetition Counter Value mask. */ +/*CCR1*/ +#define TIM1_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ +#define TIM1_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ +/*CCR2*/ +#define TIM1_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ +#define TIM1_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ +/*CCR3*/ +#define TIM1_CCR3H_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ +#define TIM1_CCR3L_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ +/*CCR4*/ +#define TIM1_CCR4H_CCR4 ((u8)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */ +#define TIM1_CCR4L_CCR4 ((u8)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */ +/*BKR*/ +#define TIM1_BKR_MOE ((u8)0x80) /*!< Main Output Enable mask. */ +#define TIM1_BKR_AOE ((u8)0x40) /*!< Automatic Output Enable mask. */ +#define TIM1_BKR_BKP ((u8)0x20) /*!< Break Polarity mask. */ +#define TIM1_BKR_BKE ((u8)0x10) /*!< Break Enable mask. */ +#define TIM1_BKR_OSSR ((u8)0x08) /*!< Off-State Selection for Run mode mask. */ +#define TIM1_BKR_OSSI ((u8)0x04) /*!< Off-State Selection for Idle mode mask. */ +#define TIM1_BKR_LOCK ((u8)0x03) /*!< Lock Configuration mask. */ +/*DTR*/ +#define TIM1_DTR_DTG ((u8)0xFF) /*!< Dead-Time Generator set-up mask. */ +/*OISR*/ +#define TIM1_OISR_OIS4 ((u8)0x40) /*!< Output Idle state 4 (OC4 output) mask. */ +#define TIM1_OISR_OIS3N ((u8)0x20) /*!< Output Idle state 3 (OC3N output) mask. */ +#define TIM1_OISR_OIS3 ((u8)0x10) /*!< Output Idle state 3 (OC3 output) mask. */ +#define TIM1_OISR_OIS2N ((u8)0x08) /*!< Output Idle state 2 (OC2N output) mask. */ +#define TIM1_OISR_OIS2 ((u8)0x04) /*!< Output Idle state 2 (OC2 output) mask. */ +#define TIM1_OISR_OIS1N ((u8)0x02) /*!< Output Idle state 1 (OC1N output) mask. */ +#define TIM1_OISR_OIS1 ((u8)0x01) /*!< Output Idle state 1 (OC1 output) mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer (TIM2) + */ + +typedef struct TIM2_struct +{ + vu8 CR1; /*!< control register 1 */ +#if defined STM8S103 + vu8 RESERVED1; /*!< Reserved register */ + vu8 RESERVED2; /*!< Reserved register */ +#endif + vu8 IER; /*!< interrupt enable register */ + vu8 SR1; /*!< status register 1 */ + vu8 SR2; /*!< status register 2 */ + vu8 EGR; /*!< event generation register */ + vu8 CCMR1; /*!< CC mode register 1 */ + vu8 CCMR2; /*!< CC mode register 2 */ + vu8 CCMR3; /*!< CC mode register 3 */ + vu8 CCER1; /*!< CC enable register 1 */ + vu8 CCER2; /*!< CC enable register 2 */ + vu8 CNTRH; /*!< counter high */ + vu8 CNTRL; /*!< counter low */ + vu8 PSCR; /*!< prescaler register */ + vu8 ARRH; /*!< auto-reload register high */ + vu8 ARRL; /*!< auto-reload register low */ + vu8 CCR1H; /*!< capture/compare register 1 high */ + vu8 CCR1L; /*!< capture/compare register 1 low */ + vu8 CCR2H; /*!< capture/compare register 2 high */ + vu8 CCR2L; /*!< capture/compare register 2 low */ + vu8 CCR3H; /*!< capture/compare register 3 high */ + vu8 CCR3L; /*!< capture/compare register 3 low */ +} +TIM2_TypeDef; + +/** @addtogroup TIM2_Registers_Reset_Value + * @{ + */ + +#define TIM2_CR1_RESET_VALUE ((u8)0x00) +#define TIM2_IER_RESET_VALUE ((u8)0x00) +#define TIM2_SR1_RESET_VALUE ((u8)0x00) +#define TIM2_SR2_RESET_VALUE ((u8)0x00) +#define TIM2_EGR_RESET_VALUE ((u8)0x00) +#define TIM2_CCMR1_RESET_VALUE ((u8)0x00) +#define TIM2_CCMR2_RESET_VALUE ((u8)0x00) +#define TIM2_CCMR3_RESET_VALUE ((u8)0x00) +#define TIM2_CCER1_RESET_VALUE ((u8)0x00) +#define TIM2_CCER2_RESET_VALUE ((u8)0x00) +#define TIM2_CNTRH_RESET_VALUE ((u8)0x00) +#define TIM2_CNTRL_RESET_VALUE ((u8)0x00) +#define TIM2_PSCR_RESET_VALUE ((u8)0x00) +#define TIM2_ARRH_RESET_VALUE ((u8)0xFF) +#define TIM2_ARRL_RESET_VALUE ((u8)0xFF) +#define TIM2_CCR1H_RESET_VALUE ((u8)0x00) +#define TIM2_CCR1L_RESET_VALUE ((u8)0x00) +#define TIM2_CCR2H_RESET_VALUE ((u8)0x00) +#define TIM2_CCR2L_RESET_VALUE ((u8)0x00) +#define TIM2_CCR3H_RESET_VALUE ((u8)0x00) +#define TIM2_CCR3L_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup TIM2_Registers_Bits_Definition + * @{ + */ +/*CR1*/ +#define TIM2_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM2_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */ +#define TIM2_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */ +#define TIM2_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */ +#define TIM2_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */ +/*IER*/ +#define TIM2_IER_CC3IE ((u8)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ +#define TIM2_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ +#define TIM2_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ +#define TIM2_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM2_SR1_CC3IF ((u8)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ +#define TIM2_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ +#define TIM2_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ +#define TIM2_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */ +/*SR2*/ +#define TIM2_SR2_CC3OF ((u8)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ +#define TIM2_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ +#define TIM2_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ +/*EGR*/ +#define TIM2_EGR_CC3G ((u8)0x08) /*!< Capture/Compare 3 Generation mask. */ +#define TIM2_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */ +#define TIM2_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */ +#define TIM2_EGR_UG ((u8)0x01) /*!< Update Generation mask. */ +/*CCMR*/ +#define TIM2_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */ +#define TIM2_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */ +#define TIM2_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */ +#define TIM2_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */ +#define TIM2_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */ +/*CCER1*/ +#define TIM2_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */ +#define TIM2_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */ +#define TIM2_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */ +#define TIM2_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */ +/*CCER2*/ +#define TIM2_CCER2_CC3P ((u8)0x02) /*!< Capture/Compare 3 output Polarity mask. */ +#define TIM2_CCER2_CC3E ((u8)0x01) /*!< Capture/Compare 3 output enable mask. */ +/*CNTR*/ +#define TIM2_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */ +#define TIM2_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCR*/ +#define TIM2_PSCR_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */ +/*ARR*/ +#define TIM2_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */ +#define TIM2_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */ +/*CCR1*/ +#define TIM2_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ +#define TIM2_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ +/*CCR2*/ +#define TIM2_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ +#define TIM2_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ +/*CCR3*/ +#define TIM2_CCR3H_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ +#define TIM2_CCR3L_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer (TIM3) + */ +typedef struct TIM3_struct +{ + vu8 CR1; /*!< control register 1 */ + vu8 IER; /*!< interrupt enable register */ + vu8 SR1; /*!< status register 1 */ + vu8 SR2; /*!< status register 2 */ + vu8 EGR; /*!< event generation register */ + vu8 CCMR1; /*!< CC mode register 1 */ + vu8 CCMR2; /*!< CC mode register 2 */ + vu8 CCER1; /*!< CC enable register 1 */ + vu8 CNTRH; /*!< counter high */ + vu8 CNTRL; /*!< counter low */ + vu8 PSCR; /*!< prescaler register */ + vu8 ARRH; /*!< auto-reload register high */ + vu8 ARRL; /*!< auto-reload register low */ + vu8 CCR1H; /*!< capture/compare register 1 high */ + vu8 CCR1L; /*!< capture/compare register 1 low */ + vu8 CCR2H; /*!< capture/compare register 2 high */ + vu8 CCR2L; /*!< capture/compare register 2 low */ +} +TIM3_TypeDef; + +/** @addtogroup TIM3_Registers_Reset_Value + * @{ + */ + +#define TIM3_CR1_RESET_VALUE ((u8)0x00) +#define TIM3_IER_RESET_VALUE ((u8)0x00) +#define TIM3_SR1_RESET_VALUE ((u8)0x00) +#define TIM3_SR2_RESET_VALUE ((u8)0x00) +#define TIM3_EGR_RESET_VALUE ((u8)0x00) +#define TIM3_CCMR1_RESET_VALUE ((u8)0x00) +#define TIM3_CCMR2_RESET_VALUE ((u8)0x00) +#define TIM3_CCER1_RESET_VALUE ((u8)0x00) +#define TIM3_CNTRH_RESET_VALUE ((u8)0x00) +#define TIM3_CNTRL_RESET_VALUE ((u8)0x00) +#define TIM3_PSCR_RESET_VALUE ((u8)0x00) +#define TIM3_ARRH_RESET_VALUE ((u8)0xFF) +#define TIM3_ARRL_RESET_VALUE ((u8)0xFF) +#define TIM3_CCR1H_RESET_VALUE ((u8)0x00) +#define TIM3_CCR1L_RESET_VALUE ((u8)0x00) +#define TIM3_CCR2H_RESET_VALUE ((u8)0x00) +#define TIM3_CCR2L_RESET_VALUE ((u8)0x00) + +/** + * @} + */ + +/** @addtogroup TIM3_Registers_Bits_Definition + * @{ + */ +/*CR1*/ +#define TIM3_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM3_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */ +#define TIM3_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */ +#define TIM3_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */ +#define TIM3_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */ +/*IER*/ +#define TIM3_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ +#define TIM3_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ +#define TIM3_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM3_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ +#define TIM3_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ +#define TIM3_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */ +/*SR2*/ +#define TIM3_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ +#define TIM3_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ +/*EGR*/ +#define TIM3_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */ +#define TIM3_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */ +#define TIM3_EGR_UG ((u8)0x01) /*!< Update Generation mask. */ +/*CCMR*/ +#define TIM3_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */ +#define TIM3_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */ +#define TIM3_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */ +#define TIM3_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */ +#define TIM3_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */ +/*CCER1*/ +#define TIM3_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */ +#define TIM3_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */ +#define TIM3_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */ +#define TIM3_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */ +/*CNTR*/ +#define TIM3_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */ +#define TIM3_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCR*/ +#define TIM3_PSCR_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */ +/*ARR*/ +#define TIM3_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */ +#define TIM3_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */ +/*CCR1*/ +#define TIM3_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ +#define TIM3_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ +/*CCR2*/ +#define TIM3_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ +#define TIM3_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 8-bit system timer (TIM4) + */ + +typedef struct TIM4_struct +{ + vu8 CR1; /*!< control register 1 */ +#if defined STM8S103 + vu8 RESERVED1; /*!< Reserved register */ + vu8 RESERVED2; /*!< Reserved register */ +#endif + vu8 IER; /*!< interrupt enable register */ + vu8 SR1; /*!< status register 1 */ + vu8 EGR; /*!< event generation register */ + vu8 CNTR; /*!< counter register */ + vu8 PSCR; /*!< prescaler register */ + vu8 ARR; /*!< auto-reload register */ +} +TIM4_TypeDef; + +/** @addtogroup TIM4_Registers_Reset_Value + * @{ + */ + +#define TIM4_CR1_RESET_VALUE ((u8)0x00) +#define TIM4_IER_RESET_VALUE ((u8)0x00) +#define TIM4_SR1_RESET_VALUE ((u8)0x00) +#define TIM4_EGR_RESET_VALUE ((u8)0x00) +#define TIM4_CNTR_RESET_VALUE ((u8)0x00) +#define TIM4_PSCR_RESET_VALUE ((u8)0x00) +#define TIM4_ARR_RESET_VALUE ((u8)0xFF) + +/** + * @} + */ + +/** @addtogroup TIM4_Registers_Bits_Definition + * @{ + */ +/*CR1*/ +#define TIM4_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */ +#define TIM4_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */ +#define TIM4_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */ +#define TIM4_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */ +#define TIM4_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */ +/*IER*/ +#define TIM4_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */ +/*SR1*/ +#define TIM4_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */ +/*EGR*/ +#define TIM4_EGR_UG ((u8)0x01) /*!< Update Generation mask. */ +/*CNTR*/ +#define TIM4_CNTR_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */ +/*PSCR*/ +#define TIM4_PSCR_PSC ((u8)0x07) /*!< Prescaler Value mask. */ +/*ARR*/ +#define TIM4_ARR_ARR ((u8)0xFF) /*!< Autoreload Value mask. */ + +/** + * @} + */ + +/*----------------------------------------------------------------------------*/ +/** + * @brief 16-bit timer with synchro module (TIM5) + */ + +typedef struct TIM5_struct +{ + vu8 CR1; /*! + #define enableInterrupts() _rim_() /* enable interrupts */ + #define disableInterrupts() _sim_() /* disable interrupts */ + #define rim() _rim_() /* enable interrupts */ + #define sim() _sim_() /* disable interrupts */ + #define nop() _nop_() /* No Operation */ + #define trap() _trap_() /* Trap (soft IT) */ + #define wfi() _wfi_() /* Wait For Interrupt */ + #define halt() _halt_() /* Halt */ +#else /* COSMIC */ + #define enableInterrupts() {_asm("rim\n");} /* enable interrupts */ + #define disableInterrupts() {_asm("sim\n");} /* disable interrupts */ + #define rim() {_asm("rim\n");} /* enable interrupts */ + #define sim() {_asm("sim\n");} /* disable interrupts */ + #define nop() {_asm("nop\n");} /* No Operation */ + #define trap() {_asm("trap\n");} /* Trap (soft IT) */ + #define wfi() {_asm("wfi\n");} /* Wait For Interrupt */ + #define halt() {_asm("halt\n");} /* Halt */ +#endif + +/*============================== Handling bits ====================================*/ +/*----------------------------------------------------------------------------- +Method : I +Description : Handle the bit from the character variables. +Comments : The different parameters of commands are + - VAR : Name of the character variable where the bit is located. + - Place : Bit position in the variable (7 6 5 4 3 2 1 0) + - Value : Can be 0 (reset bit) or not 0 (set bit) + The "MskBit" command allows to select some bits in a source + variables and copy it in a destination var (return the value). + The "ValBit" command returns the value of a bit in a char + variable: the bit is reseted if it returns 0 else the bit is set. + This method generates not an optimised code yet. +-----------------------------------------------------------------------------*/ +#define SetBit(VAR,Place) ( (VAR) |= (u8)((u8)1<<(u8)(Place)) ) +#define ClrBit(VAR,Place) ( (VAR) &= (u8)((u8)((u8)1<<(u8)(Place))^(u8)255) ) + +#define ChgBit(VAR,Place) ( (VAR) ^= (u8)((u8)1<<(u8)(Place)) ) +#define AffBit(VAR,Place,Value) ((Value) ? \ + ((VAR) |= ((u8)1<<(Place))) : \ + ((VAR) &= (((u8)1<<(Place))^(u8)255))) +#define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) ) + +#define ValBit(VAR,Place) ((u8)(VAR) & (u8)((u8)1<<(u8)(Place))) + +#define BYTE_0(n) ((u8)((n) & (u8)0xFF)) /*!< Returns the low byte of the 32-bit value */ +#define BYTE_1(n) ((u8)(BYTE_0((n) >> (u8)8))) /*!< Returns the second byte of the 32-bit value */ +#define BYTE_2(n) ((u8)(BYTE_0((n) >> (u8)16))) /*!< Returns the third byte of the 32-bit value */ +#define BYTE_3(n) ((u8)(BYTE_0((n) >> (u8)24))) /*!< Returns the high byte of the 32-bit value */ + +/*============================== Assert Macros ====================================*/ +#define IS_STATE_VALUE_OK(SensitivityValue) \ + (((SensitivityValue) == ENABLE) || \ + ((SensitivityValue) == DISABLE)) + +/*----------------------------------------------------------------------------- +Method : II +Description : Handle directly the bit. +Comments : The idea is to handle directly with the bit name. For that, it is + necessary to have RAM area descriptions (example: HW register...) + and the following command line for each area. + This method generates the most optimized code. +-----------------------------------------------------------------------------*/ + +#define AREA 0x00 /* The area of bits begins at address 0x10. */ + +#define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) ) +#define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) ) +#define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) ) + +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM8S_H */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ diff --git a/os/hal/platforms/STM8S/stm8s_type.h b/os/hal/platforms/STM8S/stm8s_type.h new file mode 100644 index 000000000..5c80f6687 --- /dev/null +++ b/os/hal/platforms/STM8S/stm8s_type.h @@ -0,0 +1,103 @@ +/** + ****************************************************************************** + * @file stm8s_type.h + * @brief This file contains all common data types. + * @author STMicroelectronics - MCD Application Team + * @version V1.1.1 + * @date 06/05/2009 + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2009 STMicroelectronics

+ * @image html logo.bmp + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM8S_TYPE_H +#define __STM8S_TYPE_H + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +typedef signed long s32; +typedef signed short s16; +typedef signed char s8; + +typedef signed long const sc32; /* Read Only */ +typedef signed short const sc16; /* Read Only */ +typedef signed char const sc8; /* Read Only */ + +typedef volatile signed long vs32; +typedef volatile signed short vs16; +typedef volatile signed char vs8; + +typedef volatile signed long const vsc32; /* Read Only */ +typedef volatile signed short const vsc16; /* Read Only */ +typedef volatile signed char const vsc8; /* Read Only */ + +typedef unsigned long u32; +typedef unsigned short u16; +typedef unsigned char u8; + +typedef unsigned long const uc32; /* Read Only */ +typedef unsigned short const uc16; /* Read Only */ +typedef unsigned char const uc8; /* Read Only */ + +typedef volatile unsigned long vu32; +typedef volatile unsigned short vu16; +typedef volatile unsigned char vu8; + +typedef volatile unsigned long const vuc32; /* Read Only */ +typedef volatile unsigned short const vuc16; /* Read Only */ +typedef volatile unsigned char const vuc8; /* Read Only */ + +typedef enum +{ + FALSE = 0, + TRUE = !FALSE +} +bool; + +typedef enum { + RESET = 0, + SET = !RESET +} +FlagStatus, ITStatus, BitStatus; + +typedef enum { + DISABLE = 0, + ENABLE = !DISABLE +} +FunctionalState; + +#define IS_FUNCTIONALSTATE_OK(VALUE) ( (VALUE == ENABLE) || (VALUE == DISABLE) ) + +typedef enum { + ERROR = 0, + SUCCESS = !ERROR +} +ErrorStatus; + +#define U8_MAX ((u8)255) +#define S8_MAX ((s8)127) +#define S8_MIN ((s8)-128) +#define U16_MAX ((u16)65535u) +#define S16_MAX ((s16)32767) +#define S16_MIN ((s16)-32768) +#define U32_MAX ((u32)4294967295uL) +#define S32_MAX ((s32)2147483647) +#define S32_MIN ((s32)-2147483648) + +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +#endif /* __STM8S_TYPE_H */ + +/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3