From 8ca210a4af9fd039e290cfcc309adde543999c1f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 9 Aug 2013 08:24:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6108 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM8L/hal_lld.c | 123 -- os/hal/platforms/STM8L/hal_lld.h | 282 --- os/hal/platforms/STM8L/hal_lld_stm8l_hd.h | 78 - os/hal/platforms/STM8L/hal_lld_stm8l_md.h | 78 - os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h | 78 - os/hal/platforms/STM8L/pal_lld.c | 105 - os/hal/platforms/STM8L/pal_lld.h | 244 --- os/hal/platforms/STM8L/platform.dox | 99 - os/hal/platforms/STM8L/serial_lld.c | 209 -- os/hal/platforms/STM8L/serial_lld.h | 270 --- os/hal/platforms/STM8L/shared_isr.c | 188 -- os/hal/platforms/STM8L/stm8l15x.h | 3000 ---------------------------- 12 files changed, 4754 deletions(-) delete mode 100644 os/hal/platforms/STM8L/hal_lld.c delete mode 100644 os/hal/platforms/STM8L/hal_lld.h delete mode 100644 os/hal/platforms/STM8L/hal_lld_stm8l_hd.h delete mode 100644 os/hal/platforms/STM8L/hal_lld_stm8l_md.h delete mode 100644 os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h delete mode 100644 os/hal/platforms/STM8L/pal_lld.c delete mode 100644 os/hal/platforms/STM8L/pal_lld.h delete mode 100644 os/hal/platforms/STM8L/platform.dox delete mode 100644 os/hal/platforms/STM8L/serial_lld.c delete mode 100644 os/hal/platforms/STM8L/serial_lld.h delete mode 100644 os/hal/platforms/STM8L/shared_isr.c delete mode 100644 os/hal/platforms/STM8L/stm8l15x.h (limited to 'os/hal/platforms/STM8L') diff --git a/os/hal/platforms/STM8L/hal_lld.c b/os/hal/platforms/STM8L/hal_lld.c deleted file mode 100644 index 06e6ad981..000000000 --- a/os/hal/platforms/STM8L/hal_lld.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM8L/hal_lld.c - * @brief STM8L HAL subsystem low level driver source. - * - * @addtogroup HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - * @details Clock sources initialization, HSI is assumed to be already - * started after reset. - * @note If the @p STM8L_CLOCK_INIT option is set to @p FALSE then the - * initialization is not performed and is left to the application. - * - * @notapi - */ -void hal_lld_init(void) { - -#if !STM8L_NO_CLOCK_INIT - /* Makes sure that HSI is stable before proceeding.*/ - CLK->ICKCR |= CLK_ICKCR_HSION; - while ((CLK->ICKCR & CLK_ICKCR_HSIRDY) == 0) - ; - - /* LSI startup and stabilization if required.*/ -#if STM8L_LSI_ENABLED - CLK->ICKCR |= CLK_ICKCR_LSION; - while ((CLK->ICKCR & CLK_ICKCR_LSIRDY) == 0) - ; -#endif - - /* HSE startup and stabilization if required.*/ -#if STM8L_HSE_ENABLED -#if HSEBYPASS - CLK->ECKCR |= CLK_ECKCR_HSEON | CLK_ECKCR_HSEBYP; -#else - CLK->ECKCR |= CLK_ECKCR_HSEON; -#endif - while ((CLK->ECKCR & CLK_ECKCR_HSERDY) == 0) - ; -#endif - - /* LSE startup and stabilization if required.*/ -#if STM8L_LSE_ENABLED -#if LSEBYPASS - CLK->ECKCR |= CLK_ECKCR_LSEON | CLK_ECKCR_LSEBYP; -#else - CLK->ECKCR |= CLK_ECKCR_LSEON; -#endif - while ((CLK->ECKCR & CLK_ECKCR_LSERDY) == 0) - ; -#endif - - /* Setting up clock dividers.*/ - CLK->CKDIVR = STM8L_SYSCLK_DIVIDER << 0; - - /* SYSCLK switch to the selected source, not necessary if it is HSI.*/ -#if STM8L_SYSCLK_SOURCE != CLK_SYSSEL_HSI - /* Switching clock (manual switch mode).*/ - CLK->SWR = STM8L_SYSCLK_SOURCE; - while ((CLK->SWCR & CLK_SWCR_SWIF) == 0) - ; - CLK->SWCR = CLK_SWCR_SWEN; -#endif - - /* Clocks initially all disabled, note the boot ROM clock is disabled - because the boot loader is no more required and it draws precious uAs.*/ - CLK->PCKENR1 = 0; - CLK->PCKENR2 = 0; - CLK->PCKENR3 = 0; - - /* Other clock related initializations.*/ - CLK->CSSR = 0; - CLK->CCOR = 0; - - /* HSI disabled if it is no more required.*/ -#if !STM8L_HSI_ENABLED - CLK->ICKCR &= ~CLK_ICKCR_HSION; -#endif -#endif /* !STM8L_NO_CLOCK_INIT */ -} - -/** @} */ diff --git a/os/hal/platforms/STM8L/hal_lld.h b/os/hal/platforms/STM8L/hal_lld.h deleted file mode 100644 index 0f8ca6776..000000000 --- a/os/hal/platforms/STM8L/hal_lld.h +++ /dev/null @@ -1,282 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM8L/hal_lld.h - * @brief STM8L HAL subsystem low level driver source. - * @pre This module requires the following macros to be defined in the - * @p board.h file: - * - HSECLK (@p 0 if disabled or frequency in Hertz). - * - HSEBYPASS (@p TRUE if external oscillator rather than a crystal). - * - LSECLK (@p 0 if disabled or frequency in Hertz). - * - LSEBYPASS (@p TRUE if external oscillator rather than a crystal). - * . - * One of the following macros must also be defined: - * - STM8L15X_MD for Medium Density devices. - * - STM8L15X_MDP for Medium Density Plus devices. - * - STM8L15X_HD for High Density devices. - * . - * - * @addtogroup HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#undef FALSE -#undef TRUE -#include "stm8l15x.h" -#define FALSE 0 -#define TRUE (!FALSE) - -#if defined (STM8L15X_MD) -#include "hal_lld_stm8l_md.h" -#elif defined (STM8L15X_MDP) -#include "hal_lld_stm8l_mdp.h" -#elif defined (STM8L15X_HD) -#include "hal_lld_stm8l_hd.h" -#else -#error "unspecified, unsupported or invalid STM8L platform" -#endif - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Defines the support for realtime counters in the HAL. - */ -#define HAL_IMPLEMENTS_COUNTERS FALSE - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "STM8L" - -#define LSICLK 38000 /**< Low speed internal clock. */ -#define HSICLK 16000000 /**< High speed internal clock. */ - -#define CLK_SYSSEL_HSI 1 /**< HSI system clock selector. */ -#define CLK_SYSSEL_LSI 2 /**< LSI system clock selector. */ -#define CLK_SYSSEL_HSE 4 /**< HSE system clock selector. */ -#define CLK_SYSSEL_LSE 8 /**< LSE system clock selector. */ - -#define CLK_SYSCLK_DIV1 0 /**< Source clock divided by 1. */ -#define CLK_SYSCLK_DIV2 1 /**< Source clock divided by 2. */ -#define CLK_SYSCLK_DIV4 2 /**< Source clock divided by 4. */ -#define CLK_SYSCLK_DIV8 3 /**< Source clock divided by 8. */ -#define CLK_SYSCLK_DIV16 4 /**< Source clock divided by 16. */ -#define CLK_SYSCLK_DIV32 5 /**< Source clock divided by 32. */ -#define CLK_SYSCLK_DIV64 6 /**< Source clock divided by 64. */ -#define CLK_SYSCLK_DIV128 7 /**< Source clock divided by 128. */ - -#define CLK_RTCSEL_HSI 1 /**< HSI RTC clock selector. */ -#define CLK_RTCSEL_LSI 2 /**< LSI RTC clock selector. */ -#define CLK_RTCSEL_HSE 4 /**< HSE RTC clock selector. */ -#define CLK_RTCSEL_LSE 8 /**< LSE RTC clock selector. */ - -#define CLK_RTCCLK_DIV1 0 /**< Source clock divided by 1. */ -#define CLK_RTCCLK_DIV2 1 /**< Source clock divided by 2. */ -#define CLK_RTCCLK_DIV4 2 /**< Source clock divided by 4. */ -#define CLK_RTCCLK_DIV8 3 /**< Source clock divided by 8. */ -#define CLK_RTCCLK_DIV16 4 /**< Source clock divided by 16. */ -#define CLK_RTCCLK_DIV32 5 /**< Source clock divided by 32. */ -#define CLK_RTCCLK_DIV64 6 /**< Source clock divided by 64. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief Disables the clock initialization in the HAL. - */ -#if !defined(STM8L_NO_CLOCK_INIT) || defined(__DOXYGEN__) -#define STM8L_NO_CLOCK_INIT FALSE -#endif - -/** - * @brief Enables or disables the HSI clock source. - */ -#if !defined(STM8L_HSI_ENABLED) || defined(__DOXYGEN__) -#define STM8L_HSI_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the LSI clock source. - */ -#if !defined(STM8L_LSI_ENABLED) || defined(__DOXYGEN__) -#define STM8L_LSI_ENABLED TRUE -#endif - -/** - * @brief Enables or disables the HSE clock source. - */ -#if !defined(STM8L_HSE_ENABLED) || defined(__DOXYGEN__) -#define STM8L_HSE_ENABLED FALSE -#endif - -/** - * @brief Enables or disables the LSE clock source. - */ -#if !defined(STM8L_HSE_ENABLED) || defined(__DOXYGEN__) -#define STM8L_LSE_ENABLED FALSE -#endif - -/** - * @brief System clock source selection. - */ -#if !defined(STM8L_SYSCLK_SOURCE) || defined(__DOXYGEN__) -#define STM8L_SYSCLK_SOURCE CLK_SYSSEL_HSI -#endif - -/** - * @brief System clock divider. - */ -#if !defined(STM8L_SYSCLK_DIVIDER) || defined(__DOXYGEN__) -#define STM8L_SYSCLK_DIVIDER CLK_SYSCLK_DIV1 -#endif - -/** - * @brief RTC clock source selection. - */ -#if !defined(STM8L_RTCCLK_SOURCE) || defined(__DOXYGEN__) -#define STM8L_RTCCLK_SOURCE CLK_RTCSEL_HSI -#endif - -/** - * @brief RTC clock divider. - */ -#if !defined(STM8L_RTCCLK_DIVIDER) || defined(__DOXYGEN__) -#define STM8L_RTCCLK_DIVIDER CLK_RTCCLK_DIV1 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV1) && \ - (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV2) && \ - (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV4) && \ - (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV8) && \ - (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV16) && \ - (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV32) && \ - (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV64) && \ - (STM8L_SYSCLK_DIVIDER != CLK_SYSCLK_DIV128) -#error "specified invalid SYSCLK divider" -#endif - -#if (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV1) && \ - (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV2) && \ - (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV4) && \ - (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV8) && \ - (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV16) && \ - (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV32) && \ - (STM8L_RTCCLK_DIVIDER != CLK_RTCCLK_DIV64) -#error "specified invalid RTCCLK divider" -#endif - -#if STM8L_HSE_ENABLED && (HSECLK == 0) -#error "impossible to activate HSE" -#endif - -#if STM8L_LSE_ENABLED && (LSECLK == 0) -#error "impossible to activate LSE" -#endif - -#if !STM8L_HSI_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI) || \ - (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI)) -#error "requested HSI clock is not enabled" -#endif - -#if !STM8L_LSI_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSI) || \ - (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSI)) -#error "requested LSI clock is not enabled" -#endif - -#if !STM8L_HSE_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSE) || \ - (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSE)) -#error "requested HSE clock is not enabled" -#endif - -#if !STM8L_LSE_ENABLED && ((STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSE) || \ - (STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSE)) -#error "requested LSE clock is not enabled" -#endif - -/** - * @brief System clock. - */ -#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__) -#define SYSCLK (HSICLK / 8) -#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSI -#define SYSCLK (HSICLK / (1 << STM8L_SYSCLK_DIVIDER)) -#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSI -#define SYSCLK (LSICLK / (1 << STM8L_SYSCLK_DIVIDER)) -#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_HSE -#define SYSCLK (HSECLK / (1 << STM8L_SYSCLK_DIVIDER)) -#elif STM8L_SYSCLK_SOURCE == CLK_SYSSEL_LSE -#define SYSCLK (LSECLK / (1 << STM8L_SYSCLK_DIVIDER)) -#else -#error "specified invalid SYSCLK source" -#endif - -/** - * @brief RTC clock. - */ -#if STM8L_NO_CLOCK_INIT || defined(__DOXYGEN__) -#define RTCCLK 0 -#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSI -#define RTCCLK (HSICLK / (1 << STM8L_RTCCLK_DIVIDER)) -#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSI -#define RTCCLK (LSICLK / (1 << STM8L_RTCCLK_DIVIDER)) -#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_HSE -#define RTCCLK (HSECLK / (1 << STM8L_RTCCLK_DIVIDER)) -#elif STM8L_RTCCLK_SOURCE == CLK_RTCSEL_LSE -#define RTCCLK (LSECLK / (1 << STM8L_RTCCLK_DIVIDER)) -#else -#error "specified invalid RTCCLK source" -#endif - -/** - * @brief CPU clock. - * @details On the STM8L the CPU clock is always equal to the system clock. - */ -#define CPUCLK SYSCLK - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM8L/hal_lld_stm8l_hd.h b/os/hal/platforms/STM8L/hal_lld_stm8l_hd.h deleted file mode 100644 index 68a3211d8..000000000 --- a/os/hal/platforms/STM8L/hal_lld_stm8l_hd.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @defgroup STM8L_HD_HAL STM8L High Density sub-family - * - * @ingroup HAL - */ - -/** - * @file STM8L/hal_lld_stm8l_hd.h - * @brief STM8L High Density sub-family capabilities descriptor. - * - * @addtogroup STM8L_HD_HAL - * @{ - */ - -#ifndef _HAL_LLD_STM8L_HD_H_ -#define _HAL_LLD_STM8L_HD_H_ - -/*===========================================================================*/ -/* Sub-family capabilities. */ -/*===========================================================================*/ - -#define STM8L_HAS_ADC1 TRUE - -#define STM8L_HAS_BEEP TRUE - -#define STM8L_HAS_COMP1 TRUE -#define STM8L_HAS_COMP2 TRUE - -#define STM8L_HAS_DAC1 TRUE - -#define STM8L_HAS_DMA1 TRUE - -#define STM8L_HAS_GPIOA TRUE -#define STM8L_HAS_GPIOB TRUE -#define STM8L_HAS_GPIOC TRUE -#define STM8L_HAS_GPIOD TRUE -#define STM8L_HAS_GPIOE TRUE -#define STM8L_HAS_GPIOF TRUE -#define STM8L_HAS_GPIOG TRUE -#define STM8L_HAS_GPIOH TRUE -#define STM8L_HAS_GPIOI TRUE - -#define STM8L_HAS_I2C1 TRUE - -#define STM8L_HAS_LCD TRUE - -#define STM8L_HAS_SPI1 TRUE -#define STM8L_HAS_SPI2 TRUE - -#define STM8L_HAS_TIM1 TRUE -#define STM8L_HAS_TIM2 TRUE -#define STM8L_HAS_TIM3 TRUE -#define STM8L_HAS_TIM4 TRUE -#define STM8L_HAS_TIM5 TRUE - -#define STM8L_HAS_USART1 TRUE -#define STM8L_HAS_USART2 TRUE -#define STM8L_HAS_USART3 TRUE - -#endif /* _HAL_LLD_STM8L_HD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM8L/hal_lld_stm8l_md.h b/os/hal/platforms/STM8L/hal_lld_stm8l_md.h deleted file mode 100644 index 072a77dca..000000000 --- a/os/hal/platforms/STM8L/hal_lld_stm8l_md.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @defgroup STM8L_MD_HAL STM8L Medium Density sub-family - * - * @ingroup HAL - */ - -/** - * @file STM8L/hal_lld_stm8l_md.h - * @brief STM8L Medium Density sub-family capabilities descriptor. - * - * @addtogroup STM8L_MD_HAL - * @{ - */ - -#ifndef _HAL_LLD_STM8L_MD_H_ -#define _HAL_LLD_STM8L_MD_H_ - -/*===========================================================================*/ -/* Sub-family capabilities. */ -/*===========================================================================*/ - -#define STM8L_HAS_ADC1 TRUE - -#define STM8L_HAS_BEEP TRUE - -#define STM8L_HAS_COMP1 TRUE -#define STM8L_HAS_COMP2 TRUE - -#define STM8L_HAS_DAC1 TRUE - -#define STM8L_HAS_DMA1 TRUE - -#define STM8L_HAS_GPIOA TRUE -#define STM8L_HAS_GPIOB TRUE -#define STM8L_HAS_GPIOC TRUE -#define STM8L_HAS_GPIOD TRUE -#define STM8L_HAS_GPIOE TRUE -#define STM8L_HAS_GPIOF TRUE -#define STM8L_HAS_GPIOG FALSE -#define STM8L_HAS_GPIOH FALSE -#define STM8L_HAS_GPIOI FALSE - -#define STM8L_HAS_I2C1 TRUE - -#define STM8L_HAS_LCD TRUE - -#define STM8L_HAS_SPI1 TRUE -#define STM8L_HAS_SPI2 FALSE - -#define STM8L_HAS_TIM1 TRUE -#define STM8L_HAS_TIM2 TRUE -#define STM8L_HAS_TIM3 TRUE -#define STM8L_HAS_TIM4 TRUE -#define STM8L_HAS_TIM5 FALSE - -#define STM8L_HAS_USART1 TRUE -#define STM8L_HAS_USART2 FALSE -#define STM8L_HAS_USART3 FALSE - -#endif /* _HAL_LLD_STM8L_MD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h b/os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h deleted file mode 100644 index 83e0672c9..000000000 --- a/os/hal/platforms/STM8L/hal_lld_stm8l_mdp.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @defgroup STM8L_MDP_HAL STM8L Medium Density Plus sub-family - * - * @ingroup HAL - */ - -/** - * @file STM8L/hal_lld_stm8l_mdp.h - * @brief STM8L Medium Density Plus sub-family capabilities descriptor. - * - * @addtogroup STM8L_MDP_HAL - * @{ - */ - -#ifndef _HAL_LLD_STM8L_MDP_H_ -#define _HAL_LLD_STM8L_MDP_H_ - -/*===========================================================================*/ -/* Sub-family capabilities. */ -/*===========================================================================*/ - -#define STM8L_HAS_ADC1 TRUE - -#define STM8L_HAS_BEEP TRUE - -#define STM8L_HAS_COMP1 TRUE -#define STM8L_HAS_COMP2 TRUE - -#define STM8L_HAS_DAC1 TRUE - -#define STM8L_HAS_DMA1 TRUE - -#define STM8L_HAS_GPIOA TRUE -#define STM8L_HAS_GPIOB TRUE -#define STM8L_HAS_GPIOC TRUE -#define STM8L_HAS_GPIOD TRUE -#define STM8L_HAS_GPIOE TRUE -#define STM8L_HAS_GPIOF TRUE -#define STM8L_HAS_GPIOG TRUE -#define STM8L_HAS_GPIOH TRUE -#define STM8L_HAS_GPIOI TRUE - -#define STM8L_HAS_I2C1 TRUE - -#define STM8L_HAS_LCD TRUE - -#define STM8L_HAS_SPI1 TRUE -#define STM8L_HAS_SPI2 TRUE - -#define STM8L_HAS_TIM1 TRUE -#define STM8L_HAS_TIM2 TRUE -#define STM8L_HAS_TIM3 TRUE -#define STM8L_HAS_TIM4 TRUE -#define STM8L_HAS_TIM5 TRUE - -#define STM8L_HAS_USART1 TRUE -#define STM8L_HAS_USART2 TRUE -#define STM8L_HAS_USART3 TRUE - -#endif /* _HAL_LLD_STM8L_MDP_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM8L/pal_lld.c b/os/hal/platforms/STM8L/pal_lld.c deleted file mode 100644 index 1b83d8a8d..000000000 --- a/os/hal/platforms/STM8L/pal_lld.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM8L/pal_lld.c - * @brief STM8L GPIO low level driver code. - * - * @addtogroup PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @notapi - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - - switch (mode) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT_PULLUP: - port->DDR &= ~mask; - port->CR1 |= mask; - port->CR2 &= ~mask; - break; - case PAL_MODE_INPUT: - case PAL_MODE_INPUT_ANALOG: - port->DDR &= ~mask; - port->CR1 &= ~mask; - port->CR2 &= ~mask; - break; - case PAL_MODE_UNCONNECTED: - case PAL_MODE_OUTPUT_PUSHPULL_SLOW: - port->DDR |= mask; - port->CR1 |= mask; - port->CR2 &= ~mask; - break; - case PAL_MODE_OUTPUT_PUSHPULL: - port->DDR |= mask; - port->CR1 |= mask; - port->CR2 |= mask; - break; - case PAL_MODE_OUTPUT_OPENDRAIN_SLOW: - port->DDR |= mask; - port->CR1 &= ~mask; - port->CR2 &= ~mask; - break; - case PAL_MODE_OUTPUT_OPENDRAIN: - port->DDR |= mask; - port->CR1 &= ~mask; - port->CR2 |= mask; - break; - } -} - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/os/hal/platforms/STM8L/pal_lld.h b/os/hal/platforms/STM8L/pal_lld.h deleted file mode 100644 index b7dffed26..000000000 --- a/os/hal/platforms/STM8L/pal_lld.h +++ /dev/null @@ -1,244 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM8L/pal_lld.h - * @brief STM8L GPIO low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLDOWN - -/** - * @brief STM8L specific alternate push-pull slow output mode. - */ -#define PAL_MODE_OUTPUT_PUSHPULL_SLOW 16 - -/** - * @brief STM8L specific alternate open-drain slow output mode. - */ -#define PAL_MODE_OUTPUT_OPENDRAIN_SLOW 17 - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief Generic I/O ports static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct { -#if STM8L_HAS_GPIOI || defined(__DOXYGEN__) - GPIO_TypeDef P[9]; -#elif STM8L_HAS_GPIOH || defined(__DOXYGEN__) - GPIO_TypeDef P[8]; -#elif STM8L_HAS_GPIOG || defined(__DOXYGEN__) - GPIO_TypeDef P[7]; -#else - GPIO_TypeDef P[6]; -#endif -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 8 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint8_t ioportmask_t; - -/** - * @brief Digital I/O modes. - */ -typedef uint8_t iomode_t; - -/** - * @brief Port Identifier. - */ -typedef GPIO_TypeDef *ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief GPIO ports as a whole. - */ -#define IOPORTS ((PALConfig *)0x5000) - -#if STM8L_HAS_GPIOA || defined(__DOXYGEN__) -/** - * @brief GPIO port A identifier. - */ -#define IOPORT1 GPIOA -#endif - -#if STM8L_HAS_GPIOB || defined(__DOXYGEN__) -/** - * @brief GPIO port B identifier. - */ -#define IOPORT2 GPIOB -#endif - -#if STM8L_HAS_GPIOC || defined(__DOXYGEN__) -/** - * @brief GPIO port C identifier. - */ -#define IOPORT3 GPIOC -#endif - -#if STM8L_HAS_GPIOD || defined(__DOXYGEN__) -/** - * @brief GPIO port D identifier. - */ -#define IOPORT4 GPIOD -#endif - -#if STM8L_HAS_GPIOE || defined(__DOXYGEN__) -/** - * @brief GPIO port E identifier. - */ -#define IOPORT5 GPIOE -#endif - -#if STM8L_HAS_GPIOF || defined(__DOXYGEN__) -/** - * @brief GPIO port F identifier. - */ -#define IOPORT6 GPIOF -#endif - -#if STM8L_HAS_GPIOG || defined(__DOXYGEN__) -/** - * @brief GPIO port G identifier. - */ -#define IOPORT7 GPIOG -#endif - -#if STM8L_HAS_GPIOH || defined(__DOXYGEN__) -/** - * @brief GPIO port H identifier. - */ -#define IOPORT8 GPIOH -#endif - -#if STM8L_HAS_GPIOI || defined(__DOXYGEN__) -/** - * @brief GPIO port I identifier. - */ -#define IOPORT9 GPIOI -#endif - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - * - * @notapi - */ -#define pal_lld_init(config) (*IOPORTS = *(config)) - -/** - * @brief Reads the physical I/O port states. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->IDR) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->ODR) - -/** - * @brief Writes a bits mask on a I/O port. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->ODR = (bits)) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -extern ROMCONST PALConfig pal_default_config; - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM8L/platform.dox b/os/hal/platforms/STM8L/platform.dox deleted file mode 100644 index 9c28a931b..000000000 --- a/os/hal/platforms/STM8L/platform.dox +++ /dev/null @@ -1,99 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @defgroup STM8L_DRIVERS STM8L Drivers - * @details This section describes all the supported drivers on the STM8L - * and the implementation details of the single drivers. - * - * @ingroup platforms - */ - -/** - * @defgroup STM8L_HAL STM8L Initialization Support - * @details The STM8L HAL support is responsible for system initialization. - * - * @section stm8l_hal_1 Supported HW resources - * - CLK. - * . - * @section stm8l_hal_2 STM8L HAL driver implementation features - * - Board related initializations. - * - Clock tree initialization. - * - Clock source selection. - * . - * @ingroup STM8L_DRIVERS - */ - -/** - * @defgroup STM8L_PAL STM8L PAL Support - * @details The STM8L PAL driver uses the GPIO peripherals. - * - * @section stm8l_pal_1 Supported HW resources - * - GPIOA. - * - GPIOB. - * - GPIOC. - * - GPIOD. - * - GPIOE. - * - GPIOF. - * - GPIOG. - * - GPIOH (where present). - * - GPIOI (where present). - * . - * @section stm8l_pal_2 STM8L PAL driver implementation features - * The PAL driver implementation fully supports the following hardware - * capabilities: - * - 8 bits wide ports. - * - Atomic set/reset/toggle functions because special STM8L instruction set. - * - Output latched regardless of the pad setting. - * - Direct read of input pads regardless of the pad setting. - * . - * @section stm8l_pal_3 Supported PAL setup modes - * The STM8L PAL driver supports the following I/O modes: - * - @p PAL_MODE_RESET. - * - @p PAL_MODE_UNCONNECTED. - * - @p PAL_MODE_INPUT. - * - @p PAL_MODE_INPUT_PULLUP. - * - @p PAL_MODE_OUTPUT_PUSHPULL. - * - @p PAL_MODE_OUTPUT_OPENDRAIN. - * . - * Any attempt to setup an invalid mode is ignored. - * - * @section stm8l_pal_4 Suboptimal behavior - * The STM8L GPIO is less than optimal in several areas, the limitations - * should be taken in account while using the PAL driver: - * - Bus/group writing is not atomic. - * - Pad/group mode setup is not atomic. - * . - * @ingroup STM8L_DRIVERS - */ - -/** - * @defgroup STM8L_SERIAL STM8L Serial Support - * @details The STM8L Serial driver uses the USART1 peripheral in a - * buffered, interrupt driven, implementation. - * - * @section stm8l_serial_1 Supported HW resources - * The serial driver can support any of the following hardware resources: - * - USART1. - * - USART2 (where present). - * - USART3 (where present). - * . - * @section stm8l_serial_2 STM8L Serial driver implementation features - * - Clock stop for reduced power usage when the driver is in stop state. - * - Fully interrupt driven. - * . - * @ingroup STM8L_DRIVERS - */ diff --git a/os/hal/platforms/STM8L/serial_lld.c b/os/hal/platforms/STM8L/serial_lld.c deleted file mode 100644 index 2ef60bce8..000000000 --- a/os/hal/platforms/STM8L/serial_lld.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM8L/serial_lld.c - * @brief STM8L low level serial driver code. - * - * @addtogroup SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief USART1 serial driver identifier. - */ -#if STM8L_SERIAL_USE_USART1 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/** - * @brief USART2 serial driver identifier. - */ -#if STM8L_SERIAL_USE_USART2 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/** - * @brief USART3 serial driver identifier. - */ -#if STM8L_SERIAL_USE_USART3 || defined(__DOXYGEN__) -SerialDriver SD3; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** - * @brief Driver default configuration. - */ -static ROMCONST SerialConfig default_config = { - BRR(SERIAL_DEFAULT_BITRATE), - SD_MODE_PARITY_NONE | SD_MODE_STOP_1 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -#if STM8L_SERIAL_USE_USART1 || defined(__DOXYGEN__) -static void notify1(GenericQueue *qp) { - - (void)qp; - USART1->CR2 |= USART_CR2_TIEN; -} -#endif /* STM8L_SERIAL_USE_USART1 */ - -#if STM8L_SERIAL_USE_USART2 || defined(__DOXYGEN__) -static void notify2(GenericQueue *qp) { - - (void)qp; - USART2->CR2 |= USART_CR2_TIEN; -} -#endif /* STM8L_SERIAL_USE_USART1 */ - -#if STM8L_SERIAL_USE_USART3 || defined(__DOXYGEN__) -static void notify3(GenericQueue *qp) { - - (void)qp; - USART3->CR2 |= USART_CR2_TIEN; -} -#endif /* STM8L_SERIAL_USE_USART3 */ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/* See in serial_lld.h.*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Error handling routine. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] sr USART SR register value - * - * @notapi - */ -void sd_lld_set_error(SerialDriver *sdp, uint8_t sr) { - flagsmask_t sts = 0; - - if (sr & USART_SR_OR) - sts |= SD_OVERRUN_ERROR; - if (sr & USART_SR_NF) - sts |= SD_NOISE_ERROR; - if (sr & USART_SR_FE) - sts |= SD_FRAMING_ERROR; - if (sr & USART_SR_PE) - sts |= SD_PARITY_ERROR; - chSysLockFromIsr(); - chnAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -/** - * @brief Low level serial driver initialization. - * - * @notapi - */ -void sd_lld_init(void) { - -#if STM8L_SERIAL_USE_USART1 - sdObjectInit(&SD1, NULL, notify1); - CLK->PCKENR1 |= CLK_PCKENR1_USART1; /* PCKEN12, clock source. */ - USART1->CR1 = USART_CR1_USARTD; /* USARTD (low power). */ - SD1.usart = USART1; -#endif - -#if STM8L_SERIAL_USE_USART2 - sdObjectInit(&SD2, NULL, notify2); - CLK->PCKENR3 |= CLK_PCKENR3_USART2; /* PCKEN13, clock source. */ - USART2->CR1 = USART_CR1_USARTD; /* USARTD (low power). */ - SD2.usart = USART2; -#endif - -#if STM8L_SERIAL_USE_USART3 - sdObjectInit(&SD3, NULL, notify3); - CLK->PCKENR3 |= CLK_PCKENR3_USART3; /* PCKEN13, clock source. */ - USART3->CR1 = USART_CR1_USARTD; /* USARTD (low power). */ - SD3.usart = USART3; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - * - * @notapi - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - USART_TypeDef *u = sdp->usart; - - if (config == NULL) - config = &default_config; - - u->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) | - ((uint8_t)config->sc_brr & (uint8_t)0x0F)); - u->BRR1 = (uint8_t)(config->sc_brr >> 4); - u->CR1 = (uint8_t)(config->sc_mode & SD_MODE_PARITY); - u->CR2 = USART_CR2_RIEN | USART_CR2_TEN | USART_CR2_REN; - u->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP); - u->CR4 = 0; - u->CR5 = 0; - u->PSCR = 1; - (void)u->SR; - (void)u->DR; -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the USART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - * - * @notapi - */ -void sd_lld_stop(SerialDriver *sdp) { - USART_TypeDef *u = sdp->usart; - - u->CR1 = USART_CR1_USARTD; - u->CR2 = 0; - u->CR3 = 0; - u->CR4 = 0; - u->CR5 = 0; - u->PSCR = 0; -} - -#endif /* HAL_USE_SERIAL */ - -/** @} */ diff --git a/os/hal/platforms/STM8L/serial_lld.h b/os/hal/platforms/STM8L/serial_lld.h deleted file mode 100644 index 1164cc8fc..000000000 --- a/os/hal/platforms/STM8L/serial_lld.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM8L/serial_lld.h - * @brief STM8L low level serial driver header. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define SD_MODE_PARITY 0x07 /**< @brief Parity field mask. */ -#define SD_MODE_PARITY_NONE 0x00 /**< @brief No parity. */ -#define SD_MODE_PARITY_EVEN 0x05 /**< @brief Even parity. */ -#define SD_MODE_PARITY_ODD 0x07 /**< @brief Odd parity. */ - -#define SD_MODE_STOP 0x30 /**< @brief Stop bits mask. */ -#define SD_MODE_STOP_1 0x00 /**< @brief One stop bit. */ -#define SD_MODE_STOP_2 0x20 /**< @brief Two stop bits. */ -#define SD_MODE_STOP_1P5 0x30 /**< @brief 1.5 stop bits. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief USART1 driver enable switch. - * @details If set to @p TRUE the support for USART1 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM8L_SERIAL_USE_USART1) || defined(__DOXYGEN__) -#define STM8L_SERIAL_USE_USART1 TRUE -#endif - -/** - * @brief USART2 driver enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM8L_SERIAL_USE_USART2) || defined(__DOXYGEN__) -#define STM8L_SERIAL_USE_USART2 TRUE -#endif - -/** - * @brief USART3 driver enable switch. - * @details If set to @p TRUE the support for USART3 is included. - * @note The default is @p TRUE. - */ -#if !defined(STM8L_SERIAL_USE_USART3) || defined(__DOXYGEN__) -#define STM8L_SERIAL_USE_USART3 TRUE -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if STM8L_SERIAL_USE_USART1 && !STM8L_HAS_USART1 -#error "USART1 not present in the selected device" -#endif - -#if STM8L_SERIAL_USE_USART2 && !STM8L_HAS_USART2 -#error "USART2 not present in the selected device" -#endif - -#if STM8L_SERIAL_USE_USART3 && !STM8L_HAS_USART3 -#error "USART3 not present in the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Generic Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - * @note This structure content is architecture dependent, each driver - * implementation defines its own version and the custom static - * initializers. - */ -typedef struct { - /** - * @brief Bit rate register. - */ - uint16_t sc_brr; - /** - * @brief Mode flags. - */ - uint8_t sc_mode; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - USART_TypeDef *usart; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Macro for baud rate computation. - * @note Make sure the final baud rate is within tolerance. - */ -#define BRR(b) (SYSCLK / (b)) - -#if STM8L_SERIAL_USE_USART1 || defined(__DOXYGEN__) -/** - * @brief USART1 RX interrupt handler segment. - */ -#define _USART1_RECEIVE_ISR() { \ - uint8_t sr = USART1->SR; \ - if (sr & (USART_SR_RXNE | USART_SR_OR | USART_SR_NF | \ - USART_SR_FE | USART_SR_PE)) { \ - if (sr & (USART_SR_OR | USART_SR_NF | USART_SR_FE | USART_SR_PE)) \ - sd_lld_set_error(&SD1, sr); \ - chSysLockFromIsr(); \ - sdIncomingDataI(&SD1, USART1->DR); \ - chSysUnlockFromIsr(); \ - } \ -} - -/** - * @brief USART1 TX interrupt handler segment. - */ -#define _USART1_TRANSMIT_ISR() { \ - if (USART1->SR & USART_SR_TXE) { \ - msg_t b; \ - chSysLockFromIsr(); \ - b = sdRequestDataI(&SD1); \ - chSysUnlockFromIsr(); \ - if (b < Q_OK) \ - USART1->CR2 &= (uint8_t)~USART_CR2_TIEN; \ - else \ - USART1->DR = (uint8_t)b; \ - } \ -} -#endif /* STM8L_SERIAL_USE_USART1 */ - -#if STM8L_SERIAL_USE_USART2 || defined(__DOXYGEN__) -/** - * @brief USART2 RX interrupt handler segment. - */ -#define _USART2_RECEIVE_ISR() { \ - uint8_t sr = USART2->SR; \ - if (sr & (USART_SR_RXNE | USART_SR_OR | USART_SR_NF | \ - USART_SR_FE | USART_SR_PE)) { \ - if (sr & (USART_SR_OR | USART_SR_NF | USART_SR_FE | USART_SR_PE)) \ - sd_lld_set_error(&SD2, sr); \ - chSysLockFromIsr(); \ - sdIncomingDataI(&SD2, USART2->DR); \ - chSysUnlockFromIsr(); \ - } \ -} - -/** - * @brief USART2 TX interrupt handler segment. - */ -#define _USART2_TRANSMIT_ISR() { \ - if (USART2->SR & USART_SR_TXE) { \ - msg_t b; \ - chSysLockFromIsr(); \ - b = sdRequestDataI(&SD2); \ - chSysUnlockFromIsr(); \ - if (b < Q_OK) \ - USART2->CR2 &= (uint8_t)~USART_CR2_TIEN; \ - else \ - USART2->DR = (uint8_t)b; \ - } \ -} -#endif /* STM8L_SERIAL_USE_USART2 */ - -#if STM8L_SERIAL_USE_USART3 || defined(__DOXYGEN__) -/** - * @brief USART3 RX interrupt handler segment. - */ -#define _USART3_RECEIVE_ISR() { \ - uint8_t sr = USART3->SR; \ - if (sr & (USART_SR_RXNE | USART_SR_OR | USART_SR_NF | \ - USART_SR_FE | USART_SR_PE)) { \ - if (sr & (USART_SR_OR | USART_SR_NF | USART_SR_FE | USART_SR_PE)) \ - sd_lld_set_error(&SD3, sr); \ - chSysLockFromIsr(); \ - sdIncomingDataI(&SD3, USART3->DR); \ - chSysUnlockFromIsr(); \ - } \ -} - -/** - * @brief USART3 TX interrupt handler segment. - */ -#define _USART3_TRANSMIT_ISR() { \ - if (USART3->SR & USART_SR_TXE) { \ - msg_t b; \ - chSysLockFromIsr(); \ - b = sdRequestDataI(&SD3); \ - chSysUnlockFromIsr(); \ - if (b < Q_OK) \ - USART3->CR2 &= (uint8_t)~USART_CR2_TIEN; \ - else \ - USART3->DR = (uint8_t)b; \ - } \ -} -#endif /* STM8L_SERIAL_USE_USART3 */ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM8L_SERIAL_USE_USART1 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif -#if STM8L_SERIAL_USE_USART2 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif -#if STM8L_SERIAL_USE_USART3 && !defined(__DOXYGEN__) -extern SerialDriver SD3; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); - void sd_lld_set_error(SerialDriver *sdp, uint8_t sr); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/STM8L/shared_isr.c b/os/hal/platforms/STM8L/shared_isr.c deleted file mode 100644 index ed94a112b..000000000 --- a/os/hal/platforms/STM8L/shared_isr.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file STM8L/shared_isr.c - * @brief STM8L shared interrupt code source. - * @details The STM8L shares some interrupt handlers among several sources. - * This module includes all the interrupt handlers that are - * used by more than one peripheral. - * @note Only the interrupt handlers that are used by the HAL are defined - * in this module. - * - * @addtogroup HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/* This inclusion allows user ISR to be added to the HAL.*/ -#if defined(_USER_ISR_) -#include "user_isr.h" -#endif - -#if defined(_TIM2_UPDATE_ISR) || defined(_USART2_TRANSMIT_ISR) || \ - defined(__DOXYGEN__) -/** - * @brief IRQ 19 service routine. - * @details This handler is shared between the following sources: - * - TIM2 update/overflow/trigger/break. - * - USART2 transmit. - * . - * - * @isr - */ -CH_IRQ_HANDLER(19) { - CH_IRQ_PROLOGUE(); - -#if defined(_TIM2_UPDATE_ISR) - _TIM2_UPDATE_ISR(); -#endif -#if defined(_USART2_TRANSMIT_ISR) - _USART2_TRANSMIT_ISR(); -#endif - - CH_IRQ_EPILOGUE(); -} -#endif /* defined(_TIM2_UPDATE_ISR) || defined(_USART2_TRANSMIT_ISR) */ - -#if defined(_TIM2_COMPARE_ISR) || defined(_USART2_RECEIVE_ISR) || \ - defined(__DOXYGEN__) -/** - * @brief IRQ 20 service routine. - * @details This handler is shared between the following sources: - * - TIM2 compare/capture - * - USART2 receive. - * . - * - * @isr - */ -CH_IRQ_HANDLER(20) { - CH_IRQ_PROLOGUE(); - -#if defined(_TIM2_COMPARE_ISR) - _TIM2_COMPARE_ISR(); -#endif -#if defined(_USART2_RECEIVE_ISR) - _USART2_RECEIVE_ISR(); -#endif - - CH_IRQ_EPILOGUE(); -} -#endif /* defined(_TIM2_COMPARE_ISR) || defined(_USART2_RECEIVE_ISR) */ - -#if defined(_TIM3_UPDATE_ISR) || defined(_USART3_TRANSMIT_ISR) || \ - defined(__DOXYGEN__) -/** - * @brief IRQ 21 service routine. - * @details This handler is shared between the following sources: - * - TIM3 update/overflow/trigger/break. - * - USART3 transmit. - * . - * - * @isr - */ -CH_IRQ_HANDLER(21) { - CH_IRQ_PROLOGUE(); - -#if defined(_TIM3_UPDATE_ISR) - _TIM3_UPDATE_ISR(); -#endif -#if defined(_USART3_TRANSMIT_ISR) - _USART3_TRANSMIT_ISR(); -#endif - - CH_IRQ_EPILOGUE(); -} -#endif /* defined(_TIM3_UPDATE_ISR) || defined(_USART3_TRANSMIT_ISR) */ - -#if defined(_TIM3_COMPARE_ISR) || defined(_USART3_RECEIVE_ISR) || \ - defined(__DOXYGEN__) -/** - * @brief IRQ 22 service routine. - * @details This handler is shared between the following sources: - * - TIM3 compare/capture - * - USART3 receive. - * . - * - * @isr - */ -CH_IRQ_HANDLER(22) { - CH_IRQ_PROLOGUE(); - -#if defined(_TIM3_COMPARE_ISR) - _TIM3_COMPARE_ISR(); -#endif -#if defined(_USART3_RECEIVE_ISR) - _USART3_RECEIVE_ISR(); -#endif - - CH_IRQ_EPILOGUE(); -} -#endif /* defined(_TIM3_COMPARE_ISR) || defined(_USART3_RECEIVE_ISR) */ - -#if defined(_TIM5_UPDATE_ISR) || defined(_USART1_TRANSMIT_ISR) || \ - defined(__DOXYGEN__) -/** - * @brief IRQ 27 service routine. - * @details This handler is shared between the following sources: - * - TIM5 update/overflow/trigger/break. - * - USART1 transmit. - * . - * - * @isr - */ -CH_IRQ_HANDLER(27) { - CH_IRQ_PROLOGUE(); - -#if defined(_TIM5_UPDATE_ISR) - _TIM5_UPDATE_ISR(); -#endif -#if defined(_USART1_TRANSMIT_ISR) - _USART1_TRANSMIT_ISR(); -#endif - - CH_IRQ_EPILOGUE(); -} -#endif /* defined(_TIM5_UPDATE_ISR) || defined(_USART1_TRANSMIT_ISR) */ - -#if defined(_TIM5_COMPARE_ISR) || defined(_USART1_RECEIVE_ISR) || \ - defined(__DOXYGEN__) -/** - * @brief IRQ 28 service routine. - * @details This handler is shared between the following sources: - * - TIM5 compare/capture - * - USART1 receive. - * . - * - * @isr - */ -CH_IRQ_HANDLER(28) { - CH_IRQ_PROLOGUE(); - -#if defined(_TIM5_COMPARE_ISR) - _TIM5_COMPARE_ISR(); -#endif -#if defined(_USART1_RECEIVE_ISR) - _USART1_RECEIVE_ISR(); -#endif - - CH_IRQ_EPILOGUE(); -} -#endif /* defined(_TIM5_COMPARE_ISR) || defined(_USART1_RECEIVE_ISR) */ - -/** @} */ diff --git a/os/hal/platforms/STM8L/stm8l15x.h b/os/hal/platforms/STM8L/stm8l15x.h deleted file mode 100644 index 6971a9da5..000000000 --- a/os/hal/platforms/STM8L/stm8l15x.h +++ /dev/null @@ -1,3000 +0,0 @@ -/** - ****************************************************************************** - * @file stm8l15x.h - * @author MCD Application Team - * @version V1.5.0 - * @date 13-May-2011 - * @brief This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM8L15x devices. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM8L15x_H - #define __STM8L15x_H - -/** @addtogroup STM8L15x_StdPeriph_Driver - * @{ - */ -/* Uncomment the line below according to the target STM8L15x device used in your - application - */ -/* #define STM8L15X_LD */ /*!< STM8L15X_LD: STM8L15x Low density devices */ -/* #define STM8L15X_MD */ /*!< STM8L15X_MD: STM8L15x Medium density devices */ -/* #define STM8L15X_MDP */ /*!< STM8L15X_MDP: STM8L15x Medium density plus devices */ -/* #define STM8L15X_HD */ /*!< STM8L15X_HD: STM8L15x/16x High density devices */ - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - - - Low density STM8L15x devices are STM8L151C3, STM8L151K3, STM8L151G3, STM8L151F3, - STM8L151C2, STM8L151K2, STM8L151G2 and STM8L151F2 microcontrollers where the - Flash memory density ranges between 4 and 8 Kbytes. - - Medium density STM8L15x devices are STM8L151C4, STM8L151C6, STM8L152C4, - STM8L152C6, STM8L151K4, STM8L151K6, STM8L152K4, STM8L152K6, STM8L151G4, - STM8L151G6, STM8L152G4 and STM8L152G6 microcontrollers where the Flash memory - density ranges between 16 and 32 Kbytes. - - Medium density Plus devices are STM8L151R6, STM8L152R6 microcontrollers where - the Flash memory density is fixed and equal to 32 Kbytes and a wider range of - peripheral than the medium density devices. - - High density STM8L15x devices are STM8L151x8, STM8L152x8, STM8L162R8 and STM8L162M8 - microcontrollers where the Flash memory density is fixed and equal to 64 Kbytes with - the same peripheral set than Medium Density Plus devices. - - */ - -#if !defined (STM8L15X_MD) && !defined (STM8L15X_MDP) && !defined (STM8L15X_HD) && !defined (STM8L15X_LD) - #error "Please select first the target STM8L device used in your application (in stm8l15x.h file)" -#endif - -/******************************************************************************/ -/* Library configuration section */ -/******************************************************************************/ -/* Check the used compiler */ -#if defined(__CSMC__) - #define _COSMIC_ -#elif defined(__RCST7__) - #define _RAISONANCE_ -#elif defined(__ICCSTM8__) - #define _IAR_ -#else - #error "Unsupported Compiler!" /* Compiler defines not found */ -#endif - -#if !defined USE_STDPERIPH_DRIVER -/* Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will be - based on direct access to peripherals registers */ -/* CHIBIOS FIX */ -/* #define USE_STDPERIPH_DRIVER*/ -#endif - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined HSE_Value - #define HSE_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSE in Hz */ -#endif /* HSE_Value */ - -/** - * @brief Definition of External Low Speed oscillator (LSE) frequency - */ -#define LSE_VALUE ((uint32_t)32768) /*!< Typical Value of the LSE in Hz */ - -/** - * @brief Definition of Device on-chip RC oscillator frequencies - */ -#define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */ -#define LSI_VALUE ((uint32_t)38000) /*!< Typical Value of the LSI in Hz */ - -#ifdef _COSMIC_ - #define FAR @far - #define NEAR @near - #define TINY @tiny - #define EEPROM @eeprom - #define CONST const -#elif defined (_RAISONANCE_) /* __RCST7__ */ - #define FAR far - #define NEAR data - #define TINY page0 - #define EEPROM eeprom - #define CONST code - #if defined (STM8L15X_MD) || defined (STM8L15X_MDP) - /*!< Used with memory Models for code less than 64K */ - #define MEMCPY memcpy - #else /* STM8L15X_HD */ - /*!< Used with memory Models for code higher than 64K */ - #define MEMCPY fmemcpy - #endif /* STM8L15X_MD or STM8L15X_MDP */ -#else /*_IAR_*/ - #define FAR __far - #define NEAR __near - #define TINY __tiny - #define EEPROM __eeprom - #define CONST const -#endif /* __CSMC__ */ - -/** - * @brief Legacy definition - */ -#define __CONST CONST - -#if defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8L15X_LD) -/*!< Used with memory Models for code smaller than 64K */ - #define PointerAttr NEAR -#else /* STM8L15X_HD */ -/*!< Used with memory Models for code higher than 64K */ - #define PointerAttr FAR -#endif /* STM8L15X_MD or STM8L15X_MDP or STM8L15X_LD*/ - -/* Uncomment the line below to enable the FLASH functions execution from RAM */ -#if !defined (RAM_EXECUTION) -/* #define RAM_EXECUTION (1) */ -#endif /* RAM_EXECUTION */ - -#ifdef RAM_EXECUTION - #ifdef _COSMIC_ - #define IN_RAM(a) a - #elif defined (_RAISONANCE_) /* __RCST7__ */ - #define IN_RAM(a) a inram - #else /*_IAR_*/ - #define IN_RAM(a) __ramfunc a - #endif /* _COSMIC_ */ -#else - #define IN_RAM(a) a -#endif /* RAM_EXECUTION */ - -/*!< [31:16] STM8L15X Standard Peripheral Library main version */ -#define __STM8L15X_STDPERIPH_VERSION_MAIN ((uint8_t)0x01) /*!< [31:24] main version */ -#define __STM8L15X_STDPERIPH_VERSION_SUB1 ((uint8_t)0x05) /*!< [23:16] sub1 version */ -#define __STM8L15X_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) /*!< [15:8] sub2 version */ -#define __STM8L15X_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release candidate */ -#define __STM8L15X_STDPERIPH_VERSION ( (__STM8L15X_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM8L15X_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM8L15X_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM8L15X_STDPERIPH_VERSION_RC)) - -/******************************************************************************/ - -/* Includes ------------------------------------------------------------------*/ - -/* Exported types and constants ----------------------------------------------*/ - -/** @addtogroup Exported_types - * @{ - */ - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ -#define __I volatile const /*!< defines 'read only' permissions */ -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/* CHIBIOS FIX */ -#if 0 -/*!< Signed integer types */ -typedef signed char int8_t; -typedef signed short int16_t; -typedef signed long int32_t; - -/*!< Unsigned integer types */ -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned long uint32_t; -#endif - -/*!< STM8Lx Standard Peripheral Library old types (maintained for legacy purpose) */ - -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - - -typedef enum {FALSE = 0, TRUE = !FALSE} bool; - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -#define U8_MAX (255) -#define S8_MAX (127) -#define S8_MIN (-128) -#define U16_MAX (65535u) -#define S16_MAX (32767) -#define S16_MIN (-32768) -#define U32_MAX (4294967295uL) -#define S32_MAX (2147483647) -#define S32_MIN (-2147483648uL) - -/** - * @} - */ - -/** @addtogroup MAP_FILE_Exported_Types_and_Constants - * @{ - */ - -/******************************************************************************/ -/* IP registers structures */ -/******************************************************************************/ - -/*----------------------------------------------------------------------------*/ -/** - * @brief General Purpose I/Os (GPIO) - */ -typedef struct GPIO_struct -{ - __IO uint8_t ODR; /*!< Output Data Register */ - __IO uint8_t IDR; /*!< Input Data Register */ - __IO uint8_t DDR; /*!< Data Direction Register */ - __IO uint8_t CR1; /*!< Configuration Register 1 */ - __IO uint8_t CR2; /*!< Configuration Register 2 */ -} -GPIO_TypeDef; - -/** @addtogroup GPIO_Registers_Reset_Value - * @{ - */ -#define GPIO_ODR_RESET_VALUE ((uint8_t)0x00) -#define GPIO_DDR_RESET_VALUE ((uint8_t)0x00) -#define GPIO_CR1_RESET_VALUE ((uint8_t)0x00) -#define GPIO_CR2_RESET_VALUE ((uint8_t)0x00) -/** - * @} - */ -/*----------------------------------------------------------------------------*/ - -/** - * @brief Real-Time Clock (RTC) peripheral registers. - */ -typedef struct RTC_struct -{ - __IO uint8_t TR1; /*!< Time Register 1*/ - __IO uint8_t TR2; /*!< Time Register 2*/ - __IO uint8_t TR3; /*!< Time Register 3*/ - - uint8_t RESERVED0; - - __IO uint8_t DR1; /*!< Date Register 1*/ - __IO uint8_t DR2; /*!< Date Register 2*/ - __IO uint8_t DR3; /*!< Date Register 3*/ - - uint8_t RESERVED1; - - __IO uint8_t CR1; /*!< Control Register 1*/ - __IO uint8_t CR2; /*!< Control Register 2*/ - __IO uint8_t CR3; /*!< Control Register 3*/ - - uint8_t RESERVED2; - - __IO uint8_t ISR1; /*!< Initialisation and Status Register 1 */ - __IO uint8_t ISR2; /*!< Initialisation and Status Register 2 */ - - uint8_t RESERVED3; - uint8_t RESERVED4; - - __IO uint8_t SPRERH; /*!< Synchronous Prediv high Register */ - __IO uint8_t SPRERL; /*!< Synchronous Prediv Low Register */ - __IO uint8_t APRER; /*!< Asynchronous Prediv Register */ - - uint8_t RESERVED5; - - __IO uint8_t WUTRH; /*!< Wake-Up Timer High Register */ - __IO uint8_t WUTRL; /*!< Wake-Up Timer Low Register */ - - uint8_t RESERVED6; - - __IO uint8_t SSRH; /*!< Sub Second High Register */ - __IO uint8_t SSRL; /*!< Sub Second Low Register */ - - __IO uint8_t WPR; /*!< Write Protection Register */ - - __IO uint8_t SHIFTRH; /*!< Shift control High Register */ - __IO uint8_t SHIFTRL; /*!< Shift control Low Register */ - - __IO uint8_t ALRMAR1; /*!< ALARM A Register 1 */ - __IO uint8_t ALRMAR2; /*!< ALARM A Register 2 */ - __IO uint8_t ALRMAR3; /*!< ALARM A Register 3 */ - __IO uint8_t ALRMAR4; /*!< ALARM A Register 4 */ - - uint8_t RESERVED7[4]; - - __IO uint8_t ALRMASSRH; /*!< ALARM A Subsecond Register High */ - __IO uint8_t ALRMASSRL; /*!< ALARM A Subsecond Register Low */ - __IO uint8_t ALRMASSMSKR; /*!< ALARM A Subsecond Mask Register */ - - uint8_t RESERVED8[3]; - - __IO uint8_t CALRH; /*!< Calibration register high */ - __IO uint8_t CALRL; /*!< Calibration register low */ - - __IO uint8_t TCR1; /*!< Tamper control register 1 */ - __IO uint8_t TCR2; /*!< Tamper control register 2 */ -} -RTC_TypeDef; - -/** @addtogroup RTC_Registers_Reset_Value - * @{ - */ -#define RTC_TR1_RESET_VALUE ((uint8_t)0x00) -#define RTC_TR2_RESET_VALUE ((uint8_t)0x00) -#define RTC_TR3_RESET_VALUE ((uint8_t)0x00) - -#define RTC_DR1_RESET_VALUE ((uint8_t)0x01) -#define RTC_DR2_RESET_VALUE ((uint8_t)0x21) -#define RTC_DR3_RESET_VALUE ((uint8_t)0x00) - -#define RTC_CR1_RESET_VALUE ((uint8_t)0x00) -#define RTC_CR2_RESET_VALUE ((uint8_t)0x00) -#define RTC_CR3_RESET_VALUE ((uint8_t)0x00) - -#define RTC_ISR1_RESET_VALUE ((uint8_t)0x07) -#define RTC_ISR2_RESET_VALUE ((uint8_t)0x00) - -#define RTC_SPRERH_RESET_VALUE ((uint8_t)0x00) -#define RTC_SPRERL_RESET_VALUE ((uint8_t)0xFF) -#define RTC_APRER_RESET_VALUE ((uint8_t)0x7F) - -#define RTC_WUTRH_RESET_VALUE ((uint8_t)0xFF) -#define RTC_WUTRL_RESET_VALUE ((uint8_t)0xFF) - -#define RTC_WPR_RESET_VALUE ((uint8_t)0x00) - -#define RTC_ALRMAR1_RESET_VALUE ((uint8_t)0x00) -#define RTC_ALRMAR2_RESET_VALUE ((uint8_t)0x00) -#define RTC_ALRMAR3_RESET_VALUE ((uint8_t)0x00) -#define RTC_ALRMAR4_RESET_VALUE ((uint8_t)0x00) - -#define RTC_SHIFTRH_RESET_VALUE ((uint8_t)0x00) -#define RTC_SHIFTRL_RESET_VALUE ((uint8_t)0x00) - -#define RTC_ALRMASSRH_RESET_VALUE ((uint8_t)0x00) -#define RTC_ALRMASSRL_RESET_VALUE ((uint8_t)0x00) -#define RTC_ALRMASSMSKR_RESET_VALUE ((uint8_t)0x00) - -#define RTC_CALRH_RESET_VALUE ((uint8_t)0x00) -#define RTC_CALRL_RESET_VALUE ((uint8_t)0x00) - -#define RTC_TCR1_RESET_VALUE ((uint8_t)0x00) -#define RTC_TCR2_RESET_VALUE ((uint8_t)0x00) - -/** - * @} - */ - -/** @addtogroup RTC_Registers_Bits_Definition - * @{ - */ - -/* Bits definition for RTC_TR1 register*/ -#define RTC_TR1_ST ((uint8_t)0x70) -#define RTC_TR1_SU ((uint8_t)0x0F) - -/* Bits definition for RTC_TR2 register*/ -#define RTC_TR2_MNT ((uint8_t)0x70) -#define RTC_TR2_MNU ((uint8_t)0x0F) - -/* Bits definition for RTC_TR3 register*/ -#define RTC_TR3_PM ((uint8_t)0x40) -#define RTC_TR3_HT ((uint8_t)0x30) -#define RTC_TR3_HU ((uint8_t)0x0F) - -/* Bits definition for RTC_DR1 register*/ -#define RTC_DR1_DT ((uint8_t)0x30) -#define RTC_DR1_DU ((uint8_t)0x0F) - -/* Bits definition for RTC_DR2 register*/ -#define RTC_DR2_WDU ((uint8_t)0xE0) -#define RTC_DR2_MT ((uint8_t)0x10) -#define RTC_DR2_MU ((uint8_t)0x0F) - -/* Bits definition for RTC_DR3 register*/ -#define RTC_DR3_YT ((uint8_t)0xF0) -#define RTC_DR3_YU ((uint8_t)0x0F) - -/* Bits definition for RTC_CR1 register*/ -#define RTC_CR1_FMT ((uint8_t)0x40) -#define RTC_CR1_RATIO ((uint8_t)0x20) -#define RTC_CR1_WUCKSEL ((uint8_t)0x07) -#define RTC_CR1_BYPSHAD ((uint8_t)0x10) - - -/* Bits definition for RTC_CR2 register*/ -#define RTC_CR2_WUTIE ((uint8_t)0x40) -#define RTC_CR2_ALRAIE ((uint8_t)0x10) -#define RTC_CR2_WUTE ((uint8_t)0x04) -#define RTC_CR2_ALRAE ((uint8_t)0x01) -#define RTC_CR2_ALRIE ((uint8_t)0x20) - - - -/* Bits definition for RTC_CR3 register*/ -#define RTC_CR3_COE ((uint8_t)0x80) -#define RTC_CR3_OSEL ((uint8_t)0x60) -#define RTC_CR3_POL ((uint8_t)0x10) -#define RTC_CR3_COSEL ((uint8_t)0x08) -#define RTC_CR3_BCK ((uint8_t)0x04) -#define RTC_CR3_SUB1H ((uint8_t)0x02) -#define RTC_CR3_ADD1H ((uint8_t)0x01) - - -/* Bits definition for RTC_ISR1 register*/ -#define RTC_ISR1_INIT ((uint8_t)0x80) -#define RTC_ISR1_INITF ((uint8_t)0x40) -#define RTC_ISR1_RSF ((uint8_t)0x20) -#define RTC_ISR1_INITS ((uint8_t)0x10) -#define RTC_ISR1_SHPF ((uint8_t)0x08) -#define RTC_ISR1_WUTWF ((uint8_t)0x04) -#define RTC_ISR1_RECALPF ((uint8_t)0x02) -#define RTC_ISR1_ALRAWF ((uint8_t)0x01) - - -/* Bits definition for RTC_ISR2 register*/ -#define RTC_ISR2_WUTF ((uint8_t)0x04) -#define RTC_ISR2_ALRAF ((uint8_t)0x01) -#define RTC_ISR2_TAMP3F ((uint8_t)0x80) -#define RTC_ISR2_TAMP2F ((uint8_t)0x40) -#define RTC_ISR2_TAMP1F ((uint8_t)0x20) - -/* Bits definition for RTC_SHIFTRH register*/ -#define RTC_SHIFTRH_ADD1S ((uint8_t)0x80) -#define RTC_SHIFTRH_SUBFS ((uint8_t)0x7F) - -/* Bits definition for RTC_SHIFTRL register*/ -#define RTC_SHIFTRL_SUBFS ((uint8_t)0xFF) - - -/* Bits definition for RTC_ALRMAR1 register*/ -#define RTC_ALRMAR1_MSK1 ((uint8_t)0x80) -#define RTC_ALRMAR1_ST ((uint8_t)0x70) -#define RTC_ALRMAR1_SU ((uint8_t)0x0F) - -/* Bits definition for RTC_ALRMAR2 register*/ -#define RTC_ALRMAR2_MSK2 ((uint8_t)0x80) -#define RTC_ALRMAR2_MNT ((uint8_t)0x70) -#define RTC_ALRMAR2_MNU ((uint8_t)0x0F) - -/* Bits definition for RTC_ALRMAR3 register*/ -#define RTC_ALRMAR3_MSK3 ((uint8_t)0x80) -#define RTC_ALRMAR3_PM ((uint8_t)0x40) -#define RTC_ALRMAR3_HT ((uint8_t)0x30) -#define RTC_ALRMAR3_HU ((uint8_t)0x0F) - -/* Bits definition for RTC_ALRMAR4 register*/ -#define RTC_ALRMAR4_MSK4 ((uint8_t)0x80) -#define RTC_ALRMAR4_WDSEL ((uint8_t)0x40) -#define RTC_ALRMAR4_DT ((uint8_t)0x30) -#define RTC_ALRMAR4_DU ((uint8_t)0x0F) - -/* Bits definition for RTC_ALRMASSRH register*/ -#define RTC_ALRMASSRH_ALSS ((uint8_t)0x7F) - -/* Bits definition for RTC_ALRMASSRL register*/ -#define RTC_ALRMASSRL_ALSS ((uint8_t)0xFF) - -/* Bits definition for RTC_ALRMASSMSKR register*/ -#define RTC_ALRMASSMSKR_MASKSS ((uint8_t)0x1F) - - -/* Bits definition for RTC_CALRH register*/ -#define RTC_CALRH_CALP ((uint8_t)0x80) -#define RTC_CALRH_CALW8 ((uint8_t)0x40) -#define RTC_CALRH_CALW16 ((uint8_t)0x20) -#define RTC_CALRH_CALWx ((uint8_t)0x60) -#define RTC_CALRH_CALM ((uint8_t)0x01) - -/* Bits definition for RTC_CALRL register*/ -#define RTC_CALRL_CALM ((uint8_t)0xFF) - -/* Bits definition for RTC_TCR1 register*/ -#define RTC_TCR1_TAMP3LEVEL ((uint8_t)0x40) -#define RTC_TCR1_TAMP3E ((uint8_t)0x20) -#define RTC_TCR1_TAMP2LEVEL ((uint8_t)0x10) -#define RTC_TCR1_TAMP2E ((uint8_t)0x08) -#define RTC_TCR1_TAMP1LEVEL ((uint8_t)0x04) -#define RTC_TCR1_TAMP1E ((uint8_t)0x02) -#define RTC_TCR1_TAMPIE ((uint8_t)0x01) - -/* Bits definition for RTC_TCR2 register*/ -#define RTC_TCR2_TAMPPUDIS ((uint8_t)0x80) -#define RTC_TCR2_TAMPPRCH ((uint8_t)0x60) -#define RTC_TCR2_TAMPFLT ((uint8_t)0x18) -#define RTC_TCR2_TAMPFREQ ((uint8_t)0x07) - - -/*RTC special defines */ -#define RTC_WPR_EnableKey ((uint8_t)0xFF) -#define RTC_WPR_DisableKey1 ((uint8_t)0xCA) -#define RTC_WPR_DisableKey2 ((uint8_t)0x53) - -/** - * @} - */ - -/** - * @brief CSS on LSE registers. - */ -typedef struct CSSLSE_struct -{ - __IO uint8_t CSR; /*!< Control and Status Register*/ -} -CSSLSE_TypeDef; - -/** @addtogroup CSSLSE_Registers_Reset_Value - * @{ - */ -#define CSSLSE_CSR_RESET_VALUE ((uint8_t)0x00) - -/** - * @} - */ - -/** @addtogroup CSSLSE_Registers_Bits_Definition - * @{ - */ - -/* Bits definition for CSSLSE_CSR register*/ -#define CSSLSE_CSR_SWITCHF ((uint8_t)0x10) -#define CSSLSE_CSR_CSSF ((uint8_t)0x08) -#define CSSLSE_CSR_CSSIE ((uint8_t)0x04) -#define CSSLSE_CSR_SWITCHEN ((uint8_t)0x02) -#define CSSLSE_CSR_CSSEN ((uint8_t)0x01) - -/** - * @} - */ -/*----------------------------------------------------------------------------*/ -/** - * @brief Beeper (BEEP) peripheral registers. - */ - -typedef struct BEEP_struct -{ - __IO uint8_t CSR1; /*!< BEEP Control status register1 */ - uint8_t RSERVED1; - uint8_t RESERVED2; - __IO uint8_t CSR2; /*!< BEEP Control status register2 */ -} -BEEP_TypeDef; - -/** @addtogroup BEEP_Registers_Reset_Value - * @{ - */ -#define BEEP_CSR1_RESET_VALUE ((uint8_t)0x00) -#define BEEP_CSR2_RESET_VALUE ((uint8_t)0x1F) - -/** - * @} - */ - -/** @addtogroup BEEP_Registers_Bits_Definition - * @{ - */ - -#define BEEP_CSR1_MSR ((uint8_t)0x01) /*!< Measurement enable mask */ - -#define BEEP_CSR2_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */ -#define BEEP_CSR2_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */ -#define BEEP_CSR2_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */ - -/** - * @} - */ - -/*----------------------------------------------------------------------------ok*/ - -/** - * @brief Configuration Registers (CFG) - */ - -typedef struct CFG_struct -{ - __IO uint8_t GCR; /*!< Global Configuration register */ -} -CFG_TypeDef; - -/** @addtogroup CFG_Registers_Reset_Value - * @{ - */ - -#define CFG_GCR_RESET_VALUE ((uint8_t)0x00) - -/** - * @} - */ - -/** @addtogroup CFG_Registers_Bits_Definition - * @{ - */ - -#define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */ -#define CFG_GCR_AL ((uint8_t)0x02) /*!< Activation Level bit mask */ - -/** - * @} - */ -/*----------------------------------------------------------------------------ok*/ - -/** - * @brief SYSCFG - */ - -typedef struct SYSCFG_struct -{ - __IO uint8_t RMPCR3; /*!< Remap control register 3 */ - __IO uint8_t RMPCR1; /*!< Remap control register 1 */ - __IO uint8_t RMPCR2; /*!< Remap control register 2 */ -} -SYSCFG_TypeDef; - -/** @addtogroup SYSCFG_Registers_Reset_Value - * @{ - */ -#define SYSCFG_RMPCR1_RESET_VALUE ((uint8_t)0x0C) -#define SYSCFG_RMPCR2_RESET_VALUE ((uint8_t)0x00) -#define SYSCFG_RMPCR3_RESET_VALUE ((uint8_t)0x00) - -/** - * @} - */ - -/** @addtogroup SYSCFG_Registers_Bits_Definition - * @{ - */ - -/* For DMA Channel Mapping*/ -#define SYSCFG_RMPCR1_ADC1DMA_REMAP ((uint8_t)0x03) /*!< ADC1 DMA channel remapping */ -#define SYSCFG_RMPCR1_TIM4DMA_REMAP ((uint8_t)0x0C) /*!< TIM4 DMA channel remapping */ - - -/* For GPIO Reapping*/ -#define SYSCFG_RMPCR1_USART1TR_REMAP ((uint8_t)0x30) /*!< USART1_TX and USART1_RX remapping */ -#define SYSCFG_RMPCR1_USART1CK_REMAP ((uint8_t)0x40) /*!< USART1_CK remapping */ -#define SYSCFG_RMPCR1_SPI1_REMAP ((uint8_t)0x80) /*!< SPI1 remapping */ - -#define SYSCFG_RMPCR2_ADC1TRIG_REMAP ((uint8_t)0x01) /*!< ADC1 External Trigger remap */ -#define SYSCFG_RMPCR2_TIM2TRIG_REMAP ((uint8_t)0x02) /*!< TIM2 Trigger remap */ -#define SYSCFG_RMPCR2_TIM3TRIG_REMAP1 ((uint8_t)0x04) /*!< TIM3 Trigger remap 1 */ -#define SYSCFG_RMPCR2_TIM2TRIG_LSE ((uint8_t)0x08) /*!< TIM2 Trigger remap to LSE */ -#define SYSCFG_RMPCR2_TIM3TRIG_LSE ((uint8_t)0x10) /*!< TIM3 Trigger remap to LSE */ -#define SYSCFG_RMPCR2_SPI2_REMAP ((uint8_t)0x20) /*!< SPI2 remapping */ -#define SYSCFG_RMPCR2_TIM3TRIG_REMAP2 ((uint8_t)0x40) /*!< TIM3 Trigger remap 2 */ -#define SYSCFG_RMPCR2_TIM23BKIN_REMAP ((uint8_t)0x80) /*!< TIM2 & TIM3 Break input remap */ - -#define SYSCFG_RMPCR3_SPI1_REMAP ((uint8_t)0x01) /*!< SPI1 remapping */ -#define SYSCFG_RMPCR3_USART3TR_REMAP ((uint8_t)0x02) /*!< USART3_TX and USART3_RX remapping */ -#define SYSCFG_RMPCR3_USART3CK_REMAP ((uint8_t)0x04) /*!< USART3_CK remapping */ -#define SYSCFG_RMPCR3_TIM3CH1_REMAP ((uint8_t)0x08) /*!< TIM3 channel 1 remapping */ -#define SYSCFG_RMPCR3_TIM3CH2_REMAP ((uint8_t)0x10) /*!< TIM3 channel 2 remapping */ -#define SYSCFG_RMPCR3_CCO_REMAP ((uint8_t)0x20) /*!< CCO remapping */ - -/** - * @} - */ -/*----------------------------------------------------------------------------ok*/ - -/** - * @brief Clock Controller (CLK) - */ -typedef struct CLK_struct -{ - __IO uint8_t CKDIVR; /*!< Clock Master Divider Register */ - __IO uint8_t CRTCR; /*!< RTC Clock selection Register */ - __IO uint8_t ICKCR; /*!< Internal Clocks Control Register */ - __IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */ - __IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */ - __IO uint8_t CCOR; /*!< Configurable Clock Output Register */ - __IO uint8_t ECKCR; /*!< External Clocks Control Register */ - __IO uint8_t SCSR; /*!< System clock status Register */ - __IO uint8_t SWR; /*!< System clock Switch Register */ - __IO uint8_t SWCR; /*!< Switch Control Register */ - __IO uint8_t CSSR; /*!< Clock Security Sytem Register */ - __IO uint8_t CBEEPR; /*!< Clock BEEP Register */ - __IO uint8_t HSICALR; /*!< HSI Calibration Register */ - __IO uint8_t HSITRIMR; /*!< HSI clock Calibration Trimmer Register */ - __IO uint8_t HSIUNLCKR; /*!< HSI Unlock Register */ - __IO uint8_t REGCSR; /*!< Main regulator control status register */ - __IO uint8_t PCKENR3; /*!< Peripheral Clock Gating Register 3 */ -} -CLK_TypeDef; - -/** @addtogroup CLK_Registers_Reset_Value - * @{ - */ -#define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x03) -#define CLK_CRTCR_RESET_VALUE ((uint8_t)0x00) -#define CLK_ICKCR_RESET_VALUE ((uint8_t)0x11) -#define CLK_PCKENR1_RESET_VALUE ((uint8_t)0x00) -#define CLK_PCKENR2_RESET_VALUE ((uint8_t)0x80) -#define CLK_PCKENR3_RESET_VALUE ((uint8_t)0x00) -#define CLK_CCOR_RESET_VALUE ((uint8_t)0x00) -#define CLK_ECKCR_RESET_VALUE ((uint8_t)0x00) -#define CLK_SCSR_RESET_VALUE ((uint8_t)0x01) -#define CLK_SWR_RESET_VALUE ((uint8_t)0x01) -#define CLK_SWCR_RESET_VALUE ((uint8_t)0x00) -#define CLK_CSSR_RESET_VALUE ((uint8_t)0x00) -#define CLK_CBEEPR_RESET_VALUE ((uint8_t)0x00) -#define CLK_HSICALR_RESET_VALUE ((uint8_t)0x00) -#define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00) -#define CLK_HSIUNLCKR_RESET_VALUE ((uint8_t)0x00) -#define CLK_REGCSR_RESET_VALUE ((uint8_t)0xB9) -/** - * @} - */ - -/** @addtogroup CLK_Registers_Bits_Definition - * @{ - */ - -#define CLK_CKDIVR_CKM ((uint8_t)0x07) /*!< System clock prescaler mask */ - -#define CLK_CRTCR_RTCDIV ((uint8_t)0xE0) /*!< RTC clock prescaler mask*/ -#define CLK_CRTCR_RTCSEL ((uint8_t)0x1E) /*!< RTC clock output selection mask */ -#define CLK_CRTCR_RTCSWBSY ((uint8_t)0x01) /*!< RTC clock switch busy */ - -#define CLK_ICKCR_BEEPAHALT ((uint8_t)0x40) /*!< BEEP clock Active Halt/Halt mode */ -#define CLK_ICKCR_FHWU ((uint8_t)0x20) /*!< Fast Wake-up from Active Halt/Halt mode */ -#define CLK_ICKCR_SAHALT ((uint8_t)0x10) /*!< Slow Active-halt mode */ -#define CLK_ICKCR_LSIRDY ((uint8_t)0x08) /*!< Low speed internal RC oscillator ready */ -#define CLK_ICKCR_LSION ((uint8_t)0x04) /*!< Low speed internal RC oscillator enable */ -#define CLK_ICKCR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */ -#define CLK_ICKCR_HSION ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */ - -#define CLK_PCKENR1_TIM2 ((uint8_t)0x01) /*!< Timer 2 clock enable */ -#define CLK_PCKENR1_TIM3 ((uint8_t)0x02) /*!< Timer 3 clock enable */ -#define CLK_PCKENR1_TIM4 ((uint8_t)0x04) /*!< Timer 4 clock enable */ -#define CLK_PCKENR1_I2C1 ((uint8_t)0x08) /*!< I2C1 clock enable */ -#define CLK_PCKENR1_SPI1 ((uint8_t)0x10) /*!< SPI1 clock enable */ -#define CLK_PCKENR1_USART1 ((uint8_t)0x20) /*!< USART1 clock enable */ -#define CLK_PCKENR1_BEEP ((uint8_t)0x40) /*!< BEEP clock enable */ -#define CLK_PCKENR1_DAC ((uint8_t)0x80) /*!< DAC clock enable */ - -#define CLK_PCKENR2_ADC1 ((uint8_t)0x01) /*!< ADC1 clock enable */ -#define CLK_PCKENR2_TIM1 ((uint8_t)0x02) /*!< TIM1 clock enable */ -#define CLK_PCKENR2_RTC ((uint8_t)0x04) /*!< RTC clock enable */ -#define CLK_PCKENR2_LCD ((uint8_t)0x08) /*!< LCD clock enable */ -#define CLK_PCKENR2_DMA1 ((uint8_t)0x10) /*!< DMA1 clock enable */ -#define CLK_PCKENR2_COMP ((uint8_t)0x20) /*!< Comparator clock enable */ -#define CLK_PCKENR2_BOOTROM ((uint8_t)0x80) /*!< Boot ROM clock enable */ - -#define CLK_PCKENR3_AES ((uint8_t)0x01) /*!< AES clock enable */ -#define CLK_PCKENR3_TIM5 ((uint8_t)0x02) /*!< Timer 5 clock enable */ -#define CLK_PCKENR3_SPI2 ((uint8_t)0x04) /*!< SPI2 clock enable */ -#define CLK_PCKENR3_UASRT2 ((uint8_t)0x08) /*!< USART2 clock enable */ -#define CLK_PCKENR3_USART3 ((uint8_t)0x10) /*!< USART3 clock enable */ - -#define CLK_CCOR_CCODIV ((uint8_t)0xE0) /*!< Configurable Clock output prescaler */ -#define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output selection */ -#define CLK_CCOR_CCOSWBSY ((uint8_t)0x01) /*!< Configurable clock output switch busy flag */ - -#define CLK_ECKCR_LSEBYP ((uint8_t)0x20) /*!< Low speed external clock bypass */ -#define CLK_ECKCR_HSEBYP ((uint8_t)0x10) /*!< High speed external clock bypass */ -#define CLK_ECKCR_LSERDY ((uint8_t)0x08) /*!< Low speed external crystal oscillator ready */ -#define CLK_ECKCR_LSEON ((uint8_t)0x04) /*!< Low speed external crystal oscillator enable */ -#define CLK_ECKCR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */ -#define CLK_ECKCR_HSEON ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */ - -#define CLK_SCSR_CKM ((uint8_t)0x0F) /*!< System clock status bits */ - -#define CLK_SWR_SWI ((uint8_t)0x0F) /*!< System clock selection bits */ - -#define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */ -#define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */ -#define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */ -#define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy */ - -#define CLK_CSSR_CSSDGON ((uint8_t)0x10) /*!< Clock security sytem deglitcher system */ -#define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security sytem detection */ -#define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */ -#define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */ -#define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */ - -#define CLK_CBEEPR_CLKBEEPSEL ((uint8_t)0x06) /*!< Configurable BEEP clock source selection */ -#define CLK_CBEEPR_BEEPSWBSY ((uint8_t)0x01) /*!< BEEP clock busy in switch */ - -#define CLK_HSICALR_HSICAL ((uint8_t)0xFF) /*!< Copy of otpion byte trimming HSI oscillator */ - -#define CLK_HSITRIMR_HSITRIM ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer */ - -#define CLK_HSIUNLCKR_HSIUNLCK ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer unlock */ - -#define CLK_REGCSR_EEREADY ((uint8_t)0x80) /*!< Flash program memory and Data EEPROM ready */ -#define CLK_REGCSR_EEBUSY ((uint8_t)0x40) /*!< Flash program memory and Data EEPROM busy */ -#define CLK_REGCSR_LSEPD ((uint8_t)0x20) /*!< LSE power-down */ -#define CLK_REGCSR_HSEPD ((uint8_t)0x10) /*!< HSE power-down */ -#define CLK_REGCSR_LSIPD ((uint8_t)0x08) /*!< LSI power-down */ -#define CLK_REGCSR_HSIPD ((uint8_t)0x04) /*!< HSI power-down */ -#define CLK_REGCSR_REGOFF ((uint8_t)0x02) /*!< Main regulator OFF */ -#define CLK_REGCSR_REGREADY ((uint8_t)0x01) /*!< Main regulator ready */ - -/** - * @} - */ -/*----------------------------------------------------------------------------ok*/ - -/** - * @brief Comparator interface (COMP) - */ - -typedef struct COMP_struct -{ - __IO uint8_t CSR1; /*!< Control status register 1 */ - __IO uint8_t CSR2; /*!< Control status register 2 */ - __IO uint8_t CSR3; /*!< Control status register 3 */ - __IO uint8_t CSR4; /*!< Control status register 4 */ - __IO uint8_t CSR5; /*!< Control status register 5 */ -} -COMP_TypeDef; - - -/** @addtogroup COMP_Registers_Reset_Value - * @{ - */ -#define COMP_CSR1_RESET_VALUE ((uint8_t)0x00) -#define COMP_CSR2_RESET_VALUE ((uint8_t)0x00) -#define COMP_CSR3_RESET_VALUE ((uint8_t)0xC0) -#define COMP_CSR4_RESET_VALUE ((uint8_t)0x00) -#define COMP_CSR5_RESET_VALUE ((uint8_t)0x00) - -/** - * @} - */ - -/** @addtogroup COMP_Registers_Bits_Definition - * @{ - */ - -/* CSR1 */ -#define COMP_CSR1_IE1 ((uint8_t)0x20) /*!< Comparator 1 Interrupt Enable Mask. */ -#define COMP_CSR1_EF1 ((uint8_t)0x10) /*!< Comparator 1 Event Flag Mask. */ -#define COMP_CSR1_CMP1OUT ((uint8_t)0x08) /*!< Comparator 1 Ouptput Mask. */ -#define COMP_CSR1_STE ((uint8_t)0x04) /*!< Schmitt trigger enable Mask. */ -#define COMP_CSR1_CMP1 ((uint8_t)0x03) /*!< Comparator 1 Configuration Mask. */ - -/* CSR2 */ -#define COMP_CSR2_IE2 ((uint8_t)0x20) /*!< Comparator 2 Interrupt Enable Mask. */ -#define COMP_CSR2_EF2 ((uint8_t)0x10) /*!< Comparator 2 Event Flag Mask. */ -#define COMP_CSR2_CMP2OUT ((uint8_t)0x08) /*!< Comparator 2 Ouptput Mask. */ -#define COMP_CSR2_SPEED ((uint8_t)0x04) /*!< Comparator 2 speed modeMask. */ -#define COMP_CSR2_CMP2 ((uint8_t)0x03) /*!< Comparator 2 Configuration Mask. */ - -/* CSR3 */ -#define COMP_CSR3_OUTSEL ((uint8_t)0xC0) /*!< Comparator 2 output selection Mask. */ -#define COMP_CSR3_INSEL ((uint8_t)0x38) /*!< Inversion input selection Mask. */ -#define COMP_CSR3_VREFEN ((uint8_t)0x04) /*!< Internal reference voltage Enable Mask. */ -#define COMP_CSR3_WNDWE ((uint8_t)0x02) /*!< Window Mode Enable Mask. */ -#define COMP_CSR3_VREFOUTEN ((uint8_t)0x01) /*!< VREF Output Enable Mask. */ - -/* CSR4 */ -#define COMP_CSR4_NINVTRIG ((uint8_t)0x38) /*!< COMP2 non-inverting input Mask. */ -#define COMP_CSR4_INVTRIG ((uint8_t)0x07) /*!< COMP2 inverting input Mask. */ - -/* CSR5 */ -#define COMP_CSR5_DACTRIG ((uint8_t)0x38) /*!< DAC outputs Mask. */ -#define COMP_CSR5_VREFTRIG ((uint8_t)0x07) /*!< VREF outputs Mask. */ - -/** - * @} - */ - -/*----------------------------------------------------------------------------ok*/ - -/** - * @brief External Interrupt Controller (EXTI) - */ -typedef struct EXTI_struct -{ - __IO uint8_t CR1; /*!< The four LSB EXTI pin sensitivity */ - __IO uint8_t CR2; /*!< The four MSB EXTI pin sensitivity */ - __IO uint8_t CR3; /*!< EXTI port B & port D sensitivity */ - __IO uint8_t SR1; /*!< Pins Status flag register 1 */ - __IO uint8_t SR2; /*!< Ports Status flage register 2 */ - __IO uint8_t CONF1; /*!< Port interrupt selector */ - uint8_t RESERVED[4]; /*!< reserved area */ - __IO uint8_t CR4; /*!< EXTI port G & port H sensitivity */ - __IO uint8_t CONF2; /*!< Port interrupt selector */ -} -EXTI_TypeDef; - -/** @addtogroup EXTI_Registers_Reset_Value - * @{ - */ - -#define EXTI_CR1_RESET_VALUE ((uint8_t)0x00) -#define EXTI_CR2_RESET_VALUE ((uint8_t)0x00) -#define EXTI_CR3_RESET_VALUE ((uint8_t)0x00) -#define EXTI_CONF1_RESET_VALUE ((uint8_t)0x00) -#define EXTI_SR1_RESET_VALUE ((uint8_t)0x00) -#define EXTI_SR2_RESET_VALUE ((uint8_t)0x00) -#define EXTI_CR4_RESET_VALUE ((uint8_t)0x00) -#define EXTI_CONF2_RESET_VALUE ((uint8_t)0x00) - -/** - * @} - */ - -/** @addtogroup EXTI_Registers_Bits_Definition - * @{ - */ -/* CR1 */ -#define EXTI_CR1_P3IS ((uint8_t)0xC0) /*!< EXTI Pin 3 external interrupt sensitivity bit Mask */ -#define EXTI_CR1_P2IS ((uint8_t)0x30) /*!< EXTI Pin 2 external interrupt sensitivity bit Mask */ -#define EXTI_CR1_P1IS ((uint8_t)0x0C) /*!< EXTI Pin 1 external interrupt sensitivity bit Mask */ -#define EXTI_CR1_P0IS ((uint8_t)0x03) /*!< EXTI Pin 0 external interrupt sensitivity bit Mask */ - -/* CR2 */ -#define EXTI_CR2_P7IS ((uint8_t)0xC0) /*!< EXTI Pin 7 external interrupt sensitivity bit Mask */ -#define EXTI_CR2_P6IS ((uint8_t)0x30) /*!< EXTI Pin 6 external interrupt sensitivity bit Mask */ -#define EXTI_CR2_P5IS ((uint8_t)0x0C) /*!< EXTI Pin 5 external interrupt sensitivity bit Mask */ -#define EXTI_CR2_P4IS ((uint8_t)0x03) /*!< EXTI Pin 4 external interrupt sensitivity bit Mask */ - -/* CR3 */ -#define EXTI_CR3_PBIS ((uint8_t)0x03) /*!< EXTI PORTB external interrupt sensitivity bits Mask */ -#define EXTI_CR3_PDIS ((uint8_t)0x0C) /*!< EXTI PORTD external interrupt sensitivity bits Mask */ -#define EXTI_CR3_PEIS ((uint8_t)0x30) /*!< EXTI PORTE external interrupt sensitivity bits Mask */ -#define EXTI_CR3_PFIS ((uint8_t)0xC0) /*!< EXTI PORTF external interrupt sensitivity bits Mask */ - -/* CONF1 */ -#define EXTI_CONF1_PBLIS ((uint8_t)0x01) /*!< EXTI PORTB low interrupt selector bit Mask */ -#define EXTI_CONF1_PBHIS ((uint8_t)0x02) /*!< EXTI PORTB high interrupt selector bit Mask */ -#define EXTI_CONF1_PDLIS ((uint8_t)0x04) /*!< EXTI PORTD low interrupt selector bit Mask */ -#define EXTI_CONF1_PDHIS ((uint8_t)0x08) /*!< EXTI PORTD high interrupt selector bit Mask */ -#define EXTI_CONF1_PELIS ((uint8_t)0x10) /*!< EXTI PORTE low interrupt selector bit Mask */ -#define EXTI_CONF1_PEHIS ((uint8_t)0x20) /*!< EXTI PORTE high interrupt selector bit Mask */ -#define EXTI_CONF1_PFLIS ((uint8_t)0x40) /*!< EXTI PORTF low interrupt selector bit Mask */ -#define EXTI_CONF1_PFES ((uint8_t)0x80) /*!< EXTI PORTF or PORTE interrupt selector bit Mask */ - -/* CR4 */ -#define EXTI_CR4_PGIS ((uint8_t)0x03) /*!< EXTI PORTG external interrupt sensitivity bits Mask */ -#define EXTI_CR4_PHIS ((uint8_t)0x0C) /*!< EXTI PORTH external interrupt sensitivity bits Mask */ - -/* CONF2 */ -#define EXTI_CONF2_PFHIS ((uint8_t)0x01) /*!< EXTI PORTF high interrupt selector bit Mask */ -#define EXTI_CONF2_PGLIS ((uint8_t)0x02) /*!< EXTI PORTG low interrupt selector bit Mask */ -#define EXTI_CONF2_PGHIS ((uint8_t)0x04) /*!< EXTI PORTG high interrupt selector bit Mask */ -#define EXTI_CONF2_PHLIS ((uint8_t)0x08) /*!< EXTI PORTH low interrupt selector bit Mask */ -#define EXTI_CONF2_PHHIS ((uint8_t)0x10) /*!< EXTI PORTH high interrupt selector bit Mask */ -#define EXTI_CONF2_PGBS ((uint8_t)0x20) /*!< EXTI PORTB or PORTG interrupt selector bit Mask */ -#define EXTI_CONF2_PHDS ((uint8_t)0x40) /*!< EXTI PORTD or PORTH interrupt selector bit Mask */ - -/** - * @} - */ - -/*----------------------------------------------------------------------------ok*/ - -/** - * @brief FLASH and Data EEPROM - */ -typedef struct FLASH_struct -{ - __IO uint8_t CR1; /*!< Flash control register 1 */ - __IO uint8_t CR2; /*!< Flash control register 2 */ - __IO uint8_t PUKR; /*!< Flash program memory unprotection register */ - __IO uint8_t DUKR; /*!< Data EEPROM unprotection register */ - __IO uint8_t IAPSR; /*!< Flash in-application programming status register */ -} -FLASH_TypeDef; - -/** @addtogroup FLASH_Registers_Reset_Value - * @{ - */ -#define FLASH_CR1_RESET_VALUE ((uint8_t)0x00) -#define FLASH_CR2_RESET_VALUE ((uint8_t)0x00) -#define FLASH_PUKR_RESET_VALUE ((uint8_t)0xAE) -#define FLASH_DUKR_RESET_VALUE ((uint8_t)0x56) -#define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40) - - -/** - * @} - */ - -/** @addtogroup FLASH_Registers_Bits_Definition - * @{ - */ -#define FLASH_CR1_EEPM ((uint8_t)0x08) /*!< Flash low power selection during Run and Low power run mode Mask */ -#define FLASH_CR1_WAITM ((uint8_t)0x04) /*!< Flash low power selection during Wait and Low power wait mode Mask */ -#define FLASH_CR1_IE ((uint8_t)0x02) /*!< Flash Interrupt enable Mask */ -#define FLASH_CR1_FIX ((uint8_t)0x01) /*!< Fix programming time Mask */ - -#define FLASH_CR2_OPT ((uint8_t)0x80) /*!< Enable write access to option bytes*/ -#define FLASH_CR2_WPRG ((uint8_t)0x40) /*!< Word write once Mask */ -#define FLASH_CR2_ERASE ((uint8_t)0x20) /*!< Erase block Mask */ -#define FLASH_CR2_FPRG ((uint8_t)0x10) /*!< Fast programming mode Mask */ -#define FLASH_CR2_PRG ((uint8_t)0x01) /*!< Program block Mask */ - -#define FLASH_IAPSR_HVOFF ((uint8_t)0x40) /*!< End of high voltage flag Mask */ -#define FLASH_IAPSR_DUL ((uint8_t)0x08) /*!< Data EEPROM unlocked flag Mask */ -#define FLASH_IAPSR_EOP ((uint8_t)0x04) /*!< End of operation flag Mask */ -#define FLASH_IAPSR_PUL ((uint8_t)0x02) /*!< Program memory unlocked flag Mask */ -#define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page Mask */ - -#define FLASH_PUKR_PUK ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */ - -#define FLASH_DUKR_DUK ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */ - - -/** - * @} - */ - -/*----------------------------------------------------------------------------*/ - -/** - * @brief Inter-Integrated Circuit (I2C) - */ -typedef struct I2C_struct -{ - __IO uint8_t CR1; /*!< I2C control register 1 */ - __IO uint8_t CR2; /*!< I2C control register 2 */ - __IO uint8_t FREQR; /*!< I2C frequency register */ - __IO uint8_t OARL; /*!< I2C own address register 1 LSB */ - __IO uint8_t OARH; /*!< I2C own address register 1 MSB */ - __IO uint8_t OAR2; /*!< I2C own address register 2 */ - __IO uint8_t DR; /*!< I2C data register */ - __IO uint8_t SR1; /*!< I2C status register 1 */ - __IO uint8_t SR2; /*!< I2C status register 2 */ - __IO uint8_t SR3; /*!< I2C status register 3 */ - __IO uint8_t ITR; /*!< I2C interrupt & DMA register */ - __IO uint8_t CCRL; /*!< I2C clock control register low */ - __IO uint8_t CCRH; /*!< I2C clock control register high */ - __IO uint8_t TRISER; /*!< I2C maximum rise time register */ - __IO uint8_t PECR; /*!< I2CPacket Error Checking register */ -} -I2C_TypeDef; - -/** @addtogroup I2C_Registers_Reset_Value - * @{ - */ -#define I2C_CR1_RESET_VALUE ((uint8_t)0x00) -#define I2C_CR2_RESET_VALUE ((uint8_t)0x00) -#define I2C_FREQR_RESET_VALUE ((uint8_t)0x00) -#define I2C_OARL_RESET_VALUE ((uint8_t)0x00) -#define I2C_OARH_RESET_VALUE ((uint8_t)0x00) -#define I2C_OAR2_RESET_VALUE ((uint8_t)0x00) -#define I2C_DR_RESET_VALUE ((uint8_t)0x00) -#define I2C_SR1_RESET_VALUE ((uint8_t)0x00) -#define I2C_SR2_RESET_VALUE ((uint8_t)0x00) -#define I2C_SR3_RESET_VALUE ((uint8_t)0x00) -#define I2C_ITR_RESET_VALUE ((uint8_t)0x00) -#define I2C_CCRL_RESET_VALUE ((uint8_t)0x00) -#define I2C_CCRH_RESET_VALUE ((uint8_t)0x00) -#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02) -#define I2C_PECR_RESET_VALUE ((uint8_t)0x00) - -/** - * @} - */ - -/** @addtogroup I2C_Registers_Bits_Definition - * @{ - */ - -#define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */ -#define I2C_CR1_ENGC ((uint8_t)0x40) /*!< General Call Enable */ -#define I2C_CR1_ENPEC ((uint8_t)0x20) /*!< PEC Enable */ -#define I2C_CR1_ARP ((uint8_t)0x10) /*!< ARP Enable */ -#define I2C_CR1_SMBTYPE ((uint8_t)0x08) /*!< SMBus type */ -#define I2C_CR1_SMBUS ((uint8_t)0x02) /*!< SMBus mode */ -#define I2C_CR1_PE ((uint8_t)0x01) /*!< Peripheral Enable */ - -#define I2C_CR2_SWRST ((uint8_t)0x80) /*!< Software Reset */ -#define I2C_CR2_ALERT ((uint8_t)0x20) /*!< SMBus Alert*/ -#define I2C_CR2_PEC ((uint8_t)0x10) /*!< Packet Error Checking */ -#define I2C_CR2_POS ((uint8_t)0x08) /*!< Acknowledge */ -#define I2C_CR2_ACK ((uint8_t)0x04) /*!< Acknowledge Enable */ -#define I2C_CR2_STOP ((uint8_t)0x02) /*!< Stop Generation */ -#define I2C_CR2_START ((uint8_t)0x01) /*!< Start Generation */ - -#define I2C_FREQR_FREQ ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */ - -#define I2C_OARL_ADD ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */ -#define I2C_OARL_ADD0 ((uint8_t)0x01) /*!< Interface Address bit0 */ - -#define I2C_OARH_ADDMODE ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */ -#define I2C_OARH_ADDCONF ((uint8_t)0x40) /*!< Address mode configuration */ -#define I2C_OARH_ADD ((uint8_t)0x06) /*!< Interface Address bits [9..8] */ - -#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */ -#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ - -#define I2C_DR_DR ((uint8_t)0xFF) /*!< Data Register */ - -#define I2C_SR1_TXE ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */ -#define I2C_SR1_RXNE ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */ -#define I2C_SR1_STOPF ((uint8_t)0x10) /*!< Stop detection (Slave mode) */ -#define I2C_SR1_ADD10 ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */ -#define I2C_SR1_BTF ((uint8_t)0x04) /*!< Byte Transfer Finished */ -#define I2C_SR1_ADDR ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */ -#define I2C_SR1_SB ((uint8_t)0x01) /*!< Start Bit (Master mode) */ - -#define I2C_SR2_SMBALERT ((uint8_t)0x80) /*!< SMBus Alert */ -#define I2C_SR2_TIMEOUT ((uint8_t)0x40) /*!< Time out or TLow error */ -#define I2C_SR2_WUFH ((uint8_t)0x20) /*!< Wake-up from Halt */ -#define I2C_SR2_PECERR ((uint8_t)0x10) /*!< PEC error in reception */ -#define I2C_SR2_OVR ((uint8_t)0x08) /*!< Overrun/Underrun */ -#define I2C_SR2_AF ((uint8_t)0x04) /*!< Acknowledge Failure */ -#define I2C_SR2_ARLO ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */ -#define I2C_SR2_BERR ((uint8_t)0x01) /*!< Bus Error */ - -#define I2C_SR3_DUALF ((uint8_t)0x80) /*!< Dual flag (Slave mode) */ -#define I2C_SR3_SMBHOST ((uint8_t)0x40) /*!< SMBus Host Header (Slave mode) */ -#define I2C_SR3_SMBDEFAULT ((uint8_t)0x20) /*!< SMBus Default Header (Slave mode) */ -#define I2C_SR3_GENCALL ((uint8_t)0x10) /*!< General Call Header (Slave mode) */ -#define I2C_SR3_TRA ((uint8_t)0x04) /*!< Transmitter/Receiver */ -#define I2C_SR3_BUSY ((uint8_t)0x02) /*!< Bus Busy */ -#define I2C_SR3_MSL ((uint8_t)0x01) /*!< Master/Slave */ - -#define I2C_ITR_LAST ((uint8_t)0x10) /*!< DMA Last transfer */ -#define I2C_ITR_DMAEN ((uint8_t)0x08) /*!< DMA request Enable */ -#define I2C_ITR_ITBUFEN ((uint8_t)0x04) /*!< Buffer Interrupt Enable */ -#define I2C_ITR_ITEVTEN ((uint8_t)0x02) /*!< Event Interrupt Enable */ -#define I2C_ITR_ITERREN ((uint8_t)0x01) /*!< Error Interrupt Enable */ - -#define I2C_CCRL_CCR ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */ - -#define I2C_CCRH_FS ((uint8_t)0x80) /*!< Master Mode Selection */ -#define I2C_CCRH_DUTY ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */ -#define I2C_CCRH_CCR ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */ - -#define I2C_TRISER_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ - -#define I2C_PECR_PEC ((uint8_t)0xFF) /*!< Packet error checking */ - -/** - * @} - */ - -/*----------------------------------------------------------------------------*/ - -/** - * @brief IR digital interface (IRTIM) - */ -typedef struct IRTIM_struct -{ - __IO uint8_t CR; /*!< control register */ -} -IRTIM_TypeDef; -/** @addtogroup IRTIM_Registers_Reset_Value - * @{ - */ -#define IRTIM_CR_RESET_VALUE ((uint8_t)0x00) - - -/** -* @} -*/ - -/** @addtogroup IRTIM_Registers_Bits_Definition - * @{ - */ -/* CR*/ -#define IRTIM_CR_EN ((uint8_t)0x01) /*!< IRTIM_OUT enable Mask. */ -#define IRTIM_CR_HSEN ((uint8_t)0x02) /*!< High sink open drain buffer enable Mask */ - -/** - * @} - */ - -/*----------------------------------------------------------------------------*/ - -/** - * @brief Interrupt Controller (ITC) - */ -typedef struct ITC_struct -{ - __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */ - __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */ - __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */ - __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */ - __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */ - __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */ - __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */ - __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */ -} -ITC_TypeDef; - -/** @addtogroup ITC_Registers_Reset_Value - * @{ - */ -#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers 0 to 7 */ -/** - * @} - */ - -/*----------------------------------------------------------------------------*/ - -/** - * @brief Internal Low Speed Watchdog (IWDG) - */ -typedef struct IWDG_struct -{ - __IO uint8_t KR; /*!< Low Speed Watchdog Key Register */ - __IO uint8_t PR; /*!< Low Speed Watchdog Prescaler Register */ - __IO uint8_t RLR; /*!< Low Speed Watchdog Reload Register */ -} -IWDG_TypeDef; - -/** @addtogroup IWDG_Registers_Reset_Value - * @{ - */ -#define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF) /*! - #define enableInterrupts() _rim_() /*! - #define enableInterrupts() __enable_interrupt() /* enable interrupts */ - #define disableInterrupts() __disable_interrupt() /* disable interrupts */ - #define rim() __enable_interrupt() /* enable interrupts */ - #define sim() __disable_interrupt() /* disable interrupts */ - #define nop() __no_operation() /* No Operation */ - #define trap() __trap() /* Trap (soft IT) */ - #define wfi() __wait_for_interrupt() /* Wait For Interrupt */ - #define wfe() __wait_for_event(); /* Wait for event */ - #define halt() __halt() /* Halt */ -#endif /* _RAISONANCE_ */ - -/*============================== Interrupt vector Handling ========================*/ - -#ifdef _COSMIC_ - #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void) - #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void) -#endif /* _COSMIC_ */ - -#ifdef _RAISONANCE_ - #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b - #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap -#endif /* _RAISONANCE_ */ - -#ifdef _IAR_ - #define STRINGVECTOR(x) #x - #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) - #define INTERRUPT_HANDLER( a, b ) \ - _Pragma( VECTOR_ID( (b)+2 ) ) \ - __interrupt void (a)( void ) - #define INTERRUPT_HANDLER_TRAP(a) \ - _Pragma( VECTOR_ID( 1 ) ) \ - __interrupt void (a) (void) -#endif /* _IAR_ */ - -/*============================== Interrupt Handler declaration ========================*/ -#ifdef _COSMIC_ - #define INTERRUPT @far @interrupt -#elif defined(_IAR_) - #define INTERRUPT __interrupt -#endif /* _COSMIC_ */ - -/*============================== Handling bits ====================================*/ -/*----------------------------------------------------------------------------- -Method : I -Description : Handle the bit from the character variables. -Comments : The different parameters of commands are - - VAR : Name of the character variable where the bit is located. - - Place : Bit position in the variable (7 6 5 4 3 2 1 0) - - Value : Can be 0 (reset bit) or not 0 (set bit) - The "MskBit" command allows to select some bits in a source - variables and copy it in a destination var (return the value). - The "ValBit" command returns the value of a bit in a char - variable: the bit is reseted if it returns 0 else the bit is set. - This method generates not an optimised code yet. ------------------------------------------------------------------------------*/ -#define SetBit(VAR,Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) -#define ClrBit(VAR,Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) ) - -#define ChgBit(VAR,Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) -#define AffBit(VAR,Place,Value) ((Value) ? \ - ((VAR) |= ((uint8_t)1<<(Place))) : \ - ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255))) -#define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) ) - -#define ValBit(VAR,Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place))) - -#define BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF)) /*!< Returns the low byte of the 32-bit value */ -#define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8))) /*!< Returns the second byte of the 32-bit value */ -#define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */ -#define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */ - -/*============================== Assert Macros ====================================*/ -#define IS_STATE_VALUE(STATE) \ - (((STATE) == SET) || \ - ((STATE) == RESET)) - -/*----------------------------------------------------------------------------- -Method : II -Description : Handle directly the bit. -Comments : The idea is to handle directly with the bit name. For that, it is - necessary to have RAM area descriptions (example: HW register...) - and the following command line for each area. - This method generates the most optimized code. ------------------------------------------------------------------------------*/ - -#define AREA 0x00 /* The area of bits begins at address 0x10. */ - -#define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) ) -#define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) ) -#define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) ) - - -#endif /* __STM8L15x_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3