From e3f3b4cd2c8b1af674bf965346426451ae4dee84 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 7 Feb 2012 18:57:30 +0000
Subject: Fixed bug 3484942.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3934 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/adc_lld.h | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx')

diff --git a/os/hal/platforms/STM32F4xx/adc_lld.h b/os/hal/platforms/STM32F4xx/adc_lld.h
index ad70d3e03..21723bd70 100644
--- a/os/hal/platforms/STM32F4xx/adc_lld.h
+++ b/os/hal/platforms/STM32F4xx/adc_lld.h
@@ -46,11 +46,8 @@
 
 /**
  * @brief   Maximum HSE  clock frequency.
- * @note    This value is arbitrary defined, the current datasheet does not
- *          define a maximum value (it is TBD). A value of 36MHz is mentioned
- *          but without relationship to VDD ranges.
  */
-#define STM32_ADCCLK_MAX        42000000
+#define STM32_ADCCLK_MAX        36000000
 /** @} */
 
 /**
@@ -123,9 +120,9 @@
 /**
  * @brief   ADC common clock divider.
  * @note    This setting is influenced by the VDDA voltage and other
- *          external conditions, please refer to the STM32L15x datasheet
+ *          external conditions, please refer to the STM32F4xx datasheet
  *          for more info.<br>
- *          See section 6.3.15 "12-bit ADC characteristics".
+ *          See section 5.3.20 "12-bit ADC characteristics".
  */
 #if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
 #define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV2
-- 
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