From 7fb7b8475cf8df99d55a5479dc5b265719533bdf Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 21 Oct 2012 17:13:48 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4768
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h
index 90b23f139..2f2df3f3c 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.h
+++ b/os/hal/platforms/STM32F4xx/hal_lld.h
@@ -89,7 +89,7 @@
 /**
  * @brief   Minimum PLLs input clock frequency.
  */
-#define STM32_PLLIN_MIN         1000000
+#define STM32_PLLIN_MIN         950000
 
 /**
  * @brief   Maximum PLLs VCO clock frequency.
@@ -97,9 +97,9 @@
 #define STM32_PLLVCO_MAX        432000000
 
 /**
- * @brief   Minimum PLLs VCO clock frequency.
+ * @brief   Maximum PLLs VCO clock frequency.
  */
-#define STM32_PLLVCO_MIN        64000000
+#define STM32_PLLVCO_MIN        192000000
 
 /**
  * @brief   Maximum PLL output clock frequency.
@@ -210,7 +210,7 @@
 #define STM32_MCO1SEL_HSE       (2 << 21)   /**< HSE clock on MCO1 pin.     */
 #define STM32_MCO1SEL_PLL       (3 << 21)   /**< PLL clock on MCO1 pin.     */
 
-#define STM32_I2SSRC_MASK       (1 << 23)   /**< I2SSRC mask.               */
+#define STM32_I2SSRC_MASK       (1 << 23)   /**< I2CSRC mask.               */
 #define STM32_I2SSRC_PLLI2S     (0 << 23)   /**< I2SSRC is PLLI2S.          */
 #define STM32_I2SSRC_CKIN       (1 << 23)   /**< I2S_CKIN is PLLI2S.        */
 
@@ -643,7 +643,7 @@
 
 /**
  * @brief   PLLN multiplier value.
- * @note    The allowed values are 64..432.
+ * @note    The allowed values are 192..432.
  * @note    The default value is calculated for a 168MHz system clock from
  *          an external 8MHz HSE clock.
  */
-- 
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