From 3cc94a962116a7529d8555bbf774cc5e31f9f1a7 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 13 Oct 2012 09:24:17 +0000
Subject: Fixed bug 3575297.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4750 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/adc_lld.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx')

diff --git a/os/hal/platforms/STM32F4xx/adc_lld.c b/os/hal/platforms/STM32F4xx/adc_lld.c
index bf0788dea..9f447f9a6 100644
--- a/os/hal/platforms/STM32F4xx/adc_lld.c
+++ b/os/hal/platforms/STM32F4xx/adc_lld.c
@@ -174,8 +174,6 @@ CH_IRQ_HANDLER(ADC1_2_3_IRQHandler) {
  */
 void adc_lld_init(void) {
 
-  ADC->CCR = STM32_ADC_ADCPRE;
-
 #if STM32_ADC_USE_ADC1
   /* Driver initialization.*/
   adcObjectInit(&ADCD1);
@@ -270,6 +268,10 @@ void adc_lld_start(ADCDriver *adcp) {
     }
 #endif /* STM32_ADC_USE_ADC3 */
 
+    /* This is a common register but apparently it requires that at least one
+       of the ADCs is clocked in order to allow writing, see bug 3575297.*/
+    ADC->CCR = STM32_ADC_ADCPRE << 16;
+
     /* ADC initial setup, starting the analog part here in order to reduce
        the latency when starting a conversion.*/
     adcp->adc->CR1 = 0;
-- 
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