From dc71ea034dc35f6a394a71831c95a73cd2ae06e7 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 2 Nov 2011 17:36:00 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3460
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 164 +++++++++++++++++++++++++++++++++++
 1 file changed, 164 insertions(+)
 create mode 100644 os/hal/platforms/STM32F4xx/hal_lld.c

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
new file mode 100644
index 000000000..74afa4bdb
--- /dev/null
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -0,0 +1,164 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F4xx/hal_lld.c
+ * @brief   STM32F4xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#define AIRCR_VECTKEY           0x05FA0000
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+  /* Reset of all peripherals.*/
+//  RCC->APB1RSTR = 0xFFFFFFFF;
+//  RCC->APB2RSTR = 0xFFFFFFFF;
+//  RCC->APB1RSTR = 0;
+//  RCC->APB2RSTR = 0;
+
+  /* SysTick initialization using the system clock.*/
+  SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
+  SysTick->VAL = 0;
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+                  SysTick_CTRL_ENABLE_Msk |
+                  SysTick_CTRL_TICKINT_Msk;
+
+  
+
+#if defined(STM32_DMA_REQUIRED)
+  dmaInit();
+#endif
+}
+
+/**
+ * @brief   STM32F2xx clocks and PLL initialization.
+ * @note    All the involved constants come from the file @p board.h.
+ * @note    This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+#if defined(STM32F2XX) || defined(__DOXYGEN__)
+/**
+ * @brief   Clocks and internal voltage initialization.
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+  /* PWR clock enable.*/
+  RCC->APB1ENR = RCC_APB1ENR_PWREN;
+
+  /* Initial clocks setup and wait for HSI stabilization, the MSI clock is
+     always enabled because it is the fallback clock when PLL the fails.*/
+  RCC->CR |= RCC_CR_HSION;
+  while ((RCC->CR & RCC_CR_HSIRDY) == 0)
+    ;                           /* Waits until HSI is stable.               */
+
+#if STM32_HSE_ENABLED
+  /* HSE activation.*/
+  RCC->CR |= RCC_CR_HSEON;
+  while ((RCC->CR & RCC_CR_HSERDY) == 0)
+    ;                           /* Waits until HSE is stable.               */
+#endif
+
+#if STM32_LSI_ENABLED
+  /* LSI activation.*/
+  RCC->CSR |= RCC_CSR_LSION;
+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+    ;                           /* Waits until LSI is stable.               */
+#endif
+
+#if STM32_LSE_ENABLED
+  /* LSE activation, have to unlock the register.*/
+  if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
+    PWR->CR |= PWR_CR_DBP;
+    RCC->BDCR |= RCC_BDCR_LSEON;
+    PWR->CR &= ~PWR_CR_DBP;
+  }
+  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;                           /* Waits until LSE is stable.               */
+#endif
+
+#if STM32_ACTIVATE_PLL
+  /* PLL activation.*/
+  RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | STM32_PLLM;
+  RCC->CR |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;                           /* Waits until PLL is stable.               */
+#endif
+
+#if STM32_ACTIVATE_PLLI2S
+  /* PLLI2S activation.*/
+  RCC->PLLI2SCFGR = STM32_PLI2SR_VALUE | STM32_PLLI2SN_VALUE;
+  RCC->CR |= RCC_CR_PLLI2SON;
+  while (!(RCC->CR & RCC_CR_PLLI2SRDY))
+    ;                           /* Waits until PLLI2S is stable.            */
+#endif
+
+  /* Other clock-related settings (dividers, MCO etc).*/
+  RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
+               STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+
+  /* Flash setup.                                                           */
+  FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | STM32_FLASHBITS;
+
+  /* Switching to the configured clock source if it is different from MSI.  */
+#if (STM32_SW != STM32_SW_HSI)
+  RCC->CFGR |= STM32_SW; /* Switches on the selected clock source.          */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;
+#endif
+#endif /* STM32_NO_INIT */
+}
+#else
+void stm32_clock_init(void) {}
+#endif
+
+/** @} */
-- 
cgit v1.2.3


From d5fa815855e904a5928441a45a37b798a0d618e9 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 5 Nov 2011 10:58:13 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3469
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 74afa4bdb..ae399242b 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -58,11 +58,12 @@
  */
 void hal_lld_init(void) {
 
-  /* Reset of all peripherals.*/
-//  RCC->APB1RSTR = 0xFFFFFFFF;
-//  RCC->APB2RSTR = 0xFFFFFFFF;
-//  RCC->APB1RSTR = 0;
-//  RCC->APB2RSTR = 0;
+  /* Reset of all peripherals. AHB3 is not reseted because it could have
+     been initialized in the board initialization file (board.c).*/
+  rccResetAHB1(!0);
+  rccResetAHB2(!0);
+  rccResetAPB1(!RCC_APB1RSTR_PWRRST);
+  rccResetAPB2(!RCC_APB2RSTR_SYSCFGRST);
 
   /* SysTick initialization using the system clock.*/
   SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
@@ -71,8 +72,6 @@ void hal_lld_init(void) {
                   SysTick_CTRL_ENABLE_Msk |
                   SysTick_CTRL_TICKINT_Msk;
 
-  
-
 #if defined(STM32_DMA_REQUIRED)
   dmaInit();
 #endif
-- 
cgit v1.2.3


From 9e51498e1196b28e5c073a7505df2ae08f05b59a Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 6 Nov 2011 09:39:57 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3474
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 15 ++++-----------
 1 file changed, 4 insertions(+), 11 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index ae399242b..bd88ad2da 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -84,10 +84,6 @@ void hal_lld_init(void) {
  *
  * @special
  */
-#if defined(STM32F2XX) || defined(__DOXYGEN__)
-/**
- * @brief   Clocks and internal voltage initialization.
- */
 void stm32_clock_init(void) {
 
 #if !STM32_NO_INIT
@@ -135,7 +131,7 @@ void stm32_clock_init(void) {
 
 #if STM32_ACTIVATE_PLLI2S
   /* PLLI2S activation.*/
-  RCC->PLLI2SCFGR = STM32_PLI2SR_VALUE | STM32_PLLI2SN_VALUE;
+  RCC->PLLI2SCFGR = STM32_PLLI2SR_VALUE | STM32_PLLI2SN_VALUE;
   RCC->CR |= RCC_CR_PLLI2SON;
   while (!(RCC->CR & RCC_CR_PLLI2SRDY))
     ;                           /* Waits until PLLI2S is stable.            */
@@ -145,19 +141,16 @@ void stm32_clock_init(void) {
   RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
                STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
 
-  /* Flash setup.                                                           */
+  /* Flash setup.*/
   FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | STM32_FLASHBITS;
 
-  /* Switching to the configured clock source if it is different from MSI.  */
+  /* Switching to the configured clock source if it is different from MSI.*/
 #if (STM32_SW != STM32_SW_HSI)
-  RCC->CFGR |= STM32_SW; /* Switches on the selected clock source.          */
+  RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */
   while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
     ;
 #endif
 #endif /* STM32_NO_INIT */
 }
-#else
-void stm32_clock_init(void) {}
-#endif
 
 /** @} */
-- 
cgit v1.2.3


From 2848e99c07e4174412dd0879046b9c3f82961695 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 6 Nov 2011 12:25:34 +0000
Subject: STM32F4 support working, most device drivers still to test, report
 added.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3475 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index bd88ad2da..5033c41c8 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -142,7 +142,8 @@ void stm32_clock_init(void) {
                STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
 
   /* Flash setup.*/
-  FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | STM32_FLASHBITS;
+  FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
+               STM32_FLASHBITS;
 
   /* Switching to the configured clock source if it is different from MSI.*/
 #if (STM32_SW != STM32_SW_HSI)
-- 
cgit v1.2.3


From 0faef9a2928309385c52f25fb892ac46ced093ab Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 3 Dec 2011 08:49:51 +0000
Subject: Fixed bug 3449139, increased version numbers.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3552 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 5033c41c8..6922ff3df 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -62,8 +62,9 @@ void hal_lld_init(void) {
      been initialized in the board initialization file (board.c).*/
   rccResetAHB1(!0);
   rccResetAHB2(!0);
+  rccResetAHB3(!0);
   rccResetAPB1(!RCC_APB1RSTR_PWRRST);
-  rccResetAPB2(!RCC_APB2RSTR_SYSCFGRST);
+  rccResetAPB2(!0);
 
   /* SysTick initialization using the system clock.*/
   SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
@@ -152,6 +153,10 @@ void stm32_clock_init(void) {
     ;
 #endif
 #endif /* STM32_NO_INIT */
+
+  /* SYSCFG clock enabled here because it is a multi-functional unit shared
+     among multiple drivers.*/
+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
 }
 
 /** @} */
-- 
cgit v1.2.3


From edcb16ebebc3a72f5df73e883949255b30f64d74 Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 16 Dec 2011 12:49:14 +0000
Subject: STM32F4x. In HAL added support of power level detector.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3616 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 6922ff3df..b2862caa4 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -73,6 +73,12 @@ void hal_lld_init(void) {
                   SysTick_CTRL_ENABLE_Msk |
                   SysTick_CTRL_TICKINT_Msk;
 
+#if STM32_PVD_ENABLE
+  /* Power voltage detector initialization */
+  PWR->CR |= PWR_CR_PVDE;
+  PWR->CR |= STM32_PLS & STM32_PLS_MASK;
+#endif /* STM32_PVD_ENABLE */
+
 #if defined(STM32_DMA_REQUIRED)
   dmaInit();
 #endif
-- 
cgit v1.2.3


From 3ff51b09a448a0986cdfd388b40a790bf5033a32 Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 17 Dec 2011 11:36:46 +0000
Subject: PVD for STM32F4x code cleanups.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3623 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index b2862caa4..d33237c2d 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -74,9 +74,8 @@ void hal_lld_init(void) {
                   SysTick_CTRL_TICKINT_Msk;
 
 #if STM32_PVD_ENABLE
-  /* Power voltage detector initialization */
-  PWR->CR |= PWR_CR_PVDE;
-  PWR->CR |= STM32_PLS & STM32_PLS_MASK;
+  /* Programmable voltage detector initialization */
+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
 #endif /* STM32_PVD_ENABLE */
 
 #if defined(STM32_DMA_REQUIRED)
-- 
cgit v1.2.3


From 334c7d645d1eccc59b9e19678b5e47d1e3ae2320 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 21 Dec 2011 18:49:04 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3645
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 2 --
 1 file changed, 2 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index d33237c2d..fa87998c5 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -29,8 +29,6 @@
 #include "ch.h"
 #include "hal.h"
 
-#define AIRCR_VECTKEY           0x05FA0000
-
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
-- 
cgit v1.2.3


From da9678f49a11241924c18902f7169c818a3cf995 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 22 Dec 2011 12:38:21 +0000
Subject: Provisional STM32F2xx support.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3649 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index fa87998c5..6d78c32df 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -94,6 +94,11 @@ void stm32_clock_init(void) {
   /* PWR clock enable.*/
   RCC->APB1ENR = RCC_APB1ENR_PWREN;
 
+  /* PWR initialization.*/
+  PWR->CR = STM32_VOS;
+  while (PWR->CSR & PWR_CSR_VOSRDY)
+    ;                           /* Waits until power regulator is stable.   */
+
   /* Initial clocks setup and wait for HSI stabilization, the MSI clock is
      always enabled because it is the fallback clock when PLL the fails.*/
   RCC->CR |= RCC_CR_HSION;
-- 
cgit v1.2.3


From 22b48b6876d80efce354c8b4c432b1f4a6bcf795 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 22 Dec 2011 18:53:26 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3650
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 6d78c32df..38d46177e 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -96,7 +96,7 @@ void stm32_clock_init(void) {
 
   /* PWR initialization.*/
   PWR->CR = STM32_VOS;
-  while (PWR->CSR & PWR_CSR_VOSRDY)
+  while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
     ;                           /* Waits until power regulator is stable.   */
 
   /* Initial clocks setup and wait for HSI stabilization, the MSI clock is
-- 
cgit v1.2.3


From efa92aaed21cbaa80f4bc88a0ef9bb6bbb7aa3ee Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 4 Jan 2012 08:46:11 +0000
Subject: Realtime counter support in the generic HAL driver and
 implementations for al STM32 devices, others will follow.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3723 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 38d46177e..d9bf8374e 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -71,6 +71,9 @@ void hal_lld_init(void) {
                   SysTick_CTRL_ENABLE_Msk |
                   SysTick_CTRL_TICKINT_Msk;
 
+  /* DWT cycle counter enable.*/
+  DWT_CTRL |= DWT_CTRL_CYCCNTENA;
+
 #if STM32_PVD_ENABLE
   /* Programmable voltage detector initialization */
   PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
-- 
cgit v1.2.3


From c506b8f2b1bf2446442040cd3f00f8750754d5aa Mon Sep 17 00:00:00 2001
From: barthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 4 Jan 2012 20:03:49 +0000
Subject: PVD. Checked compilability on F1x, L1x, F4x. Testhal fro F1x

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/pvd2_dev@3732 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index d9bf8374e..71b8ad219 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -74,14 +74,15 @@ void hal_lld_init(void) {
   /* DWT cycle counter enable.*/
   DWT_CTRL |= DWT_CTRL_CYCCNTENA;
 
-#if STM32_PVD_ENABLE
-  /* Programmable voltage detector initialization */
-  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
-#endif /* STM32_PVD_ENABLE */
-
 #if defined(STM32_DMA_REQUIRED)
   dmaInit();
 #endif
+
+  /* Programmable voltage detector enable. */
+#if STM32_PVD_ENABLE
+  rccEnablePWRInterface(FALSE);
+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
 }
 
 /**
-- 
cgit v1.2.3


From 45c0b7f9bc8d295ac8bfd97cbe14f9bd10756a30 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 4 Jan 2012 22:00:44 +0000
Subject: Documentation related fixes and updated all the mcuconf.h for the
 STM32.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3735 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 71b8ad219..02905b6bd 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -78,7 +78,7 @@ void hal_lld_init(void) {
   dmaInit();
 #endif
 
-  /* Programmable voltage detector enable. */
+  /* Programmable voltage detector enable.*/
 #if STM32_PVD_ENABLE
   rccEnablePWRInterface(FALSE);
   PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
-- 
cgit v1.2.3


From 8824a54e5efd1cc239bd7af2f8cbe12481d7a247 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 10 Jan 2012 18:14:24 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3783
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 48 +++++++++++++++++++++++++++++++++++-
 1 file changed, 47 insertions(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 02905b6bd..a655231cd 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -41,6 +41,47 @@
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
+/**
+ * @brief   Initializes the backup domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+  /* Backup domain access enabled during initialization.*/
+  PWR->CR |= PWR_CR_DBP;
+
+  /* RTC clock initialization.*/
+#if STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+  /* RTC clock not required, backup domain reset as initialization.*/
+  RCC->BDCR = RCC_BDCR_BDRST;
+  RCC->BDCR = 0;
+#else /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+  /* If the backup domain hasn't been initialized yet then proceed with
+     initialization.*/
+  if (!(RCC->BDCR & RCC_BDCR_LSEON)) {
+    /* Backup domain reset.*/
+    RCC->BDCR = RCC_BDCR_BDRST;
+    RCC->BDCR = 0;
+
+    /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+    RCC->BDCR |= RCC_BDCR_LSEON;
+    while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+      ;                                     /* Waits until LSE is stable.   */
+#endif
+
+    /* Selects clock source.*/
+    RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL;
+
+    /* RTC enabled regardless its previous status, this will also prevent
+       successive initializations.*/
+    RCC->BDCR |= RCC_BDCR_RTCEN;
+  }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+
+  /*  Backup domain access disabled for operations safety.*/
+  PWR->CR &= ~PWR_CR_DBP;
+}
+
 /*===========================================================================*/
 /* Driver interrupt handlers.                                                */
 /*===========================================================================*/
@@ -74,13 +115,18 @@ void hal_lld_init(void) {
   /* DWT cycle counter enable.*/
   DWT_CTRL |= DWT_CTRL_CYCCNTENA;
 
+  /* PWR clock enabled.*/
+  rccEnablePWRInterface(FALSE);
+
+  /* Initializes the backup domain.*/
+  hal_lld_backup_domain_init();
+
 #if defined(STM32_DMA_REQUIRED)
   dmaInit();
 #endif
 
   /* Programmable voltage detector enable.*/
 #if STM32_PVD_ENABLE
-  rccEnablePWRInterface(FALSE);
   PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
 #endif /* STM32_PVD_ENABLE */
 }
-- 
cgit v1.2.3


From 1ed89364ca6b9b6c89d13f6d39f7b2d085c8f8e4 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 10 Jan 2012 18:30:38 +0000
Subject: Backup domain and RTC clock initialization added.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3785 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 26 ++++++++++----------------
 1 file changed, 10 insertions(+), 16 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index a655231cd..d26059d70 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -49,31 +49,25 @@ static void hal_lld_backup_domain_init(void) {
   /* Backup domain access enabled during initialization.*/
   PWR->CR |= PWR_CR_DBP;
 
-  /* RTC clock initialization.*/
-#if STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
-  /* RTC clock not required, backup domain reset as initialization.*/
-  RCC->BDCR = RCC_BDCR_BDRST;
-  RCC->BDCR = 0;
-#else /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
-  /* If the backup domain hasn't been initialized yet then proceed with
-     initialization.*/
-  if (!(RCC->BDCR & RCC_BDCR_LSEON)) {
+  /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+  if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
     /* Backup domain reset.*/
     RCC->BDCR = RCC_BDCR_BDRST;
-    RCC->BDCR = 0;
-
-    /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
-    RCC->BDCR |= RCC_BDCR_LSEON;
+    RCC->BDCR = RCC_BDCR_LSEON;
     while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
       ;                                     /* Waits until LSE is stable.   */
+  }
 #endif
 
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+  /* If the backup domain hasn't been initialized yet then proceed with
+     initialization.*/
+  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
     RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL;
 
-    /* RTC enabled regardless its previous status, this will also prevent
-       successive initializations.*/
+    /* RTC clock enabled.*/
     RCC->BDCR |= RCC_BDCR_RTCEN;
   }
 #endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
-- 
cgit v1.2.3


From 58f1fe92ee9c68ffd08bccd19f67eafbbc968a71 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 11 Jan 2012 18:02:20 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3788
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 1 +
 1 file changed, 1 insertion(+)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index d26059d70..00c560f08 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -54,6 +54,7 @@ static void hal_lld_backup_domain_init(void) {
   if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
     /* Backup domain reset.*/
     RCC->BDCR = RCC_BDCR_BDRST;
+    RCC->BDCR = 0;
     RCC->BDCR = RCC_BDCR_LSEON;
     while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
       ;                                     /* Waits until LSE is stable.   */
-- 
cgit v1.2.3


From 4e3e0d62789355cfc630012dfcab96c78d3fec2e Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 12 Jan 2012 18:26:26 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3797
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 00c560f08..3dd520c2c 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -46,8 +46,8 @@
  */
 static void hal_lld_backup_domain_init(void) {
 
-  /* Backup domain access enabled during initialization.*/
-  PWR->CR |= PWR_CR_DBP;
+  /* Backup domain access enabled and left open.*/
+  PWR->CR = PWR_CR_DBP;
 
   /* If enabled then the LSE is started.*/
 #if STM32_LSE_ENABLED
@@ -72,9 +72,6 @@ static void hal_lld_backup_domain_init(void) {
     RCC->BDCR |= RCC_BDCR_RTCEN;
   }
 #endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
-
-  /*  Backup domain access disabled for operations safety.*/
-  PWR->CR &= ~PWR_CR_DBP;
 }
 
 /*===========================================================================*/
-- 
cgit v1.2.3


From 17f9264b099705e80822be875a0dbc0658ad05fd Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 14 Jan 2012 13:30:33 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3810
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 3dd520c2c..9fbd34b08 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -47,18 +47,20 @@
 static void hal_lld_backup_domain_init(void) {
 
   /* Backup domain access enabled and left open.*/
-  PWR->CR = PWR_CR_DBP;
+  PWR->CR |= PWR_CR_DBP;
 
-  /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
-  if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
+  /* Reset BKP domain if different clock source selected.*/
+  if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){
     /* Backup domain reset.*/
     RCC->BDCR = RCC_BDCR_BDRST;
     RCC->BDCR = 0;
-    RCC->BDCR = RCC_BDCR_LSEON;
-    while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-      ;                                     /* Waits until LSE is stable.   */
   }
+
+  /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+  RCC->BDCR |= RCC_BDCR_LSEON;
+  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;                                     /* Waits until LSE is stable.   */
 #endif
 
 #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
@@ -66,7 +68,7 @@ static void hal_lld_backup_domain_init(void) {
      initialization.*/
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
-    RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL;
+    RCC->BDCR |= STM32_RTCSEL;
 
     /* RTC clock enabled.*/
     RCC->BDCR |= RCC_BDCR_RTCEN;
-- 
cgit v1.2.3


From e2448aac991fff9bc29d892de9d78c6d1714e81c Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 15 Jan 2012 09:37:27 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3811
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 9fbd34b08..d25431f76 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -50,7 +50,7 @@ static void hal_lld_backup_domain_init(void) {
   PWR->CR |= PWR_CR_DBP;
 
   /* Reset BKP domain if different clock source selected.*/
-  if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){
+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
     /* Backup domain reset.*/
     RCC->BDCR = RCC_BDCR_BDRST;
     RCC->BDCR = 0;
-- 
cgit v1.2.3


From de5dcbba856524599a8f06d3a9bdbf1b01db44c2 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 21 Jan 2012 14:29:42 +0000
Subject: License text updated with new year.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3846 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index d25431f76..e7c09cc06 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011 Giovanni Di Sirio.
+                 2011,2012 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
-- 
cgit v1.2.3


From 267cd61c1914bc1d71f47f020d391c2d3ac1c224 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 11 Feb 2012 08:57:22 +0000
Subject: Fixed bug 3485500.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3950 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index e7c09cc06..44de90602 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -107,7 +107,8 @@ void hal_lld_init(void) {
                   SysTick_CTRL_TICKINT_Msk;
 
   /* DWT cycle counter enable.*/
-  DWT_CTRL |= DWT_CTRL_CYCCNTENA;
+  SCS_DEMCR |= SCS_DEMCR_TRCENA;
+  DWT_CTRL  |= DWT_CTRL_CYCCNTENA;
 
   /* PWR clock enabled.*/
   rccEnablePWRInterface(FALSE);
-- 
cgit v1.2.3


From ad8290460d4f252fde3fcf435e525268ea0854df Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 3 May 2012 17:38:29 +0000
Subject: Added an HSE bypass option to the STM32 clock initialization.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4157 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 44de90602..8982da7b9 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -151,6 +151,10 @@ void stm32_clock_init(void) {
     ;                           /* Waits until HSI is stable.               */
 
 #if STM32_HSE_ENABLED
+#if defined(STM32_HSE_BYPASS)
+  /* HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEBYP;
+#endif
   /* HSE activation.*/
   RCC->CR |= RCC_CR_HSEON;
   while ((RCC->CR & RCC_CR_HSERDY) == 0)
-- 
cgit v1.2.3


From b04461616c2f33eccfb08a439c36344e9dda40c5 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 12 May 2012 09:22:43 +0000
Subject: Fixed bug 3503490.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4193 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 8982da7b9..61bceab37 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -189,7 +189,7 @@ void stm32_clock_init(void) {
 
 #if STM32_ACTIVATE_PLLI2S
   /* PLLI2S activation.*/
-  RCC->PLLI2SCFGR = STM32_PLLI2SR_VALUE | STM32_PLLI2SN_VALUE;
+  RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;
   RCC->CR |= RCC_CR_PLLI2SON;
   while (!(RCC->CR & RCC_CR_PLLI2SRDY))
     ;                           /* Waits until PLLI2S is stable.            */
-- 
cgit v1.2.3


From 93be331bcec89f81d0335fb7c5e239f0f02d6e0b Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 22 Oct 2012 08:52:18 +0000
Subject: STM32F2xx deleted and merged with STM32F4xx code.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4775 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 61bceab37..a1d3d3d79 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -20,7 +20,7 @@
 
 /**
  * @file    STM32F4xx/hal_lld.c
- * @brief   STM32F4xx HAL subsystem low level driver source.
+ * @brief   STM32F4xx/STM32F2xx HAL subsystem low level driver source.
  *
  * @addtogroup HAL
  * @{
@@ -140,9 +140,13 @@ void stm32_clock_init(void) {
   RCC->APB1ENR = RCC_APB1ENR_PWREN;
 
   /* PWR initialization.*/
+#if defined(STM32F4XX) || defined(__DOXYGEN__)
   PWR->CR = STM32_VOS;
   while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
     ;                           /* Waits until power regulator is stable.   */
+#else
+  PWR->CR = 0;
+#endif
 
   /* Initial clocks setup and wait for HSI stabilization, the MSI clock is
      always enabled because it is the fallback clock when PLL the fails.*/
-- 
cgit v1.2.3


From 7112dfa32e35f35998bf4ab05888317ef5aed59a Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 23 Oct 2012 20:51:36 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4777
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index a1d3d3d79..e3cf144e1 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -26,6 +26,8 @@
  * @{
  */
 
+/* TODO: LSEBYP like in F3.*/
+
 #include "ch.h"
 #include "hal.h"
 
@@ -155,12 +157,14 @@ void stm32_clock_init(void) {
     ;                           /* Waits until HSI is stable.               */
 
 #if STM32_HSE_ENABLED
+  /* HSE activation.*/
 #if defined(STM32_HSE_BYPASS)
   /* HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEBYP;
-#endif
-  /* HSE activation.*/
+  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#else
+  /* No HSE Bypass.*/
   RCC->CR |= RCC_CR_HSEON;
+#endif
   while ((RCC->CR & RCC_CR_HSERDY) == 0)
     ;                           /* Waits until HSE is stable.               */
 #endif
@@ -185,7 +189,8 @@ void stm32_clock_init(void) {
 
 #if STM32_ACTIVATE_PLL
   /* PLL activation.*/
-  RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | STM32_PLLM;
+  RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
+                 STM32_PLLM;
   RCC->CR |= RCC_CR_PLLON;
   while (!(RCC->CR & RCC_CR_PLLRDY))
     ;                           /* Waits until PLL is stable.               */
-- 
cgit v1.2.3


From 94e6acd97233a4633aed56ec8e71f16654ba01c1 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 16 Nov 2012 10:17:06 +0000
Subject: Fixed bug 3586425.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4826 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index e3cf144e1..521a1723a 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -208,9 +208,14 @@ void stm32_clock_init(void) {
   RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
                STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
 
-  /* Flash setup.*/
-  FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
-               STM32_FLASHBITS;
+  /* Flash setup.
+     Some old revisions of F4x MCUs randomly crashes with compiler
+     optimizations enabled AND flash caches enabled. */
+  if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
+    FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS;
+  else
+    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
+                 FLASH_ACR_DCEN | STM32_FLASHBITS;
 
   /* Switching to the configured clock source if it is different from MSI.*/
 #if (STM32_SW != STM32_SW_HSI)
-- 
cgit v1.2.3


From 5089bc85d642f39214d43045c685709632a86c68 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 23 Dec 2012 10:35:16 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4956
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F4xx/hal_lld.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 521a1723a..80bea7b51 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -208,14 +208,19 @@ void stm32_clock_init(void) {
   RCC->CFGR |= STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
                STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
 
-  /* Flash setup.
-     Some old revisions of F4x MCUs randomly crashes with compiler
+  /* Flash setup.*/
+#if defined(STM32_USE_REVISION_A_FIX)
+  /* Some old revisions of F4x MCUs randomly crashes with compiler
      optimizations enabled AND flash caches enabled. */
   if ((DBGMCU->IDCODE == 0x20006411) && (SCB->CPUID == 0x410FC241))
     FLASH->ACR = FLASH_ACR_PRFTEN | STM32_FLASHBITS;
   else
     FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
                  FLASH_ACR_DCEN | STM32_FLASHBITS;
+#else
+  FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |
+               FLASH_ACR_DCEN | STM32_FLASHBITS;
+#endif
 
   /* Switching to the configured clock source if it is different from MSI.*/
 #if (STM32_SW != STM32_SW_HSI)
-- 
cgit v1.2.3


From b999931853091a3683a9f9fa5a1eb2c1c5c856a2 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 25 Dec 2012 08:20:13 +0000
Subject: Code templates-related fixes.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4971 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 80bea7b51..1242bdc82 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -31,6 +31,10 @@
 #include "ch.h"
 #include "hal.h"
 
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
-- 
cgit v1.2.3


From 184a71345c6a36a9a8664eda8fbcc3ea728267a8 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 2 Feb 2013 10:58:09 +0000
Subject: Updated license years.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5102 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 1242bdc82..6400465ba 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
-- 
cgit v1.2.3


From 01f971ba1d63d8568789adf51cde22fb35f69e73 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 28 Feb 2013 16:23:19 +0000
Subject: Adjusted C file templates.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5339 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 6400465ba..dc9dc29e7 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -40,7 +40,7 @@
 /*===========================================================================*/
 
 /*===========================================================================*/
-/* Driver local variables.                                                   */
+/* Driver local variables and types.                                         */
 /*===========================================================================*/
 
 /*===========================================================================*/
-- 
cgit v1.2.3


From 853216256ad4cdacf5f94edb7d6b738c6be165a1 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 30 Mar 2013 10:32:37 +0000
Subject: Relicensing parts of the tree under the Apache 2.0 license.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5521 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 24 ++++++++++--------------
 1 file changed, 10 insertions(+), 14 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index dc9dc29e7..603371b2c 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
-- 
cgit v1.2.3


From eff9b74c9c3714a8aec6a61f86e84f38edfd213a Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 11 May 2013 07:05:28 +0000
Subject: Fixed bug #409.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5703 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F4xx/hal_lld.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'os/hal/platforms/STM32F4xx/hal_lld.c')

diff --git a/os/hal/platforms/STM32F4xx/hal_lld.c b/os/hal/platforms/STM32F4xx/hal_lld.c
index 603371b2c..f72812da9 100644
--- a/os/hal/platforms/STM32F4xx/hal_lld.c
+++ b/os/hal/platforms/STM32F4xx/hal_lld.c
@@ -95,11 +95,11 @@ void hal_lld_init(void) {
 
   /* Reset of all peripherals. AHB3 is not reseted because it could have
      been initialized in the board initialization file (board.c).*/
-  rccResetAHB1(!0);
-  rccResetAHB2(!0);
-  rccResetAHB3(!0);
-  rccResetAPB1(!RCC_APB1RSTR_PWRRST);
-  rccResetAPB2(!0);
+  rccResetAHB1(~0);
+  rccResetAHB2(~0);
+  rccResetAHB3(~0);
+  rccResetAPB1(~RCC_APB1RSTR_PWRRST);
+  rccResetAPB2(~0);
 
   /* SysTick initialization using the system clock.*/
   SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
-- 
cgit v1.2.3