From 10e2b91f3ecf6f85f8f4806bd99507e985c01cfe Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 7 Dec 2012 11:52:13 +0000
Subject: GPT, ICU, PWM tested on STM32F3xx.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4882 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F3xx/hal_lld.h   | 10 +++----
 os/hal/platforms/STM32F3xx/platform.mk |  3 ++
 os/hal/platforms/STM32F3xx/stm32_rcc.h | 54 ++++++++++++++++++++++++++++++++++
 3 files changed, 62 insertions(+), 5 deletions(-)

(limited to 'os/hal/platforms/STM32F3xx')

diff --git a/os/hal/platforms/STM32F3xx/hal_lld.h b/os/hal/platforms/STM32F3xx/hal_lld.h
index 348bba45c..270664abd 100644
--- a/os/hal/platforms/STM32F3xx/hal_lld.h
+++ b/os/hal/platforms/STM32F3xx/hal_lld.h
@@ -170,11 +170,11 @@
 #define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
 #define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
 
-#define STM32_PPRE2_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
-#define STM32_PPRE2_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
-#define STM32_PPRE2_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
-#define STM32_PPRE2_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
-#define STM32_PPRE2_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
+#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
+#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
+#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
+#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
+#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
 
 #define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI/2. */
 #define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is
diff --git a/os/hal/platforms/STM32F3xx/platform.mk b/os/hal/platforms/STM32F3xx/platform.mk
index becb7986c..0401a8ddf 100644
--- a/os/hal/platforms/STM32F3xx/platform.mk
+++ b/os/hal/platforms/STM32F3xx/platform.mk
@@ -1,6 +1,9 @@
 # List of all the STM32F3xx platform files.
 PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F3xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32F3xx/hal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c
diff --git a/os/hal/platforms/STM32F3xx/stm32_rcc.h b/os/hal/platforms/STM32F3xx/stm32_rcc.h
index 229333104..2144ee041 100644
--- a/os/hal/platforms/STM32F3xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F3xx/stm32_rcc.h
@@ -422,6 +422,33 @@
  * @name    TIM peripherals specific RCC operations
  * @{
  */
+/**
+ * @brief   Enables the TIM1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief   Disables the TIM1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief   Resets the TIM1 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
+
 /**
  * @brief   Enables the TIM2 peripheral clock.
  *
@@ -496,6 +523,33 @@
  * @api
  */
 #define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
+
+/**
+ * @brief   Enables the TIM8 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief   Disables the TIM8 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief   Resets the TIM8 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
 /** @} */
 
 /**
-- 
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