From 10e2b91f3ecf6f85f8f4806bd99507e985c01cfe Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 7 Dec 2012 11:52:13 +0000 Subject: GPT, ICU, PWM tested on STM32F3xx. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4882 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F3xx/hal_lld.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'os/hal/platforms/STM32F3xx/hal_lld.h') diff --git a/os/hal/platforms/STM32F3xx/hal_lld.h b/os/hal/platforms/STM32F3xx/hal_lld.h index 348bba45c..270664abd 100644 --- a/os/hal/platforms/STM32F3xx/hal_lld.h +++ b/os/hal/platforms/STM32F3xx/hal_lld.h @@ -170,11 +170,11 @@ #define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */ #define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */ -#define STM32_PPRE2_DIV1 (0 << 8) /**< HCLK divided by 1. */ -#define STM32_PPRE2_DIV2 (4 << 8) /**< HCLK divided by 2. */ -#define STM32_PPRE2_DIV4 (5 << 8) /**< HCLK divided by 4. */ -#define STM32_PPRE2_DIV8 (6 << 8) /**< HCLK divided by 8. */ -#define STM32_PPRE2_DIV16 (7 << 8) /**< HCLK divided by 16. */ +#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */ #define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI/2. */ #define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is -- cgit v1.2.3