From ed26815f85668f5eedc6c28581e8900f037cbba1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 10 Nov 2011 17:54:41 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3481 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/adc_lld.h | 5 +++ os/hal/platforms/STM32F1xx/hal_lld_f100.h | 5 +++ os/hal/platforms/STM32F1xx/hal_lld_f103.h | 6 +++ os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 5 +++ os/hal/platforms/STM32F1xx/stm32_dma.h | 61 +++++++++++++++++++++----- 5 files changed, 70 insertions(+), 12 deletions(-) (limited to 'os/hal/platforms/STM32F1xx') diff --git a/os/hal/platforms/STM32F1xx/adc_lld.h b/os/hal/platforms/STM32F1xx/adc_lld.h index e3a327afa..bd4ec3dee 100644 --- a/os/hal/platforms/STM32F1xx/adc_lld.h +++ b/os/hal/platforms/STM32F1xx/adc_lld.h @@ -85,6 +85,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief ADC1 driver enable switch. * @details If set to @p TRUE the support for ADC1 is included. @@ -107,6 +111,7 @@ #if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__) #define STM32_ADC_ADC1_IRQ_PRIORITY 5 #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index cdad07bc5..230b415ef 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -337,6 +337,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief Main clock source selection. * @note If the selected clock source is not the PLL then the PLL is not @@ -423,6 +427,7 @@ #if !defined(STM32_RTC) || defined(__DOXYGEN__) #define STM32_RTC STM32_RTC_LSI #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index 92144b5dc..ee265fe7f 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -508,6 +508,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief Main clock source selection. * @note If the selected clock source is not the PLL then the PLL is not @@ -601,6 +605,8 @@ #if !defined(STM32_RTC) || defined(__DOXYGEN__) #define STM32_RTC STM32_RTC_LSI #endif +/** @} */ + /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index 52de807d2..cc9b2f796 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -278,6 +278,10 @@ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ /** * @brief PLL1 main switch. * @note If this constant is set to @p TRUE then the PLL1 is initialized @@ -430,6 +434,7 @@ #if !defined(STM32_RTC) || defined(__DOXYGEN__) #define STM32_RTC STM32_RTC_LSI #endif +/** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.h b/os/hal/platforms/STM32F1xx/stm32_dma.h index bacd0a809..a33577af8 100644 --- a/os/hal/platforms/STM32F1xx/stm32_dma.h +++ b/os/hal/platforms/STM32F1xx/stm32_dma.h @@ -51,26 +51,56 @@ */ #define STM32_DMA_ISR_MASK 0x0F +/** + * @brief Returns the channel associated to the specified stream. + * + * @param[in] n the stream number (0...STM32_DMA_STREAMS-1) + * @param[in] c a stream/channel association word, one channel per + * nibble, not associated channels must be set to 0xF + * @return Always zero, in this platform there is no dynamic + * association between streams and channels. + */ +#define STM32_DMA_GETCHANNEL(n, c) 0 + /** * @name DMA streams identifiers * @{ */ -#define STM32_DMA1_STREAM1 (&_stm32_dma_streams[0]) -#define STM32_DMA1_STREAM2 (&_stm32_dma_streams[1]) -#define STM32_DMA1_STREAM3 (&_stm32_dma_streams[2]) -#define STM32_DMA1_STREAM4 (&_stm32_dma_streams[3]) -#define STM32_DMA1_STREAM5 (&_stm32_dma_streams[4]) -#define STM32_DMA1_STREAM6 (&_stm32_dma_streams[5]) -#define STM32_DMA1_STREAM7 (&_stm32_dma_streams[6]) -#define STM32_DMA2_STREAM1 (&_stm32_dma_streams[7]) -#define STM32_DMA2_STREAM2 (&_stm32_dma_streams[8]) -#define STM32_DMA2_STREAM3 (&_stm32_dma_streams[9]) -#define STM32_DMA2_STREAM4 (&_stm32_dma_streams[10]) -#define STM32_DMA2_STREAM5 (&_stm32_dma_streams[11]) +/** + * @brief Returns an unique numeric identifier for a DMA stream. + * + * @param[in] dma the DMA unit number + * @param[in] stream the stream number + * @return An unique numeric stream identifier. + */ +#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1)) + +/** + * @brief Returns a pointer to a stm32_dma_stream_t structure. + * + * @param[in] n the stream numeric identifier + * @return A pointer to the stm32_dma_stream_t constant structure + * associated to the DMA stream. + */ +#define STM32_DMA_STREAM(n) (&_stm32_dma_streams[n]) + +#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(0) +#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(1) +#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(2) +#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(3) +#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(4) +#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(5) +#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(6) +#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(7) +#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(8) +#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(9) +#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(10) +#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(11) /** @} */ /** * @name CR register constants common to all DMA types + * @{ */ #define STM32_DMA_CR_EN DMA_CCR1_EN #define STM32_DMA_CR_TEIE DMA_CCR1_TEIE @@ -97,6 +127,7 @@ /** * @name CR register constants only found in enhanced DMA + * @{ */ #define STM32_DMA_CR_CHSEL_MASK 0 /**< @brief Ignored by normal DMA. */ #define STM32_DMA_CR_CHSEL(n) 0 /**< @brief Ignored by normal DMA. */ @@ -104,6 +135,7 @@ /** * @name Status flags passed to the ISR callbacks + * @{ */ #define STM32_DMA_ISR_FEIF 0 #define STM32_DMA_ISR_DMEIF 0 @@ -149,6 +181,10 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); /* Driver macros. */ /*===========================================================================*/ +/** + * @name Macro Functions + * @{ + */ /** * @brief Associates a peripheral data register to a DMA stream. * @note This function can be invoked in both ISR or thread context. @@ -302,6 +338,7 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); #define dmaWaitCompletion(dmastp) \ while (((dmastp)->channel->CNDTR > 0) && \ ((dmastp)->channel->CCR & STM32_DMA_CR_EN)) +/** @} */ /*===========================================================================*/ /* External declarations. */ -- cgit v1.2.3