From 8824a54e5efd1cc239bd7af2f8cbe12481d7a247 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 10 Jan 2012 18:14:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3783 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F1xx/hal_lld.c | 67 ++++++++++++++++++-------- os/hal/platforms/STM32F1xx/hal_lld_f100.h | 20 +++++++- os/hal/platforms/STM32F1xx/hal_lld_f103.h | 20 +++++++- os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h | 20 +++++++- 4 files changed, 102 insertions(+), 25 deletions(-) (limited to 'os/hal/platforms/STM32F1xx') diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c index 653201363..bf3baca8a 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld.c +++ b/os/hal/platforms/STM32F1xx/hal_lld.c @@ -41,6 +41,47 @@ /* Driver local functions. */ /*===========================================================================*/ +/** + * @brief Initializes the backup domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled during initialization.*/ + PWR->CR |= PWR_CR_DBP; + + /* RTC clock initialization.*/ +#if STM32_RTCSEL == STM32_RTCSEL_NOCLOCK + /* RTC clock not required, backup domain reset as initialization.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; +#else /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if (!(RCC->BDCR & RCC_BDCR_LSEON)) { + /* Backup domain reset.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + + /* If enabled then the LSE is started.*/ +#if STM32_LSE_ENABLED + RCC->BDCR |= RCC_BDCR_LSEON; + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + + /* Selects clock source.*/ + RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL; + + /* RTC enabled regardless its previous status, this will also prevent + successive initializations.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + } +#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */ + + /* Backup domain access disabled for operations safety.*/ + PWR->CR &= ~PWR_CR_DBP; +} + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -70,13 +111,19 @@ void hal_lld_init(void) { /* DWT cycle counter enable.*/ DWT_CTRL |= DWT_CTRL_CYCCNTENA; + /* PWR and BD clocks enabled.*/ + rccEnablePWRInterface(FALSE); + rccEnableBKPInterface(FALSE); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + #if defined(STM32_DMA_REQUIRED) dmaInit(); #endif /* Programmable voltage detector enable.*/ #if STM32_PVD_ENABLE - rccEnablePWRInterface(FALSE); PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK); #endif /* STM32_PVD_ENABLE */ } @@ -122,15 +169,6 @@ void stm32_clock_init(void) { ; /* Waits until LSI is stable. */ #endif -#if STM32_LSE_ENABLED - /* LSE activation, have to unlock the register.*/ - PWR->CR |= PWR_CR_DBP; - RCC->BDCR |= RCC_BDCR_LSEON; - while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) - ; /* Waits until LSE is stable. */ - PWR->CR &= ~PWR_CR_DBP; -#endif - #if STM32_ACTIVATE_PLL /* PLL activation.*/ RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC; @@ -193,15 +231,6 @@ void stm32_clock_init(void) { ; /* Waits until LSI is stable. */ #endif -#if STM32_LSE_ENABLED - /* LSE activation, have to unlock the register.*/ - PWR->CR |= PWR_CR_DBP; - RCC->BDCR |= RCC_BDCR_LSEON; - while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) - ; /* Waits until LSE is stable. */ - PWR->CR &= ~PWR_CR_DBP; -#endif - /* Settings of various dividers and multipliers in CFGR2.*/ RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 | STM32_PREDIV1 | STM32_PREDIV1SRC; diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h index 13823e978..766e9e48a 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h @@ -648,8 +648,9 @@ #error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" #endif -#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) #error "HSI not enabled, required by STM32_MCOSEL" #endif @@ -870,6 +871,21 @@ #error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" #endif +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSECLK / 128) +#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK +#define STM32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + /** * @brief ADC frequency. */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h index a536dcf33..39b13cf38 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h @@ -981,8 +981,9 @@ #error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" #endif -#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) #error "HSI not enabled, required by STM32_MCOSEL" #endif @@ -1204,6 +1205,21 @@ #error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" #endif +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSECLK / 128) +#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK +#define STM32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + /** * @brief ADC frequency. */ diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h index 157741431..8e63ebaf3 100644 --- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h @@ -596,8 +596,9 @@ #error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" #endif -#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) #error "HSI not enabled, required by STM32_MCOSEL" #endif @@ -956,6 +957,21 @@ #error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" #endif +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__) +#define STM32_RTCCLK STM32_LSECLK +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK (STM32_HSECLK / 128) +#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK +#define STM32_RTCCLK 0 +#else +#error "invalid source selected for RTC clock" +#endif + /** * @brief ADC frequency. */ -- cgit v1.2.3