From 659ae9692564f5bd99435cfbf3564a5e78d09ace Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 21 Aug 2012 11:04:42 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4602
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F1xx/platform_f105_f107.mk | 29 +++++++++++++++++++++++
 os/hal/platforms/STM32F1xx/stm32_rcc.h           | 30 ++++++++++++++++++++++++
 2 files changed, 59 insertions(+)
 create mode 100644 os/hal/platforms/STM32F1xx/platform_f105_f107.mk

(limited to 'os/hal/platforms/STM32F1xx')

diff --git a/os/hal/platforms/STM32F1xx/platform_f105_f107.mk b/os/hal/platforms/STM32F1xx/platform_f105_f107.mk
new file mode 100644
index 000000000..2967a4762
--- /dev/null
+++ b/os/hal/platforms/STM32F1xx/platform_f105_f107.mk
@@ -0,0 +1,29 @@
+# List of all the STM32F1xx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \
+              ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32F1xx/adc_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32F1xx/ext_lld_isr.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/can_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
+			  ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \
+			  ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F1xx \
+              ${CHIBIOS}/os/hal/platforms/STM32 \
+              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1 \
+              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1 \
+              ${CHIBIOS}/os/hal/platforms/STM32/RTCv1 \
+              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1 \
+              ${CHIBIOS}/os/hal/platforms/STM32/OTGv1
+
diff --git a/os/hal/platforms/STM32F1xx/stm32_rcc.h b/os/hal/platforms/STM32F1xx/stm32_rcc.h
index bdf4cb85f..bc0a869b6 100644
--- a/os/hal/platforms/STM32F1xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F1xx/stm32_rcc.h
@@ -461,6 +461,36 @@
 #define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
 /** @} */
 
+/**
+ * @name    OTG peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_FS(lp) rccEnableAHB(RCC_AHBENR_OTGFSEN, lp)
+
+/**
+ * @brief   Disables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableOTG_FS(lp) rccDisableAHB(RCC_AHBENR_OTGFSEN, lp)
+
+/**
+ * @brief   Resets the OTG_FS peripheral.
+ *
+ * @api
+ */
+#define rccResetOTG_FS() rccResetAHB(RCC_AHBRSTR_OTGFSRST)
+/** @} */
+
 /**
  * @name    SDIO peripheral specific RCC operations
  * @{
-- 
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