From e0b177423e1b14ab942fbf40b79d60d13ae02eb5 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 15 May 2012 17:01:41 +0000
Subject: Initial STM32F0xx support.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4198 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/stm32f0xx.h | 3220 ++++++++++++++++++++++++++++++++
 1 file changed, 3220 insertions(+)
 create mode 100644 os/hal/platforms/STM32F0xx/stm32f0xx.h

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/stm32f0xx.h b/os/hal/platforms/STM32F0xx/stm32f0xx.h
new file mode 100644
index 000000000..07c252c11
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/stm32f0xx.h
@@ -0,0 +1,3220 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx.h
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    23-March-2012
+  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32F0xx devices.  
+  *          
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f0xx
+  * @{
+  */
+    
+#ifndef __STM32F0XX_H
+#define __STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32F-0 device used in your 
+   application 
+  */
+
+#if !defined (STM32F0XX)
+  #define STM32F0XX    /*!< STM32F0XX: STM32F0xx devices */
+#endif
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+
+ - STM32F0xx devices are STM32F050xx microcontrollers where the Flash memory 
+   density ranges between 32 and 64 Kbytes.
+  */
+
+#if !defined (STM32F0XX)
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif /* STM32F0XX */
+
+#if !defined  USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */
+#if !defined  (HSE_VALUE)     
+#define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 
+   Timeout value 
+   */
+#if !defined  (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSI start up */
+#endif /* HSI_STARTUP_TIMEOUT */
+
+#if !defined  (HSI_VALUE) 
+#define HSI_VALUE  ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI_VALUE */
+
+#if !defined  (HSI14_VALUE) 
+#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* HSI14_VALUE */
+
+#if !defined  (LSI_VALUE) 
+#define LSI_VALUE  ((uint32_t)40000)    /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+#endif /* LSI_VALUE */
+
+#if !defined  (LSE_VALUE) 
+#define LSE_VALUE  ((uint32_t)32768)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+/**
+ * @brief STM32F0xx Standard Peripheral Library version number V1.0.0
+   */
+#define __STM32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32F0XX_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
+#define __STM32F0XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F0XX_STDPERIPH_VERSION        ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32F0XX_STDPERIPH_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief STM32F0xx Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+#define __CM0_REV                 0 /*!< Core Revision r0p0                            */
+#define __MPU_PRESENT             0 /*!< STM32F0xx do not provide MPU                  */
+#define __NVIC_PRIO_BITS          2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                        */
+  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                          */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                          */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                      */
+
+/******  STM32F-0 specific Interrupt Numbers *********************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
+  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
+  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
+  RCC_IRQn                    = 4,      /*!< RCC Interrupt                                           */
+  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
+  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
+  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
+  TS_IRQn                     = 8,      /*!< TS Interrupt                                            */
+  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
+  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
+  DMA1_Channel4_5_IRQn        = 11,     /*!< DMA1 Channel 4 and Channel 5 Interrupts                 */
+  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
+  TIM1_BRK_UP_TRG_COM_IRQn    = 13,     /*!< TIM1 Break, Update, Trigger and Commutation Interrupts  */
+  TIM1_CC_IRQn                = 14,     /*!< TIM1 Capture Compare Interrupt                          */
+  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
+  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
+  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
+  TIM14_IRQn                  = 19,     /*!< TIM14 Interrupt                                         */
+  TIM15_IRQn                  = 20,     /*!< TIM15 Interrupt                                         */
+  TIM16_IRQn                  = 21,     /*!< TIM16 Interrupt                                         */
+  TIM17_IRQn                  = 22,     /*!< TIM17 Interrupt                                         */
+  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
+  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
+  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
+  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
+  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
+  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
+  CEC_IRQn                    = 30      /*!< CEC Interrupt                                           */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm0.h"
+#include "system_stm32f0xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
+  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
+  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
+  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
+  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
+  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
+  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
+  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
+  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
+  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
+  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
+  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
+   __IO uint32_t DR;          /*!< ADC data register,                                          Address offset:0x40 */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CCR;
+} ADC_Common_TypeDef;
+
+/** 
+  * @brief HDMI-CEC 
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< CEC control register,                                       Address offset:0x00 */
+  __IO uint32_t CFGR;         /*!< CEC configuration register,                                 Address offset:0x04 */
+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,                                      Address offset:0x08 */
+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,                                       Address offset:0x0C */
+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register,                          Address offset:0x10 */
+  __IO uint32_t IER;          /*!< CEC interrupt enable register,                              Address offset:0x14 */
+}CEC_TypeDef;
+
+/**
+  * @brief Comparator 
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x1C */
+} COMP_TypeDef;
+
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;       /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;      /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t   RESERVED0;    /*!< Reserved,                                                    0x05 */
+  uint16_t  RESERVED1;    /*!< Reserved,                                                    0x06 */
+  __IO uint32_t CR;       /*!< CRC Control register,                        Address offset: 0x08 */
+  uint32_t  RESERVED2;    /*!< Reserved,                                                    0x0C */
+  __IO uint32_t INIT;     /*!< Initial CRC value register,                  Address offset: 0x10 */
+} CRC_TypeDef;
+
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
+  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
+  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
+  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
+       uint32_t RESERVED[6];  /*!< Reserved,                                                                 0x14 */
+  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
+       uint32_t RESERVED1;    /*!< Reserved,                                                                 0x30 */
+  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register                                           */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register                                          */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register                                      */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register                                          */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,                            Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,                        Address offset: 0x04 */
+} DMA_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                             Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                                 Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,                  Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,                  Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,                   Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                                    Address offset: 0x14 */
+}EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+typedef struct
+{
+  __IO uint32_t ACR;          /*!<FLASH access control register,                 Address offset: 0x00 */
+  __IO uint32_t KEYR;         /*!<FLASH key register,                            Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;      /*!<FLASH OPT key register,                        Address offset: 0x08 */
+  __IO uint32_t SR;           /*!<FLASH status register,                         Address offset: 0x0C */
+  __IO uint32_t CR;           /*!<FLASH control register,                        Address offset: 0x10 */
+  __IO uint32_t AR;           /*!<FLASH address register,                        Address offset: 0x14 */
+  __IO uint32_t RESERVED;     /*!< Reserved,                                                     0x18 */
+  __IO uint32_t OBR;          /*!<FLASH option bytes register,                   Address offset: 0x1C */
+  __IO uint32_t WRPR;         /*!<FLASH option bytes register,                   Address offset: 0x20 */
+} FLASH_TypeDef;
+
+
+/** 
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint16_t RDP;          /*!<FLASH option byte Read protection,             Address offset: 0x00 */
+  __IO uint16_t USER;         /*!<FLASH option byte user options,                Address offset: 0x02 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                     0x04 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                     0x06 */
+  __IO uint16_t WRP0;         /*!<FLASH option byte write protection 0,          Address offset: 0x08 */
+  __IO uint16_t WRP1;         /*!<FLASH option byte write protection 1,          Address offset: 0x0C */
+} OB_TypeDef;
+  
+
+/** 
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
+  __IO uint16_t OTYPER;       /*!< GPIO port output type register,                           Address offset: 0x04 */
+  uint16_t RESERVED0;         /*!< Reserved,                                                                 0x06 */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,                          Address offset: 0x08 */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,                     Address offset: 0x0C */
+  __IO uint16_t IDR;          /*!< GPIO port input data register,                            Address offset: 0x10 */
+  uint16_t RESERVED1;         /*!< Reserved,                                                                 0x12 */
+  __IO uint16_t ODR;          /*!< GPIO port output data register,                           Address offset: 0x14 */
+  uint16_t RESERVED2;         /*!< Reserved,                                                                 0x16 */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,                     Address offset: 0x18 */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,                    Address offset: 0x1C */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function low register,                Address offset: 0x20-0x24 */
+  __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
+  uint16_t RESERVED3;         /*!< Reserved,                                                                 0x2A */
+}GPIO_TypeDef;
+
+/** 
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t CFGR1;       /*!< SYSCFG configuration register 1,                           Address offset: 0x00 */
+       uint32_t RESERVED;    /*!< Reserved,                                                                  0x04 */
+  __IO uint32_t EXTICR[4];   /*!< SYSCFG external interrupt configuration register,     Address offset: 0x14-0x08 */
+  __IO uint32_t CFGR2;       /*!< SYSCFG configuration register 2,                           Address offset: 0x18 */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
+}I2C_TypeDef;
+
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+
+/** 
+  * @brief Reset and Clock Control
+  */
+typedef struct
+{
+  __IO uint32_t CR;         /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t CFGR;       /*!< RCC clock configuration register,                            Address offset: 0x04 */
+  __IO uint32_t CIR;        /*!< RCC clock interrupt register,                                Address offset: 0x08 */
+  __IO uint32_t APB2RSTR;   /*!< RCC APB2 peripheral reset register,                          Address offset: 0x0C */
+  __IO uint32_t APB1RSTR;   /*!< RCC APB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHBENR;     /*!< RCC AHB peripheral clock register,                           Address offset: 0x14 */
+  __IO uint32_t APB2ENR;    /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x18 */
+  __IO uint32_t APB1ENR;    /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x1C */
+  __IO uint32_t BDCR;       /*!< RCC Backup domain control register,                          Address offset: 0x20 */ 
+  __IO uint32_t CSR;        /*!< RCC clock control & status register,                         Address offset: 0x24 */
+  __IO uint32_t AHBRSTR;    /*!< RCC AHB peripheral reset register,                           Address offset: 0x28 */
+  __IO uint32_t CFGR2;      /*!< RCC clock configuration register 2,                          Address offset: 0x2C */
+  __IO uint32_t CFGR3;      /*!< RCC clock configuration register 3,                          Address offset: 0x30 */
+  __IO uint32_t CR2;        /*!< RCC clock control register 2,                                Address offset: 0x34 */
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{                           
+  __IO uint32_t TR;         /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                   Address offset: 0x10 */
+       uint32_t RESERVED0;  /*!< Reserved,                                                 Address offset: 0x14 */
+       uint32_t RESERVED1;  /*!< Reserved,                                                 Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                     Address offset: 0x1C */
+       uint32_t RESERVED2;  /*!< Reserved,                                                 Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CAL;        /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+       uint32_t RESERVED3;  /*!< Reserved,                                                 Address offset: 0x48 */
+       uint32_t RESERVED4;  /*!< Reserved,                                                 Address offset: 0x4C */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                    Address offset: 0x60 */
+} RTC_TypeDef;
+
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+  
+typedef struct
+{
+  __IO uint16_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
+  uint16_t  RESERVED0;    /*!< Reserved, 0x02                                                            */
+  __IO uint16_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
+  uint16_t  RESERVED1;    /*!< Reserved, 0x06                                                            */
+  __IO uint16_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
+  uint16_t  RESERVED2;    /*!< Reserved, 0x0A                                                            */
+  __IO uint16_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
+  uint16_t  RESERVED3;    /*!< Reserved, 0x0E                                                            */
+  __IO uint16_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
+  uint16_t  RESERVED4;    /*!< Reserved, 0x12                                                            */
+  __IO uint16_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
+  uint16_t  RESERVED5;    /*!< Reserved, 0x16                                                            */
+  __IO uint16_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
+  uint16_t  RESERVED6;    /*!< Reserved, 0x1A                                                            */ 
+  __IO uint16_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
+  uint16_t  RESERVED7;    /*!< Reserved, 0x1E                                                            */
+  __IO uint16_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
+  uint16_t  RESERVED8;    /*!< Reserved, 0x22                                                            */    
+} SPI_TypeDef;
+
+
+/** 
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint16_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */
+  uint16_t      RESERVED0;       /*!< Reserved,                                                    0x02 */
+  __IO uint16_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */
+  uint16_t      RESERVED1;       /*!< Reserved,                                                    0x06 */
+  __IO uint16_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */
+  uint16_t      RESERVED2;       /*!< Reserved,                                                    0x0A */
+  __IO uint16_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */
+  uint16_t      RESERVED3;       /*!< Reserved,                                                    0x0E */
+  __IO uint16_t SR;              /*!< TIM status register,                         Address offset: 0x10 */
+  uint16_t      RESERVED4;       /*!< Reserved,                                                    0x12 */
+  __IO uint16_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */
+  uint16_t      RESERVED5;       /*!< Reserved,                                                    0x16 */
+  __IO uint16_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */
+  uint16_t      RESERVED6;       /*!< Reserved,                                                    0x1A */
+  __IO uint16_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */
+  uint16_t      RESERVED7;       /*!< Reserved,                                                    0x1E */
+  __IO uint16_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */
+  uint16_t      RESERVED8;       /*!< Reserved,                                                    0x22 */
+  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */
+  __IO uint16_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */
+  uint16_t      RESERVED10;      /*!< Reserved,                                                    0x2A */
+  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */
+  __IO uint16_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */
+  uint16_t      RESERVED12;      /*!< Reserved,                                                    0x32 */
+  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */
+  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */
+  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */
+  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */
+  __IO uint16_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */
+  uint16_t      RESERVED17;      /*!< Reserved,                                                    0x26 */
+  __IO uint16_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */
+  uint16_t      RESERVED18;      /*!< Reserved,                                                    0x4A */
+  __IO uint16_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */
+  uint16_t      RESERVED19;      /*!< Reserved,                                                    0x4E */
+  __IO uint16_t OR;              /*!< TIM option register,                         Address offset: 0x50 */
+  uint16_t      RESERVED20;      /*!< Reserved,                                                    0x52 */
+} TIM_TypeDef;
+
+/** 
+  * @brief Touch Sensing Controller (TSC)
+  */
+typedef struct
+{
+  __IO uint32_t CR;        /*!< TSC control register,                                     Address offset: 0x00 */
+  __IO uint32_t IER;       /*!< TSC interrupt enable register,                            Address offset: 0x04 */
+  __IO uint32_t ICR;       /*!< TSC interrupt clear register,                             Address offset: 0x08 */ 
+  __IO uint32_t ISR;       /*!< TSC interrupt status register,                            Address offset: 0x0C */
+  __IO uint32_t IOHCR;     /*!< TSC I/O hysteresis control register,                      Address offset: 0x10 */
+  __IO uint32_t RESERVED1; /*!< Reserved,                                                 Address offset: 0x14 */
+  __IO uint32_t IOASCR;    /*!< TSC I/O analog switch control register,                   Address offset: 0x18 */
+  __IO uint32_t RESERVED2; /*!< Reserved,                                                 Address offset: 0x1C */
+  __IO uint32_t IOSCR;     /*!< TSC I/O sampling control register,                        Address offset: 0x20 */
+  __IO uint32_t RESERVED3; /*!< Reserved,                                                 Address offset: 0x24 */
+  __IO uint32_t IOCCR;     /*!< TSC I/O channel control register,                         Address offset: 0x28 */
+  __IO uint32_t RESERVED4; /*!< Reserved,                                                 Address offset: 0x2C */
+  __IO uint32_t IOGCSR;    /*!< TSC I/O group control status register,                    Address offset: 0x30 */
+  __IO uint32_t IOGXCR[6]; /*!< TSC I/O group x counter register,                         Address offset: 0x34-48 */
+} TSC_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+  
+typedef struct
+{
+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
+  __IO uint16_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */
+  uint16_t  RESERVED1;  /*!< Reserved, 0x0E                                                 */  
+  __IO uint16_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
+  uint16_t  RESERVED2;  /*!< Reserved, 0x12                                                 */
+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
+  __IO uint16_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
+  uint16_t  RESERVED3;  /*!< Reserved, 0x1A                                                 */
+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
+  __IO uint16_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
+  uint16_t  RESERVED4;  /*!< Reserved, 0x26                                                 */
+  __IO uint16_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
+  uint16_t  RESERVED5;  /*!< Reserved, 0x2A                                                 */
+} USART_TypeDef;
+
+
+/** 
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APBPERIPH_BASE        PERIPH_BASE
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000)
+
+#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
+#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
+#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
+#define TIM14_BASE            (APBPERIPH_BASE + 0x00002000)
+#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
+#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
+#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
+#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
+#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
+#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
+#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
+#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
+#define DAC_BASE              (APBPERIPH_BASE + 0x00007400)
+#define CEC_BASE              (APBPERIPH_BASE + 0x00007800)
+
+#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
+#define COMP_BASE             (APBPERIPH_BASE + 0x0001001C)
+#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
+#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400)
+#define ADC_BASE              (APBPERIPH_BASE + 0x00012708)
+#define TIM1_BASE             (APBPERIPH_BASE + 0x00012C00)
+#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
+#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
+#define TIM15_BASE            (APBPERIPH_BASE + 0x00014000)
+#define TIM16_BASE            (APBPERIPH_BASE + 0x00014400)
+#define TIM17_BASE            (APBPERIPH_BASE + 0x00014800)
+#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
+#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FFFF800)        /*!< FLASH Option Bytes base address */
+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
+#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
+
+#define GPIOA_BASE            (AHB2PERIPH_BASE + 0x00000000)
+#define GPIOB_BASE            (AHB2PERIPH_BASE + 0x00000400)
+#define GPIOC_BASE            (AHB2PERIPH_BASE + 0x00000800)
+#define GPIOD_BASE            (AHB2PERIPH_BASE + 0x00000C00)
+#define GPIOF_BASE            (AHB2PERIPH_BASE + 0x00001400)
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define CEC                 ((CEC_TypeDef *) CEC_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define COMP                ((COMP_TypeDef *) COMP_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE) 
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define TSC                 ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for ADC_ISR register  ******************/
+#define ADC_ISR_AWD                          ((uint32_t)0x00000080)        /*!< Analog watchdog flag */
+#define ADC_ISR_OVR                          ((uint32_t)0x00000010)        /*!< Overrun flag */
+#define ADC_ISR_EOSEQ                        ((uint32_t)0x00000008)        /*!< End of Sequence flag */
+#define ADC_ISR_EOC                          ((uint32_t)0x00000004)        /*!< End of Conversion */
+#define ADC_ISR_EOSMP                        ((uint32_t)0x00000002)        /*!< End of sampling flag */
+#define ADC_ISR_ADRDY                        ((uint32_t)0x00000001)        /*!< ADC Ready */
+
+/* Old EOSEQ bit definition, maintained for legacy purpose */
+#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
+
+/********************  Bits definition for ADC_IER register  ******************/
+#define ADC_IER_AWDIE                        ((uint32_t)0x00000080)        /*!< Analog Watchdog interrupt enable */
+#define ADC_IER_OVRIE                        ((uint32_t)0x00000010)        /*!< Overrun interrupt enable */
+#define ADC_IER_EOSEQIE                      ((uint32_t)0x00000008)        /*!< End of Sequence of conversion interrupt enable */
+#define ADC_IER_EOCIE                        ((uint32_t)0x00000004)        /*!< End of Conversion interrupt enable */
+#define ADC_IER_EOSMPIE                      ((uint32_t)0x00000002)        /*!< End of sampling interrupt enable */
+#define ADC_IER_ADRDYIE                      ((uint32_t)0x00000001)        /*!< ADC Ready interrupt enable */
+
+/* Old EOSEQIE bit definition, maintained for legacy purpose */
+#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
+
+/********************  Bits definition for ADC_CR register  *******************/
+#define ADC_CR_ADCAL                         ((uint32_t)0x80000000)        /*!< ADC calibration */
+#define ADC_CR_ADSTP                         ((uint32_t)0x00000010)        /*!< ADC stop of conversion command */
+#define ADC_CR_ADSTART                       ((uint32_t)0x00000004)        /*!< ADC start of conversion */
+#define ADC_CR_ADDIS                         ((uint32_t)0x00000002)        /*!< ADC disable command */
+#define ADC_CR_ADEN                          ((uint32_t)0x00000001)        /*!< ADC enable control */
+
+/*******************  Bits definition for ADC_CFGR1 register  *****************/
+#define  ADC_CFGR1_AWDCH                      ((uint32_t)0x7C000000)       /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_CFGR1_AWDCH_0                    ((uint32_t)0x04000000)       /*!< Bit 0 */
+#define  ADC_CFGR1_AWDCH_1                    ((uint32_t)0x08000000)       /*!< Bit 1 */
+#define  ADC_CFGR1_AWDCH_2                    ((uint32_t)0x10000000)       /*!< Bit 2 */
+#define  ADC_CFGR1_AWDCH_3                    ((uint32_t)0x20000000)       /*!< Bit 3 */
+#define  ADC_CFGR1_AWDCH_4                    ((uint32_t)0x40000000)       /*!< Bit 4 */
+#define  ADC_CFGR1_AWDEN                      ((uint32_t)0x00800000)       /*!< Analog watchdog enable on regular channels */
+#define  ADC_CFGR1_AWDSGL                     ((uint32_t)0x00400000)       /*!< Enable the watchdog on a single channel or on all channels  */
+#define  ADC_CFGR1_DISCEN                     ((uint32_t)0x00010000)       /*!< Discontinuous mode on regular channels */
+#define  ADC_CFGR1_AUTOFF                     ((uint32_t)0x00008000)       /*!< ADC auto power off */
+#define  ADC_CFGR1_WAIT                       ((uint32_t)0x00004000)       /*!< ADC wait conversion mode */
+#define  ADC_CFGR1_CONT                       ((uint32_t)0x00002000)       /*!< Continuous Conversion */
+#define  ADC_CFGR1_OVRMOD                     ((uint32_t)0x00001000)       /*!< Overrun mode */
+#define  ADC_CFGR1_EXTEN                      ((uint32_t)0x00000C00)       /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define  ADC_CFGR1_EXTEN_0                    ((uint32_t)0x00000400)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTEN_1                    ((uint32_t)0x00000800)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL                     ((uint32_t)0x000001C0)       /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_CFGR1_EXTSEL_0                   ((uint32_t)0x00000040)       /*!< Bit 0 */
+#define  ADC_CFGR1_EXTSEL_1                   ((uint32_t)0x00000080)       /*!< Bit 1 */
+#define  ADC_CFGR1_EXTSEL_2                   ((uint32_t)0x00000100)       /*!< Bit 2 */
+#define  ADC_CFGR1_ALIGN                      ((uint32_t)0x00000020)       /*!< Data Alignment */
+#define  ADC_CFGR1_RES                        ((uint32_t)0x00000018)       /*!< RES[1:0] bits (Resolution) */
+#define  ADC_CFGR1_RES_0                      ((uint32_t)0x00000008)       /*!< Bit 0 */
+#define  ADC_CFGR1_RES_1                      ((uint32_t)0x00000010)       /*!< Bit 1 */
+#define  ADC_CFGR1_SCANDIR                    ((uint32_t)0x00000004)       /*!< Sequence scan direction */
+#define  ADC_CFGR1_DMACFG                     ((uint32_t)0x00000002)       /*!< Direct memory access configuration */
+#define  ADC_CFGR1_DMAEN                      ((uint32_t)0x00000001)       /*!< Direct memory access enable */
+
+/* Old WAIT bit definition, maintained for legacy purpose */
+#define  ADC_CFGR1_AUTDLY                     ADC_CFGR1_WAIT
+
+/*******************  Bits definition for ADC_CFGR2 register  *****************/
+#define  ADC_CFGR2_JITOFFDIV4                 ((uint32_t)0x80000000)       /*!< Jitter Off when ADC clocked by PCLK div4 */
+#define  ADC_CFGR2_JITOFFDIV2                 ((uint32_t)0x40000000)       /*!< Jitter Off when ADC clocked by PCLK div2 */
+
+/******************  Bit definition for ADC_SMPR register  ********************/
+#define  ADC_SMPR1_SMPR                      ((uint32_t)0x00000007)        /*!< SMPR[2:0] bits (Sampling time selection) */
+#define  ADC_SMPR1_SMPR_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  ADC_SMPR1_SMPR_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  ADC_SMPR1_SMPR_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog low threshold */
+
+/******************  Bit definition for ADC_CHSELR register  ******************/
+#define  ADC_CHSELR_CHSEL18                   ((uint32_t)0x00040000)        /*!< Channel 18 selection */
+#define  ADC_CHSELR_CHSEL17                   ((uint32_t)0x00020000)        /*!< Channel 17 selection */
+#define  ADC_CHSELR_CHSEL16                   ((uint32_t)0x00010000)        /*!< Channel 16 selection */
+#define  ADC_CHSELR_CHSEL15                   ((uint32_t)0x00008000)        /*!< Channel 15 selection */
+#define  ADC_CHSELR_CHSEL14                   ((uint32_t)0x00004000)        /*!< Channel 14 selection */
+#define  ADC_CHSELR_CHSEL13                   ((uint32_t)0x00002000)        /*!< Channel 13 selection */
+#define  ADC_CHSELR_CHSEL12                   ((uint32_t)0x00001000)        /*!< Channel 12 selection */
+#define  ADC_CHSELR_CHSEL11                   ((uint32_t)0x00000800)        /*!< Channel 11 selection */
+#define  ADC_CHSELR_CHSEL10                   ((uint32_t)0x00000400)        /*!< Channel 10 selection */
+#define  ADC_CHSELR_CHSEL9                    ((uint32_t)0x00000200)        /*!< Channel 9 selection */
+#define  ADC_CHSELR_CHSEL8                    ((uint32_t)0x00000100)        /*!< Channel 8 selection */
+#define  ADC_CHSELR_CHSEL7                    ((uint32_t)0x00000080)        /*!< Channel 7 selection */
+#define  ADC_CHSELR_CHSEL6                    ((uint32_t)0x00000040)        /*!< Channel 6 selection */
+#define  ADC_CHSELR_CHSEL5                    ((uint32_t)0x00000020)        /*!< Channel 5 selection */
+#define  ADC_CHSELR_CHSEL4                    ((uint32_t)0x00000010)        /*!< Channel 4 selection */
+#define  ADC_CHSELR_CHSEL3                    ((uint32_t)0x00000008)        /*!< Channel 3 selection */
+#define  ADC_CHSELR_CHSEL2                    ((uint32_t)0x00000004)        /*!< Channel 2 selection */
+#define  ADC_CHSELR_CHSEL1                    ((uint32_t)0x00000002)        /*!< Channel 1 selection */
+#define  ADC_CHSELR_CHSEL0                    ((uint32_t)0x00000001)        /*!< Channel 0 selection */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define  ADC_CCR_VBATEN                       ((uint32_t)0x01000000)       /*!< Voltage battery enable */
+#define  ADC_CCR_TSEN                         ((uint32_t)0x00800000)       /*!< Tempurature sensore enable */
+#define  ADC_CCR_VREFEN                       ((uint32_t)0x00400000)       /*!< Vrefint enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 HDMI-CEC (CEC)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CEC_CR register  *********************/
+#define  CEC_CR_CECEN                        ((uint32_t)0x00000001)       /*!< CEC Enable                         */
+#define  CEC_CR_TXSOM                        ((uint32_t)0x00000002)       /*!< CEC Tx Start Of Message            */
+#define  CEC_CR_TXEOM                        ((uint32_t)0x00000004)       /*!< CEC Tx End Of Message              */
+
+/*******************  Bit definition for CEC_CFGR register  *******************/
+#define  CEC_CFGR_SFT                        ((uint32_t)0x00000007)       /*!< CEC Signal Free Time               */
+#define  CEC_CFGR_RXTOL                      ((uint32_t)0x00000008)       /*!< CEC Tolerance                      */
+#define  CEC_CFGR_BRESTP                     ((uint32_t)0x00000010)       /*!< CEC Rx Stop                        */
+#define  CEC_CFGR_BREGEN                     ((uint32_t)0x00000020)       /*!< CEC Bit Rising Error generation    */
+#define  CEC_CFGR_LREGEN                     ((uint32_t)0x00000040)       /*!< CEC Long Period Error generation   */
+#define  CEC_CFGR_BRDNOGEN                   ((uint32_t)0x00000080)       /*!< CEC Broadcast no Error generation  */
+#define  CEC_CFGR_SFTOPT                     ((uint32_t)0x00000100)       /*!< CEC Signal Free Time optional      */
+#define  CEC_CFGR_OAR                        ((uint32_t)0x7FFF0000)       /*!< CEC Own Address                    */
+#define  CEC_CFGR_LSTN                       ((uint32_t)0x80000000)       /*!< CEC Listen mode                    */
+
+/*******************  Bit definition for CEC_TXDR register  *******************/
+#define  CEC_TXDR_TXD                        ((uint32_t)0x000000FF)       /*!< CEC Tx Data                        */
+
+/*******************  Bit definition for CEC_RXDR register  *******************/
+#define  CEC_TXDR_RXD                        ((uint32_t)0x000000FF)       /*!< CEC Rx Data                        */
+
+/*******************  Bit definition for CEC_ISR register  ********************/
+#define  CEC_ISR_RXBR                        ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received                   */
+#define  CEC_ISR_RXEND                       ((uint32_t)0x00000002)       /*!< CEC End Of Reception                   */
+#define  CEC_ISR_RXOVR                       ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun                         */
+#define  CEC_ISR_BRE                         ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error                */
+#define  CEC_ISR_SBPE                        ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error          */
+#define  CEC_ISR_LBPE                        ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error           */
+#define  CEC_ISR_RXACKE                      ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge             */
+#define  CEC_ISR_ARBLST                      ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost                   */
+#define  CEC_ISR_TXBR                        ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request                    */
+#define  CEC_ISR_TXEND                       ((uint32_t)0x00000200)       /*!< CEC End of Transmission                */
+#define  CEC_ISR_TXUDR                       ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun                 */
+#define  CEC_ISR_TXERR                       ((uint32_t)0x00000800)       /*!< CEC Tx-Error                           */
+#define  CEC_ISR_TXACKE                      ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge             */
+
+/*******************  Bit definition for CEC_IER register  ********************/
+#define  CEC_IER_RXBRIE                      ((uint32_t)0x00000001)       /*!< CEC Rx-Byte Received IT Enable         */
+#define  CEC_IER_RXENDIE                     ((uint32_t)0x00000002)       /*!< CEC End Of Reception IT Enable         */
+#define  CEC_IER_RXOVRIE                     ((uint32_t)0x00000004)       /*!< CEC Rx-Overrun IT Enable               */
+#define  CEC_IER_BREIEIE                     ((uint32_t)0x00000008)       /*!< CEC Rx Bit Rising Error IT Enable      */
+#define  CEC_IER_SBPEIE                      ((uint32_t)0x00000010)       /*!< CEC Rx Short Bit period Error IT Enable*/
+#define  CEC_IER_LBPEIE                      ((uint32_t)0x00000020)       /*!< CEC Rx Long Bit period Error IT Enable */
+#define  CEC_IER_RXACKEIE                    ((uint32_t)0x00000040)       /*!< CEC Rx Missing Acknowledge IT Enable   */
+#define  CEC_IER_ARBLSTIE                    ((uint32_t)0x00000080)       /*!< CEC Arbitration Lost IT Enable         */
+#define  CEC_IER_TXBRIE                      ((uint32_t)0x00000100)       /*!< CEC Tx Byte Request  IT Enable         */
+#define  CEC_IER_TXENDIE                     ((uint32_t)0x00000200)       /*!< CEC End of Transmission IT Enable      */
+#define  CEC_IER_TXUDRIE                     ((uint32_t)0x00000400)       /*!< CEC Tx-Buffer Underrun IT Enable       */
+#define  CEC_IER_TXERRIE                     ((uint32_t)0x00000800)       /*!< CEC Tx-Error IT Enable                 */
+#define  CEC_IER_TXACKEIE                    ((uint32_t)0x00001000)       /*!< CEC Tx Missing Acknowledge IT Enable   */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+/***********************  Bit definition for COMP_CSR register  ***************/
+/* COMP1 bits definition */
+#define COMP_CSR_COMP1EN               ((uint32_t)0x00000001) /*!< COMP1 enable */
+#define COMP_CSR_COMP1SW1              ((uint32_t)0x00000002) /*!< SW1 switch control */
+#define COMP_CSR_COMP1MODE             ((uint32_t)0x0000000C) /*!< COMP1 power mode */
+#define COMP_CSR_COMP1MODE_0           ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
+#define COMP_CSR_COMP1MODE_1           ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
+#define COMP_CSR_COMP1INSEL            ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
+#define COMP_CSR_COMP1INSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
+#define COMP_CSR_COMP1INSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
+#define COMP_CSR_COMP1INSEL_2          ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
+#define COMP_CSR_COMP1OUTSEL           ((uint32_t)0x00000700) /*!< COMP1 output select */
+#define COMP_CSR_COMP1OUTSEL_0         ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
+#define COMP_CSR_COMP1OUTSEL_1         ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
+#define COMP_CSR_COMP1OUTSEL_2         ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
+#define COMP_CSR_COMP1POL              ((uint32_t)0x00000800) /*!< COMP1 output polarity */
+#define COMP_CSR_COMP1HYST             ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
+#define COMP_CSR_COMP1HYST_0           ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
+#define COMP_CSR_COMP1HYST_1           ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
+#define COMP_CSR_COMP1OUT              ((uint32_t)0x00004000) /*!< COMP1 output level */
+#define COMP_CSR_COMP1LOCK             ((uint32_t)0x00008000) /*!< COMP1 lock */
+/* COMP2 bits definition */
+#define COMP_CSR_COMP2EN               ((uint32_t)0x00010000) /*!< COMP2 enable */
+#define COMP_CSR_COMP2MODE             ((uint32_t)0x000C0000) /*!< COMP2 power mode */
+#define COMP_CSR_COMP2MODE_0           ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
+#define COMP_CSR_COMP2MODE_1           ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
+#define COMP_CSR_COMP2INSEL            ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
+#define COMP_CSR_COMP2INSEL_0          ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
+#define COMP_CSR_COMP2INSEL_1          ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
+#define COMP_CSR_COMP2INSEL_2          ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
+#define COMP_CSR_WNDWEN                ((uint32_t)0x00800000) /*!< Comparators window mode enable */
+#define COMP_CSR_COMP2OUTSEL           ((uint32_t)0x07000000) /*!< COMP2 output select */
+#define COMP_CSR_COMP2OUTSEL_0         ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
+#define COMP_CSR_COMP2OUTSEL_1         ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
+#define COMP_CSR_COMP2OUTSEL_2         ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
+#define COMP_CSR_COMP2POL              ((uint32_t)0x08000000) /*!< COMP2 output polarity */
+#define COMP_CSR_COMP2HYST             ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
+#define COMP_CSR_COMP2HYST_0           ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
+#define COMP_CSR_COMP2HYST_1           ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
+#define COMP_CSR_COMP2OUT              ((uint32_t)0x40000000) /*!< COMP2 output level */
+#define COMP_CSR_COMP2LOCK             ((uint32_t)0x80000000) /*!< COMP2 lock */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define  CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
+#define  CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
+#define  CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
+#define  CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
+#define  CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
+
+/*******************  Bit definition for CRC_INIT register  *******************/
+#define  CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    Digital to Analog Converter (DAC)                       */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DAC_CR register  ********************/
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
+
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
+
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
+#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA Underrun Interrupt enable */
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001)        /*!<DAC channel1 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FF)         /*!<DAC channel1 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x00000FFF)        /*!<DAC channel1 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
+
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
+#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
+#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
+#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
+#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
+#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
+#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
+#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
+#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
+#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
+#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
+#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
+#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
+#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
+#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
+#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)        /*!< TIM3 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP       ((uint32_t)0x00000100)        /*!< TIM14 counter stopped when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+#define  DBGMCU_APB2_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000800)        /*!< TIM1 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM15_STOP       ((uint32_t)0x00010000)        /*!< TIM15 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM16_STOP       ((uint32_t)0x00020000)        /*!< TIM16 counter stopped when core is halted */
+#define  DBGMCU_APB2_FZ_DBG_TIM17_STOP       ((uint32_t)0x00040000)        /*!< TIM17 counter stopped when core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
+#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
+#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
+#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
+#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
+#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
+#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
+#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
+#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
+#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
+#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
+#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
+#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
+#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
+#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
+#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
+#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
+#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
+#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
+#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
+#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
+#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
+#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
+#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
+#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
+#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
+#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
+
+/*******************  Bit definition for DMA_CCR register  ********************/
+#define  DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
+#define  DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
+#define  DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
+#define  DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
+#define  DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
+#define  DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
+#define  DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
+#define  DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
+
+#define  DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
+#define  DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
+#define  DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
+#define  DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
+#define  DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
+
+#define  DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
+#define  DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
+#define  DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
+
+#define  DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
+
+/******************  Bit definition for DMA_CNDTR register  *******************/
+#define  DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
+
+/******************  Bit definition for DMA_CPAR register  ********************/
+#define  DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
+
+/******************  Bit definition for DMA_CMAR register  ********************/
+#define  DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
+
+/******************************************************************************/
+/*                                                                            */
+/*                 External Interrupt/Event Controller (EXTI)                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
+#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
+#define  EXTI_IMR_MR25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
+#define  EXTI_IMR_MR27                       ((uint32_t)0x08000000)        /*!< Interrupt Mask on line 27 */
+
+/******************  Bit definition for EXTI_EMR register  ********************/
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
+#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
+#define  EXTI_EMR_MR25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
+#define  EXTI_EMR_MR27                       ((uint32_t)0x08000000)        /*!< Event Mask on line 27 */
+
+/*******************  Bit definition for EXTI_RTSR register  ******************/
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
+
+/*******************  Bit definition for EXTI_FTSR register *******************/
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
+
+/******************* Bit definition for EXTI_SWIER register *******************/
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
+
+/******************  Bit definition for EXTI_PR register  *********************/
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      FLASH and Option Bytes Registers                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
+
+#define  FLASH_ACR_PRFTBE                    ((uint32_t)0x00000010)        /*!< Prefetch Buffer Enable */
+#define  FLASH_ACR_PRFTBS                    ((uint32_t)0x00000020)        /*!< Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                    ((uint32_t)0xFFFFFFFF)        /*!< FPEC Key */
+
+/*****************  Bit definition for FLASH_OPTKEYR register  ****************/
+#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option Byte Key */
+
+/******************  FLASH Keys  **********************************************/
+#define FLASH_FKEY1                          ((uint32_t)0x45670123)        /*!< Flash program erase key1 */
+#define FLASH_FKEY2                          ((uint32_t)0xCDEF89AB)        /*!< Flash program erase key2: used with FLASH_PEKEY1
+                                                                                to unlock the write access to the FPEC. */
+                                                               
+#define FLASH_OPTKEY1                        ((uint32_t)0x45670123)        /*!< Flash option key1 */
+#define FLASH_OPTKEY2                        ((uint32_t)0xCDEF89AB)        /*!< Flash option key2: used with FLASH_OPTKEY1 to
+                                                                                unlock the write access to the option byte block */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
+#define  FLASH_SR_PGERR                      ((uint32_t)0x00000004)        /*!< Programming Error */
+#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000010)        /*!< Write Protection Error */
+#define  FLASH_SR_EOP                        ((uint32_t)0x00000020)        /*!< End of operation */
+
+/*******************  Bit definition for FLASH_CR register  *******************/
+#define  FLASH_CR_PG                         ((uint32_t)0x00000001)        /*!< Programming */
+#define  FLASH_CR_PER                        ((uint32_t)0x00000002)        /*!< Page Erase */
+#define  FLASH_CR_MER                        ((uint32_t)0x00000004)        /*!< Mass Erase */
+#define  FLASH_CR_OPTPG                      ((uint32_t)0x00000010)        /*!< Option Byte Programming */
+#define  FLASH_CR_OPTER                      ((uint32_t)0x00000020)        /*!< Option Byte Erase */
+#define  FLASH_CR_STRT                       ((uint32_t)0x00000040)        /*!< Start */
+#define  FLASH_CR_LOCK                       ((uint32_t)0x00000080)        /*!< Lock */
+#define  FLASH_CR_OPTWRE                     ((uint32_t)0x00000200)        /*!< Option Bytes Write Enable */
+#define  FLASH_CR_ERRIE                      ((uint32_t)0x00000400)        /*!< Error Interrupt Enable */
+#define  FLASH_CR_EOPIE                      ((uint32_t)0x00001000)        /*!< End of operation interrupt enable */
+#define  FLASH_CR_OBL_LAUNCH                 ((uint32_t)0x00002000)        /*!< Option Bytes Loader Launch */
+
+/*******************  Bit definition for FLASH_AR register  *******************/
+#define  FLASH_AR_FAR                        ((uint32_t)0xFFFFFFFF)        /*!< Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                    ((uint32_t)0x00000001)        /*!< Option Byte Error */
+#define  FLASH_OBR_RDPRT1                    ((uint32_t)0x00000002)        /*!< Read protection Level 1 */
+#define  FLASH_OBR_RDPRT2                    ((uint32_t)0x00000004)        /*!< Read protection Level 2 */
+
+#define  FLASH_OBR_USER                      ((uint32_t)0x00003700)        /*!< User Option Bytes */
+#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00000100)        /*!< IWDG SW */
+#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00000200)        /*!< nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00000400)        /*!< nRST_STDBY */
+#define  FLASH_OBR_nBOOT1                    ((uint32_t)0x00001000)        /*!< nBOOT1 */
+#define  FLASH_OBR_VDDA_MONITOR              ((uint32_t)0x00002000)        /*!< VDDA power supply supervisor */
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_BOOT1                      FLASH_OBR_nBOOT1
+
+/* Old BOOT1 bit definition, maintained for legacy purpose */
+#define FLASH_OBR_VDDA_ANALOG                FLASH_OBR_VDDA_MONITOR
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define  FLASH_WRPR_WRP                      ((uint32_t)0x0000FFFF)        /*!< Write Protect */
+
+/*----------------------------------------------------------------------------*/
+
+/******************  Bit definition for OB_RDP register  **********************/
+#define  OB_RDP_RDP                          ((uint32_t)0x000000FF)        /*!< Read protection option byte */
+#define  OB_RDP_nRDP                         ((uint32_t)0x0000FF00)        /*!< Read protection complemented option byte */
+
+/******************  Bit definition for OB_USER register  *********************/
+#define  OB_USER_USER                        ((uint32_t)0x00FF0000)        /*!< User option byte */
+#define  OB_USER_nUSER                       ((uint32_t)0xFF000000)        /*!< User complemented option byte */
+
+/******************  Bit definition for OB_WRP0 register  *********************/
+#define  OB_WRP0_WRP0                        ((uint32_t)0x000000FF)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP0_nWRP0                       ((uint32_t)0x0000FF00)        /*!< Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for OB_WRP1 register  *********************/
+#define  OB_WRP1_WRP1                        ((uint32_t)0x00FF0000)        /*!< Flash memory write protection option bytes */
+#define  OB_WRP1_nWRP1                       ((uint32_t)0xFF000000)        /*!< Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       General Purpose IOs (GPIO)                           */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
+
+/******************  Bit definition for GPIO_OTYPER register  *****************/
+#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
+
+/****************  Bit definition for GPIO_OSPEEDR register  ******************/
+#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_PUPDR register ******************/
+#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
+
+/*******************  Bit definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_0                 ((uint32_t)0x00000001)
+#define GPIO_IDR_1                 ((uint32_t)0x00000002)
+#define GPIO_IDR_2                 ((uint32_t)0x00000004)
+#define GPIO_IDR_3                 ((uint32_t)0x00000008)
+#define GPIO_IDR_4                 ((uint32_t)0x00000010)
+#define GPIO_IDR_5                 ((uint32_t)0x00000020)
+#define GPIO_IDR_6                 ((uint32_t)0x00000040)
+#define GPIO_IDR_7                 ((uint32_t)0x00000080)
+#define GPIO_IDR_8                 ((uint32_t)0x00000100)
+#define GPIO_IDR_9                 ((uint32_t)0x00000200)
+#define GPIO_IDR_10                ((uint32_t)0x00000400)
+#define GPIO_IDR_11                ((uint32_t)0x00000800)
+#define GPIO_IDR_12                ((uint32_t)0x00001000)
+#define GPIO_IDR_13                ((uint32_t)0x00002000)
+#define GPIO_IDR_14                ((uint32_t)0x00004000)
+#define GPIO_IDR_15                ((uint32_t)0x00008000)
+
+/******************  Bit definition for GPIO_ODR register  ********************/
+#define GPIO_ODR_0                 ((uint32_t)0x00000001)
+#define GPIO_ODR_1                 ((uint32_t)0x00000002)
+#define GPIO_ODR_2                 ((uint32_t)0x00000004)
+#define GPIO_ODR_3                 ((uint32_t)0x00000008)
+#define GPIO_ODR_4                 ((uint32_t)0x00000010)
+#define GPIO_ODR_5                 ((uint32_t)0x00000020)
+#define GPIO_ODR_6                 ((uint32_t)0x00000040)
+#define GPIO_ODR_7                 ((uint32_t)0x00000080)
+#define GPIO_ODR_8                 ((uint32_t)0x00000100)
+#define GPIO_ODR_9                 ((uint32_t)0x00000200)
+#define GPIO_ODR_10                ((uint32_t)0x00000400)
+#define GPIO_ODR_11                ((uint32_t)0x00000800)
+#define GPIO_ODR_12                ((uint32_t)0x00001000)
+#define GPIO_ODR_13                ((uint32_t)0x00002000)
+#define GPIO_ODR_14                ((uint32_t)0x00004000)
+#define GPIO_ODR_15                ((uint32_t)0x00008000)
+
+/****************** Bit definition for GPIO_BSRR register  ********************/
+#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)
+
+/****************** Bit definition for GPIO_BRR register  *********************/
+#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
+#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
+#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
+#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
+#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
+#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
+#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
+#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
+#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
+#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
+#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
+#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
+#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
+#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
+#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
+#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  *******************/
+#define  I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
+#define  I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
+#define  I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
+#define  I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
+#define  I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
+#define  I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
+#define  I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
+#define  I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
+#define  I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
+#define  I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
+#define  I2C_CR1_SWRST                       ((uint32_t)0x00002000)        /*!< Software reset */
+#define  I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
+#define  I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
+#define  I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
+#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
+#define  I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
+#define  I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
+#define  I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
+#define  I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
+#define  I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
+#define  I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
+
+/******************  Bit definition for I2C_CR2 register  ********************/
+#define  I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
+#define  I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
+#define  I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
+#define  I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
+#define  I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
+#define  I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
+#define  I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
+#define  I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
+#define  I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
+#define  I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
+#define  I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
+
+/*******************  Bit definition for I2C_OAR1 register  ******************/
+#define  I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
+#define  I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
+#define  I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
+
+/*******************  Bit definition for I2C_OAR2 register  ******************/
+#define  I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
+#define  I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
+#define  I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
+
+/*******************  Bit definition for I2C_TIMINGR register *******************/
+#define  I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
+#define  I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
+#define  I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
+#define  I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
+#define  I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
+
+/******************* Bit definition for I2C_TIMEOUTR register *******************/
+#define  I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
+#define  I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
+#define  I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
+#define  I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
+#define  I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
+
+/******************  Bit definition for I2C_ISR register  *********************/
+#define  I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
+#define  I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
+#define  I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
+#define  I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
+#define  I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
+#define  I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
+#define  I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
+#define  I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
+#define  I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
+#define  I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
+#define  I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
+#define  I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
+#define  I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
+#define  I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
+#define  I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
+#define  I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
+#define  I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
+
+/******************  Bit definition for I2C_ICR register  *********************/
+#define  I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
+#define  I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
+#define  I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
+#define  I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
+#define  I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
+#define  I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
+#define  I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
+#define  I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
+#define  I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
+
+/******************  Bit definition for I2C_PECR register  *********************/
+#define  I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
+
+/******************  Bit definition for I2C_RXDR register  *********************/
+#define  I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit receive data */
+
+/******************  Bit definition for I2C_TXDR register  *********************/
+#define  I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)        /*!< 8-bit transmit data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!< PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!< Bit 0 */
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!< Bit 1 */
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!< Bit 2 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!< Watchdog prescaler value update */
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!< Watchdog counter reload value update */
+#define  IWDG_SR_WVU                         ((uint8_t)0x04)               /*!< Watchdog counter window value update */
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define  IWDG_WINR_WIN                         ((uint16_t)0x0FFF)            /*!< Watchdog counter window value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define  PWR_CR_LPSDSR                       ((uint16_t)0x0001)     /*!< Low-power deepsleep/sleep/low power run */
+#define  PWR_CR_PDDS                         ((uint16_t)0x0002)     /*!< Power Down Deepsleep */
+#define  PWR_CR_CWUF                         ((uint16_t)0x0004)     /*!< Clear Wakeup Flag */
+#define  PWR_CR_CSBF                         ((uint16_t)0x0008)     /*!< Clear Standby Flag */
+#define  PWR_CR_PVDE                         ((uint16_t)0x0010)     /*!< Power Voltage Detector Enable */
+
+#define  PWR_CR_PLS                          ((uint16_t)0x00E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CR_PLS_0                        ((uint16_t)0x0020)     /*!< Bit 0 */
+#define  PWR_CR_PLS_1                        ((uint16_t)0x0040)     /*!< Bit 1 */
+#define  PWR_CR_PLS_2                        ((uint16_t)0x0080)     /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define  PWR_CR_PLS_LEV0                     ((uint16_t)0x0000)     /*!< PVD level 0 */
+#define  PWR_CR_PLS_LEV1                     ((uint16_t)0x0020)     /*!< PVD level 1 */
+#define  PWR_CR_PLS_LEV2                     ((uint16_t)0x0040)     /*!< PVD level 2 */
+#define  PWR_CR_PLS_LEV3                     ((uint16_t)0x0060)     /*!< PVD level 3 */
+#define  PWR_CR_PLS_LEV4                     ((uint16_t)0x0080)     /*!< PVD level 4 */
+#define  PWR_CR_PLS_LEV5                     ((uint16_t)0x00A0)     /*!< PVD level 5 */
+#define  PWR_CR_PLS_LEV6                     ((uint16_t)0x00C0)     /*!< PVD level 6 */
+#define  PWR_CR_PLS_LEV7                     ((uint16_t)0x00E0)     /*!< PVD level 7 */
+
+#define  PWR_CR_DBP                          ((uint16_t)0x0100)     /*!< Disable Backup Domain write protection */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                         ((uint16_t)0x0001)     /*!< Wakeup Flag */
+#define  PWR_CSR_SBF                         ((uint16_t)0x0002)     /*!< Standby Flag */
+#define  PWR_CSR_PVDO                        ((uint16_t)0x0004)     /*!< PVD Output */
+#define  PWR_CSR_VREFINTRDYF                 ((uint16_t)0x0008)     /*!< Internal voltage reference (VREFINT) ready flag */
+
+#define  PWR_CSR_EWUP1                       ((uint16_t)0x0100)     /*!< Enable WKUP pin 1 */
+#define  PWR_CSR_EWUP2                       ((uint16_t)0x0200)     /*!< Enable WKUP pin 2 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)        /*!< Internal High Speed clock trimming */
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)        /*!< Internal High Speed clock Calibration */
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)        /*!< Clock Security System enable */
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFGR register  *******************/
+/*!< SW configuration */
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
+
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */
+
+/*!< HPRE configuration */
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
+
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
+
+/*!< PPRE configuration */
+#define  RCC_CFGR_PPRE                       ((uint32_t)0x00000700)        /*!< PRE[2:0] bits (APB prescaler) */
+#define  RCC_CFGR_PPRE_0                     ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_CFGR_PPRE_1                     ((uint32_t)0x00000200)        /*!< Bit 1 */
+#define  RCC_CFGR_PPRE_2                     ((uint32_t)0x00000400)        /*!< Bit 2 */
+
+#define  RCC_CFGR_PPRE_DIV1                  ((uint32_t)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE_DIV2                  ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE_DIV4                  ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE_DIV8                  ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
+#define  RCC_CFGR_PPRE_DIV16                 ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
+
+/*!< ADCPPRE configuration */
+#define  RCC_CFGR_ADCPRE                     ((uint32_t)0x00004000)        /*!< ADCPRE bit (ADC prescaler) */
+
+#define  RCC_CFGR_ADCPRE_DIV2                ((uint32_t)0x00000000)        /*!< PCLK divided by 2 */
+#define  RCC_CFGR_ADCPRE_DIV4                ((uint32_t)0x00004000)        /*!< PCLK divided by 4 */
+
+#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE                   ((uint32_t)0x00020000)        /*!< HSE divider for PLL entry */
+
+/*!< PLLMUL configuration */
+#define  RCC_CFGR_PLLMULL                    ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_CFGR_PLLMULL_0                  ((uint32_t)0x00040000)        /*!< Bit 0 */
+#define  RCC_CFGR_PLLMULL_1                  ((uint32_t)0x00080000)        /*!< Bit 1 */
+#define  RCC_CFGR_PLLMULL_2                  ((uint32_t)0x00100000)        /*!< Bit 2 */
+#define  RCC_CFGR_PLLMULL_3                  ((uint32_t)0x00200000)        /*!< Bit 3 */
+
+#define  RCC_CFGR_PLLSRC_HSI_Div2            ((uint32_t)0x00000000)        /*!< HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_CFGR_PLLSRC_PREDIV1             ((uint32_t)0x00010000)        /*!< PREDIV1 clock selected as PLL entry clock source */
+
+#define  RCC_CFGR_PLLXTPRE_PREDIV1           ((uint32_t)0x00000000)        /*!< PREDIV1 clock not divided for PLL entry */
+#define  RCC_CFGR_PLLXTPRE_PREDIV1_Div2      ((uint32_t)0x00020000)        /*!< PREDIV1 clock divided by 2 for PLL entry */
+
+#define  RCC_CFGR_PLLMULL2                   ((uint32_t)0x00000000)        /*!< PLL input clock*2 */
+#define  RCC_CFGR_PLLMULL3                   ((uint32_t)0x00040000)        /*!< PLL input clock*3 */
+#define  RCC_CFGR_PLLMULL4                   ((uint32_t)0x00080000)        /*!< PLL input clock*4 */
+#define  RCC_CFGR_PLLMULL5                   ((uint32_t)0x000C0000)        /*!< PLL input clock*5 */
+#define  RCC_CFGR_PLLMULL6                   ((uint32_t)0x00100000)        /*!< PLL input clock*6 */
+#define  RCC_CFGR_PLLMULL7                   ((uint32_t)0x00140000)        /*!< PLL input clock*7 */
+#define  RCC_CFGR_PLLMULL8                   ((uint32_t)0x00180000)        /*!< PLL input clock*8 */
+#define  RCC_CFGR_PLLMULL9                   ((uint32_t)0x001C0000)        /*!< PLL input clock*9 */
+#define  RCC_CFGR_PLLMULL10                  ((uint32_t)0x00200000)        /*!< PLL input clock10 */
+#define  RCC_CFGR_PLLMULL11                  ((uint32_t)0x00240000)        /*!< PLL input clock*11 */
+#define  RCC_CFGR_PLLMULL12                  ((uint32_t)0x00280000)        /*!< PLL input clock*12 */
+#define  RCC_CFGR_PLLMULL13                  ((uint32_t)0x002C0000)        /*!< PLL input clock*13 */
+#define  RCC_CFGR_PLLMULL14                  ((uint32_t)0x00300000)        /*!< PLL input clock*14 */
+#define  RCC_CFGR_PLLMULL15                  ((uint32_t)0x00340000)        /*!< PLL input clock*15 */
+#define  RCC_CFGR_PLLMULL16                  ((uint32_t)0x00380000)        /*!< PLL input clock*16 */
+
+/*!< MCO configuration */
+#define  RCC_CFGR_MCO                        ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_CFGR_MCO_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
+#define  RCC_CFGR_MCO_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
+#define  RCC_CFGR_MCO_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
+
+#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_CFGR_MCO_HSI14                  ((uint32_t)0x01000000)        /*!< HSI14 clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x02000000)        /*!< LSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x03000000)        /*!< LSE clock selected as MCO source */
+#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x04000000)        /*!< System clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x05000000)        /*!< HSI clock selected as MCO source */
+#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x06000000)        /*!< HSE clock selected as MCO source  */
+#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x07000000)        /*!< PLL clock divided by 2 selected as MCO source */
+
+/*!<******************  Bit definition for RCC_CIR register  ********************/
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
+#define  RCC_CIR_HSI14RDYF                   ((uint32_t)0x00000020)        /*!< HSI14 Ready Interrupt flag */
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
+#define  RCC_CIR_HSI14RDYIE                  ((uint32_t)0x00002000)        /*!< HSI14 Ready Interrupt Enable */
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
+#define  RCC_CIR_HSI14RDYC                   ((uint32_t)0x00200000)        /*!< HSI14 Ready Interrupt Clear */
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
+#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 clock reset */
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000800)        /*!< TIM1 clock reset */
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
+#define  RCC_APB2RSTR_TIM15RST               ((uint32_t)0x00010000)        /*!< TIM15 clock reset */
+#define  RCC_APB2RSTR_TIM16RST               ((uint32_t)0x00020000)        /*!< TIM16 clock reset */
+#define  RCC_APB2RSTR_TIM17RST               ((uint32_t)0x00040000)        /*!< TIM17 clock reset */
+#define  RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)        /*!< Timer 14 clock reset */
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
+#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
+#define  RCC_APB1RSTR_CECRST                 ((uint32_t)0x40000000)        /*!< CEC clock reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)        /*!< DMA1 clock enable */
+#define  RCC_AHBENR_SRAMEN                   ((uint32_t)0x00000004)        /*!< SRAM interface clock enable */
+#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00000010)        /*!< FLITF clock enable */
+#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00000040)        /*!< CRC clock enable */
+#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00020000)        /*!< GPIOA clock enable */
+#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00040000)        /*!< GPIOB clock enable */
+#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00080000)        /*!< GPIOC clock enable */
+#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00100000)        /*!< GPIOD clock enable */
+#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00400000)        /*!< GPIOF clock enable */
+#define  RCC_AHBENR_TSEN                     ((uint32_t)0x01000000)        /*!< TS clock enable */
+
+/*****************  Bit definition for RCC_APB2ENR register  ******************/
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)        /*!< SYSCFG clock enable */
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000800)        /*!< TIM1 clock enable */
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
+#define  RCC_APB2ENR_TIM15EN                 ((uint32_t)0x00010000)        /*!< TIM15 clock enable */
+#define  RCC_APB2ENR_TIM16EN                 ((uint32_t)0x00020000)        /*!< TIM16 clock enable */
+#define  RCC_APB2ENR_TIM17EN                 ((uint32_t)0x00040000)        /*!< TIM17 clock enable */
+#define  RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)        /*!< Timer 14 clock enable */
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
+#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
+#define  RCC_APB1ENR_CECEN                   ((uint32_t)0x40000000)        /*!< CEC clock enable */
+
+/*******************  Bit definition for RCC_BDCR register  *******************/
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)        /*!< External Low Speed oscillator enable */
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)        /*!< External Low Speed oscillator Ready */
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)        /*!< External Low Speed oscillator Bypass */
+
+#define  RCC_BDCR_LSEDRV                     ((uint32_t)0x00000018)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
+#define  RCC_BDCR_LSEDRV_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
+#define  RCC_BDCR_LSEDRV_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
+
+#define  RCC_BDCR_RTCSEL                     ((uint32_t)0x00000300)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_BDCR_RTCSEL_0                   ((uint32_t)0x00000100)        /*!< Bit 0 */
+#define  RCC_BDCR_RTCSEL_1                   ((uint32_t)0x00000200)        /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define  RCC_BDCR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
+#define  RCC_BDCR_RTCSEL_LSE                 ((uint32_t)0x00000100)        /*!< LSE oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_LSI                 ((uint32_t)0x00000200)        /*!< LSI oscillator clock used as RTC clock */
+#define  RCC_BDCR_RTCSEL_HSE                 ((uint32_t)0x00000300)        /*!< HSE oscillator clock divided by 128 used as RTC clock */
+
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)        /*!< RTC clock enable */
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)        /*!< Backup domain software reset  */
+
+/*******************  Bit definition for RCC_CSR register  ********************/  
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
+#define  RCC_CSR_V18PWRRSTF                 ((uint32_t)0x00800000)        /*!< V1.8 power domain reset flag */
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)        /*!< Remove reset flag */
+#define  RCC_CSR_OBL                         ((uint32_t)0x02000000)        /*!< OBL reset flag */
+#define  RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
+#define  RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
+
+/*******************  Bit definition for RCC_AHBRSTR register  ****************/
+#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00020000)         /*!< GPIOA clock reset */
+#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00040000)         /*!< GPIOB clock reset */
+#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00080000)         /*!< GPIOC clock reset */
+#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00010000)         /*!< GPIOD clock reset */
+#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00040000)         /*!< GPIOF clock reset */
+#define  RCC_AHBRSTR_TSRST                   ((uint32_t)0x00100000)         /*!< TS clock reset */
+
+/*******************  Bit definition for RCC_CFGR2 register  ******************/
+/*!< PREDIV1 configuration */
+#define  RCC_CFGR2_PREDIV1                   ((uint32_t)0x0000000F)        /*!< PREDIV1[3:0] bits */
+#define  RCC_CFGR2_PREDIV1_0                 ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR2_PREDIV1_1                 ((uint32_t)0x00000002)        /*!< Bit 1 */
+#define  RCC_CFGR2_PREDIV1_2                 ((uint32_t)0x00000004)        /*!< Bit 2 */
+#define  RCC_CFGR2_PREDIV1_3                 ((uint32_t)0x00000008)        /*!< Bit 3 */
+
+#define  RCC_CFGR2_PREDIV1_DIV1              ((uint32_t)0x00000000)        /*!< PREDIV1 input clock not divided */
+#define  RCC_CFGR2_PREDIV1_DIV2              ((uint32_t)0x00000001)        /*!< PREDIV1 input clock divided by 2 */
+#define  RCC_CFGR2_PREDIV1_DIV3              ((uint32_t)0x00000002)        /*!< PREDIV1 input clock divided by 3 */
+#define  RCC_CFGR2_PREDIV1_DIV4              ((uint32_t)0x00000003)        /*!< PREDIV1 input clock divided by 4 */
+#define  RCC_CFGR2_PREDIV1_DIV5              ((uint32_t)0x00000004)        /*!< PREDIV1 input clock divided by 5 */
+#define  RCC_CFGR2_PREDIV1_DIV6              ((uint32_t)0x00000005)        /*!< PREDIV1 input clock divided by 6 */
+#define  RCC_CFGR2_PREDIV1_DIV7              ((uint32_t)0x00000006)        /*!< PREDIV1 input clock divided by 7 */
+#define  RCC_CFGR2_PREDIV1_DIV8              ((uint32_t)0x00000007)        /*!< PREDIV1 input clock divided by 8 */
+#define  RCC_CFGR2_PREDIV1_DIV9              ((uint32_t)0x00000008)        /*!< PREDIV1 input clock divided by 9 */
+#define  RCC_CFGR2_PREDIV1_DIV10             ((uint32_t)0x00000009)        /*!< PREDIV1 input clock divided by 10 */
+#define  RCC_CFGR2_PREDIV1_DIV11             ((uint32_t)0x0000000A)        /*!< PREDIV1 input clock divided by 11 */
+#define  RCC_CFGR2_PREDIV1_DIV12             ((uint32_t)0x0000000B)        /*!< PREDIV1 input clock divided by 12 */
+#define  RCC_CFGR2_PREDIV1_DIV13             ((uint32_t)0x0000000C)        /*!< PREDIV1 input clock divided by 13 */
+#define  RCC_CFGR2_PREDIV1_DIV14             ((uint32_t)0x0000000D)        /*!< PREDIV1 input clock divided by 14 */
+#define  RCC_CFGR2_PREDIV1_DIV15             ((uint32_t)0x0000000E)        /*!< PREDIV1 input clock divided by 15 */
+#define  RCC_CFGR2_PREDIV1_DIV16             ((uint32_t)0x0000000F)        /*!< PREDIV1 input clock divided by 16 */
+
+/*******************  Bit definition for RCC_CFGR3 register  ******************/
+/*!< USART1 Clock source selection */
+#define  RCC_CFGR3_USART1SW                  ((uint32_t)0x00000003)        /*!< USART1SW[1:0] bits */
+#define  RCC_CFGR3_USART1SW_0                ((uint32_t)0x00000001)        /*!< Bit 0 */
+#define  RCC_CFGR3_USART1SW_1                ((uint32_t)0x00000002)        /*!< Bit 1 */
+/*!< I2C1 Clock source selection */
+#define  RCC_CFGR3_I2C1SW                    ((uint32_t)0x00000010)        /*!< I2C1SW bits */ 
+#define  RCC_CFGR3_CECSW                     ((uint32_t)0x00000040)        /*!< CECSW bits */ 
+#define  RCC_CFGR3_ADCSW                     ((uint32_t)0x00000100)        /*!< ADCSW bits */ 
+
+/*******************  Bit definition for RCC_CR2 register  ********************/
+#define  RCC_CR2_HSI14ON                     ((uint32_t)0x00000001)        /*!< Internal High Speed 14MHz clock enable */
+#define  RCC_CR2_HSI14RDY                    ((uint32_t)0x00000002)        /*!< Internal High Speed 14MHz clock ready flag */
+#define  RCC_CR2_HSI14DIS                    ((uint32_t)0x00000004)        /*!< Internal High Speed 14MHz clock disable */
+#define  RCC_CR2_HSI14TRIM                   ((uint32_t)0x000000F8)        /*!< Internal High Speed 14MHz clock trimming */
+#define  RCC_CR2_HSI14CAL                    ((uint32_t)0x0000FF00)        /*!< Internal High Speed 14MHz clock Calibration */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM                            ((uint32_t)0x00400000)        /*!<  */
+#define RTC_TR_HT                            ((uint32_t)0x00300000)        /*!<  */
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)        /*!<  */
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)        /*!<  */
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)        /*!<  */
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)        /*!<  */
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)        /*!<  */
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)        /*!<  */
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)        /*!<  */
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)        /*!<  */
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)        /*!<  */
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)        /*!<  */
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)        /*!<  */
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)        /*!<  */
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)        /*!<  */
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)        /*!<  */
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)        /*!<  */
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)        /*!<  */
+#define RTC_TR_ST                            ((uint32_t)0x00000070)        /*!<  */
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)        /*!<  */
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)        /*!<  */
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)        /*!<  */
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)        /*!<  */
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)        /*!<  */
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)        /*!<  */
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)        /*!<  */
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)        /*!<  */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)        /*!<  */
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)        /*!<  */
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)        /*!<  */
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)        /*!<  */
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)        /*!<  */
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)        /*!<  */
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)        /*!<  */
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)        /*!<  */
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)        /*!<  */
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)        /*!<  */
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)        /*!<  */
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)        /*!<  */
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)        /*!<  */
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)        /*!<  */
+#define RTC_DR_MT                            ((uint32_t)0x00001000)        /*!<  */
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)        /*!<  */
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)        /*!<  */
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)        /*!<  */
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)        /*!<  */
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)        /*!<  */
+#define RTC_DR_DT                            ((uint32_t)0x00000030)        /*!<  */
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)        /*!<  */
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)        /*!<  */
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)        /*!<  */
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)        /*!<  */
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)        /*!<  */
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)        /*!<  */
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)        /*!<  */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE                           ((uint32_t)0x00800000)        /*!<  */
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)        /*!<  */
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)        /*!<  */
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)        /*!<  */
+#define RTC_CR_POL                           ((uint32_t)0x00100000)        /*!<  */
+#define RTC_CR_CALSEL                        ((uint32_t)0x00080000)        /*!<  */
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)        /*!<  */
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)        /*!<  */
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)        /*!<  */
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)        /*!<  */
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)        /*!<  */
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)        /*!<  */
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)        /*!<  */
+#define RTC_CR_DCE                           ((uint32_t)0x00000080)        /*!<  */
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)        /*!<  */
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)        /*!<  */
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)        /*!<  */
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)        /*!<  */
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)        /*!<  */
+#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)        /*!<  */
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)        /*!<  */
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)        /*!<  */
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)        /*!<  */
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)        /*!<  */
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)        /*!<  */
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)        /*!<  */
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)        /*!<  */
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)        /*!<  */
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)        /*!<  */
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)        /*!<  */
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)        /*!<  */
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)        /*!<  */
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)        /*!<  */
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)        /*!<  */
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)        /*!<  */
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)        /*!<  */
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)        /*!<  */
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)        /*!<  */
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)        /*!<  */
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)        /*!<  */
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)        /*!<  */
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)        /*!<  */
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)        /*!<  */
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)        /*!<  */
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)        /*!<  */
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)        /*!<  */
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)        /*!<  */
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)        /*!<  */
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)        /*!<  */
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)        /*!<  */
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)        /*!<  */
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)        /*!<  */
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)        /*!<  */
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)        /*!<  */
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)        /*!<  */
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)        /*!<  */
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)        /*!<  */
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)        /*!<  */
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)        /*!<  */
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)        /*!<  */
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)        /*!<  */
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)        /*!<  */
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)        /*!<  */
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)        /*!<  */
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)        /*!<  */
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)        /*!<  */
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)        /*!<  */
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)        /*!<  */
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)        /*!<  */
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)        /*!<  */
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)        /*!<  */
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)        /*!<  */
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)        /*!<  */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)        /*!<  */
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)        /*!<  */
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)        /*!<  */
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)        /*!<  */
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)        /*!<  */
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)        /*!<  */
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)        /*!<  */
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)        /*!<  */
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)        /*!<  */
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)        /*!<  */
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)        /*!<  */
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)        /*!<  */
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)        /*!<  */
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)        /*!<  */
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)        /*!<  */
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)        /*!<  */
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)        /*!<  */
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)        /*!<  */
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)        /*!<  */
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)        /*!<  */
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)        /*!<  */
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)        /*!<  */
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)        /*!<  */
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)        /*!<  */
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)        /*!<  */
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)        /*!<  */
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)        /*!<  */
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)        /*!<  */
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)        /*!<  */
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)        /*!<  */
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)        /*!<  */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)        /*!<  */
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)        /*!<  */
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)        /*!<  */
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)        /*!<  */
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)        /*!<  */
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)        /*!<  */
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)        /*!<  */
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)        /*!<  */
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)        /*!<  */
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)        /*!<  */
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)        /*!<  */
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)        /*!<  */
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)        /*!<  */
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)        /*!<  */
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)        /*!<  */
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)        /*!<  */
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)        /*!<  */
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)        /*!<  */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CAL_CALP                         ((uint32_t)0x00008000)        /*!<  */
+#define RTC_CAL_CALW8                        ((uint32_t)0x00004000)        /*!<  */
+#define RTC_CAL_CALW16                       ((uint32_t)0x00002000)        /*!<  */
+#define RTC_CAL_CALM                         ((uint32_t)0x000001FF)        /*!<  */
+#define RTC_CAL_CALM_0                       ((uint32_t)0x00000001)        /*!<  */
+#define RTC_CAL_CALM_1                       ((uint32_t)0x00000002)        /*!<  */
+#define RTC_CAL_CALM_2                       ((uint32_t)0x00000004)        /*!<  */
+#define RTC_CAL_CALM_3                       ((uint32_t)0x00000008)        /*!<  */
+#define RTC_CAL_CALM_4                       ((uint32_t)0x00000010)        /*!<  */
+#define RTC_CAL_CALM_5                       ((uint32_t)0x00000020)        /*!<  */
+#define RTC_CAL_CALM_6                       ((uint32_t)0x00000040)        /*!<  */
+#define RTC_CAL_CALM_7                       ((uint32_t)0x00000080)        /*!<  */
+#define RTC_CAL_CALM_8                       ((uint32_t)0x00000100)        /*!<  */
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)        /*!<  */
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)        /*!<  */
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)        /*!<  */
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)        /*!<  */
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)        /*!<  */
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)        /*!<  */
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)        /*!<  */
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)        /*!<  */
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)        /*!<  */
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)        /*!<  */
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)        /*!<  */
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)        /*!<  */
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)        /*!<  */
+#define RTC_TAFCR_TAMP3EDGE                  ((uint32_t)0x00000040)        /*!<  */
+#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)        /*!<  */
+#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)        /*!<  */
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)        /*!<  */
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)        /*!<  */
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)        /*!<  */
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)        /*!<  */
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)        /*!<  */
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)        /*!<  */
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)        /*!<  */
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)        /*!<  */
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)        /*!<  */
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)        /*!<  */
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface (SPI)                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!< Clock Phase */
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!< Clock Polarity */
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!< Master Selection */
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!< BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!< Bit 0 */
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!< Bit 1 */
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!< Bit 2 */
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!< SPI Enable */
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!< Frame Format */
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!< Internal slave select */
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!< Software slave management */
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!< Receive only */
+#define  SPI_CR1_CRCL                        ((uint16_t)0x0800)            /*!< CRC Length */
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!< Transmit CRC next */
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!< Hardware CRC calculation enable */
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!< Output enable in bidirectional mode */
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define  SPI_CR2_RXDMAEN                     ((uint16_t)0x0001)            /*!< Rx Buffer DMA Enable */
+#define  SPI_CR2_TXDMAEN                     ((uint16_t)0x0002)            /*!< Tx Buffer DMA Enable */
+#define  SPI_CR2_SSOE                        ((uint16_t)0x0004)            /*!< SS Output Enable */
+#define  SPI_CR2_NSSP                        ((uint16_t)0x0008)            /*!< NSS pulse management Enable */
+#define  SPI_CR2_FRF                         ((uint16_t)0x0010)            /*!< Frame Format Enable */
+#define  SPI_CR2_ERRIE                       ((uint16_t)0x0020)            /*!< Error Interrupt Enable */
+#define  SPI_CR2_RXNEIE                      ((uint16_t)0x0040)            /*!< RX buffer Not Empty Interrupt Enable */
+#define  SPI_CR2_TXEIE                       ((uint16_t)0x0080)            /*!< Tx buffer Empty Interrupt Enable */
+#define  SPI_CR2_DS                          ((uint16_t)0x0F00)            /*!< DS[3:0] Data Size */
+#define  SPI_CR2_DS_0                        ((uint16_t)0x0100)            /*!< Bit 0 */
+#define  SPI_CR2_DS_1                        ((uint16_t)0x0200)            /*!< Bit 1 */
+#define  SPI_CR2_DS_2                        ((uint16_t)0x0400)            /*!< Bit 2 */
+#define  SPI_CR2_DS_3                        ((uint16_t)0x0800)            /*!< Bit 3 */
+#define  SPI_CR2_FRXTH                       ((uint16_t)0x1000)            /*!< FIFO reception Threshold */
+#define  SPI_CR2_LDMARX                      ((uint16_t)0x2000)            /*!< Last DMA transfer for reception */
+#define  SPI_CR2_LDMATX                      ((uint16_t)0x4000)            /*!< Last DMA transfer for transmission */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define  SPI_SR_RXNE                         ((uint16_t)0x0001)            /*!< Receive buffer Not Empty */
+#define  SPI_SR_TXE                          ((uint16_t)0x0002)            /*!< Transmit buffer Empty */
+#define  SPI_SR_CHSIDE                       ((uint16_t)0x0004)            /*!< Channel side */
+#define  SPI_SR_UDR                          ((uint16_t)0x0008)            /*!< Underrun flag */
+#define  SPI_SR_CRCERR                       ((uint16_t)0x0010)            /*!< CRC Error flag */
+#define  SPI_SR_MODF                         ((uint16_t)0x0020)            /*!< Mode fault */
+#define  SPI_SR_OVR                          ((uint16_t)0x0040)            /*!< Overrun flag */
+#define  SPI_SR_BSY                          ((uint16_t)0x0080)            /*!< Busy flag */
+#define  SPI_SR_FRE                          ((uint16_t)0x0100)            /*!< TI frame format error */
+#define  SPI_SR_FRLVL                        ((uint16_t)0x0600)            /*!< FIFO Reception Level */
+#define  SPI_SR_FRLVL_0                      ((uint16_t)0x0200)            /*!< Bit 0 */
+#define  SPI_SR_FRLVL_1                      ((uint16_t)0x0400)            /*!< Bit 1 */
+#define  SPI_SR_FTLVL                        ((uint16_t)0x1800)            /*!< FIFO Transmission Level */
+#define  SPI_SR_FTLVL_0                      ((uint16_t)0x0800)            /*!< Bit 0 */
+#define  SPI_SR_FTLVL_1                      ((uint16_t)0x1000)            /*!< Bit 1 */  
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!< Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity */
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization */
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
+#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
+#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
+#define SYSCFG_CFGR1_ADC_DMA_RMP            ((uint32_t)0x00000100) /*!< ADC DMA remap */
+#define SYSCFG_CFGR1_USART1TX_DMA_RMP       ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
+#define SYSCFG_CFGR1_USART1RX_DMA_RMP       ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
+#define SYSCFG_CFGR1_TIM16_DMA_RMP          ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
+#define SYSCFG_CFGR1_TIM17_DMA_RMP          ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
+#define SYSCFG_CFGR1_I2C_FMP_PB6            ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB7            ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB8            ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
+#define SYSCFG_CFGR1_I2C_FMP_PB9            ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/** 
+  * @brief  EXTI0 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0003) /*!< PF[0] pin */
+
+/** 
+  * @brief  EXTI1 configuration  
+  */ 
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0030) /*!< PF[1] pin */
+
+/** 
+  * @brief  EXTI2 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!< PD[2] pin */
+
+/** 
+  * @brief  EXTI3 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!< PC[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/** 
+  * @brief  EXTI4 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0003) /*!< PF[4] pin */
+
+/** 
+  * @brief  EXTI5 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0030) /*!< PF[5] pin */
+
+/** 
+  * @brief  EXTI6 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0300) /*!< PF[6] pin */
+
+/** 
+  * @brief  EXTI7 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x3000) /*!< PF[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/** 
+  * @brief  EXTI8 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!< PC[8] pin */
+
+/** 
+  * @brief  EXTI9 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!< PC[9] pin */
+
+/** 
+  * @brief  EXTI10 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!< PC[10] pin */
+
+/** 
+  * @brief  EXTI11 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!< PC[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/** 
+  * @brief  EXTI12 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!< PC[12] pin */
+
+/** 
+  * @brief  EXTI13 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!< PC[13] pin */
+
+/** 
+  * @brief  EXTI14 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!< PC[14] pin */
+
+/** 
+  * @brief  EXTI15 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!< PC[15] pin */
+
+/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
+#define SYSCFG_CFGR2_LOCKUP_LOCK               ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
+#define SYSCFG_CFGR2_SRAM_PARITY_LOCK          ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_PVD_LOCK                  ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
+#define SYSCFG_CFGR2_SRAM_PE                   ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable */
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable */
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode */
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction */
+
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */
+
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable */
+
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control */
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection */
+
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output) */
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output) */
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output) */
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+
+#define  TIM_SMCR_OCCS                       ((uint16_t)0x0008)            /*!< OCREF clear selection */
+
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection) */
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode */
+
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */
+
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */
+
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable */
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable */
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable */
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable */
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable */
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable */
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable */
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable */
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable */
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag */
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag */
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag */
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag */
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag */
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag */
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag */
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag */
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation */
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation */
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation */
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation */
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation */
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation */
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable */
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable */
+
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable */
+
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable */
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable */
+
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable */
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable */
+
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */
+
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable */
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */
+
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */
+
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */
+
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable */
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity */
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable */
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable */
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity */
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable */
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable */
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity */
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable */
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable */
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity */
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */
+
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */
+
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode */
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable */
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity */
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable */
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */
+
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM14_OR_TI1_RMP                       ((uint16_t)0x0003)            /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
+#define TIM14_OR_TI1_RMP_0                     ((uint16_t)0x0001)            /*!<Bit 0 */
+#define TIM14_OR_TI1_RMP_1                     ((uint16_t)0x0002)            /*!<Bit 1 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for USART_CR1 register  *******************/
+#define  USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
+#define  USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
+#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
+#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
+#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
+#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
+#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
+#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
+#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
+#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
+#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
+#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
+#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
+#define  USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
+#define  USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
+#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
+#define  USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
+#define  USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
+#define  USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
+#define  USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
+#define  USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
+#define  USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
+#define  USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
+#define  USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
+#define  USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
+#define  USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
+#define  USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
+#define  USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define  USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
+#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
+#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
+#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
+#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
+#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
+#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
+#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
+#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
+#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
+#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
+#define  USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
+#define  USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
+#define  USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
+#define  USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
+#define  USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
+#define  USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
+#define  USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
+#define  USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
+#define  USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
+#define  USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
+#define  USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
+#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
+#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
+#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
+#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
+#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
+#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
+#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
+#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
+#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
+#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
+#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
+#define  USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
+#define  USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
+#define  USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
+#define  USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
+#define  USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
+#define  USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
+#define  USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
+#define  USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
+#define  USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
+#define  USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
+#define  USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
+#define  USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_FRACTION              ((uint16_t)0x000F)                /*!< Fraction of USARTDIV */
+#define  USART_BRR_DIV_MANTISSA              ((uint16_t)0xFFF0)                /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)                /*!< PSC[7:0] bits (Prescaler value) */
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)                /*!< GT[7:0] bits (Guard time value) */
+
+
+/*******************  Bit definition for USART_RTOR register  *****************/
+#define  USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
+#define  USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
+
+/*******************  Bit definition for USART_RQR register  ******************/
+#define  USART_RQR_ABRRQ                    ((uint16_t)0x0001)                /*!< Auto-Baud Rate Request */
+#define  USART_RQR_SBKRQ                    ((uint16_t)0x0002)                /*!< Send Break Request */
+#define  USART_RQR_MMRQ                     ((uint16_t)0x0004)                /*!< Mute Mode Request */
+#define  USART_RQR_RXFRQ                    ((uint16_t)0x0008)                /*!< Receive Data flush Request */
+#define  USART_RQR_TXFRQ                    ((uint16_t)0x0010)                /*!< Transmit data flush Request */
+
+/*******************  Bit definition for USART_ISR register  ******************/
+#define  USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
+#define  USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
+#define  USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
+#define  USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
+#define  USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
+#define  USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
+#define  USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
+#define  USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
+#define  USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
+#define  USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
+#define  USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
+#define  USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
+#define  USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
+#define  USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
+#define  USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
+#define  USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
+#define  USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
+#define  USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
+#define  USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
+#define  USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
+#define  USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
+#define  USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
+
+/*******************  Bit definition for USART_ICR register  ******************/
+#define  USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
+#define  USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
+#define  USART_ICR_NCF                      ((uint32_t)0x00000004)             /*!< Noise detected Clear Flag */
+#define  USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
+#define  USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
+#define  USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
+#define  USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
+#define  USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
+#define  USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
+#define  USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
+#define  USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
+#define  USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
+
+/*******************  Bit definition for USART_RDR register  ******************/
+#define  USART_RDR_RDR                       ((uint16_t)0x01FF)                /*!< RDR[8:0] bits (Receive Data value) */
+
+/*******************  Bit definition for USART_TDR register  ******************/
+#define  USART_TDR_TDR                       ((uint16_t)0x01FF)                /*!< TDR[8:0] bits (Transmit Data value) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!< Bit 0 */
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!< Bit 1 */
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!< Bit 2 */
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!< Bit 3 */
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!< Bit 4 */
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!< Bit 5 */
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!< Bit 6 */
+
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!< W[6:0] bits (7-bit window value) */
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!< Bit 0 */
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!< Bit 1 */
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!< Bit 2 */
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!< Bit 3 */
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!< Bit 4 */
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!< Bit 5 */
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!< Bit 6 */
+
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!< WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!< Bit 0 */
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!< Bit 1 */
+
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!< Early Wakeup Interrupt Flag */
+
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */ 
+
+#ifdef USE_STDPERIPH_DRIVER
+  #include "stm32f0xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F0XX_H */
+
+/**
+  * @}
+  */
+
+  /**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-- 
cgit v1.2.3


From b0c0f93b8f60d3cf5225987d04c4ef84f8f72cee Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 16 May 2012 17:04:28 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4201
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.c | 285 +++++++++++++
 os/hal/platforms/STM32F0xx/hal_lld.h | 788 +++++++++++++++++++++++++++++++++++
 2 files changed, 1073 insertions(+)
 create mode 100644 os/hal/platforms/STM32F0xx/hal_lld.c
 create mode 100644 os/hal/platforms/STM32F0xx/hal_lld.h

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
new file mode 100644
index 000000000..806ec3ea3
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -0,0 +1,285 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F0xx/hal_lld.c
+ * @brief   STM32F0xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the backup domain.
+ * @note    WARNING! Changing clock source impossible without resetting
+ *          of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+  /* Backup domain access enabled and left open.*/
+  PWR->CR |= PWR_CR_DBP;
+
+  /* Reset BKP domain if different clock source selected.*/
+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
+    /* Backup domain reset.*/
+    RCC->BDCR = RCC_BDCR_BDRST;
+    RCC->BDCR = 0;
+  }
+
+  /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+  RCC->BDCR |= RCC_BDCR_LSEON;
+  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;                                     /* Waits until LSE is stable.   */
+#endif
+
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+  /* If the backup domain hasn't been initialized yet then proceed with
+     initialization.*/
+  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+    /* Selects clock source.*/
+    RCC->BDCR |= STM32_RTCSEL;
+
+    /* RTC clock enabled.*/
+    RCC->BDCR |= RCC_BDCR_RTCEN;
+  }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+  /* Reset of all peripherals.*/
+  rccResetAPB1(0xFFFFFFFF);
+  rccResetAPB2(0xFFFFFFFF);
+
+  /* SysTick initialization using the system clock.*/
+  SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
+  SysTick->VAL = 0;
+  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+                  SysTick_CTRL_ENABLE_Msk |
+                  SysTick_CTRL_TICKINT_Msk;
+
+  /* DWT cycle counter enable.*/
+  SCS_DEMCR |= SCS_DEMCR_TRCENA;
+  DWT_CTRL  |= DWT_CTRL_CYCCNTENA;
+
+  /* PWR and BD clocks enabled.*/
+  rccEnablePWRInterface(FALSE);
+  rccEnableBKPInterface(FALSE);
+
+  /* Initializes the backup domain.*/
+  hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+  dmaInit();
+#endif
+
+  /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+}
+
+/**
+ * @brief   STM32 clocks and PLL initialization.
+ * @note    All the involved constants come from the file @p board.h.
+ * @note    This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+#if defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) ||                    \
+    defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) ||                    \
+    defined(STM32F10X_HD) || defined(STM32F10X_XL) ||                       \
+    defined(__DOXYGEN__)
+/*
+ * Clocks initialization for all sub-families except CL.
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+  /* HSI setup, it enforces the reset situation in order to handle possible
+     problems with JTAG probes and re-initializations.*/
+  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
+  while (!(RCC->CR & RCC_CR_HSIRDY))
+    ;                                       /* Wait until HSI is stable.    */
+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
+  RCC->CFGR = 0;                            /* CFGR reset value.            */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+    ;                                       /* Waits until HSI is selected. */
+
+#if STM32_HSE_ENABLED
+  /* HSE activation.*/
+  RCC->CR |= RCC_CR_HSEON;
+  while (!(RCC->CR & RCC_CR_HSERDY))
+    ;                                       /* Waits until HSE is stable.   */
+#endif
+
+#if STM32_LSI_ENABLED
+  /* LSI activation.*/
+  RCC->CSR |= RCC_CSR_LSION;
+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+    ;                                       /* Waits until LSI is stable.   */
+#endif
+
+#if STM32_ACTIVATE_PLL
+  /* PLL activation.*/
+  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
+  RCC->CR   |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;                                       /* Waits until PLL is stable.   */
+#endif
+
+  /* Clock settings.*/
+#if STM32_HAS_USB
+  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE |
+              STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2  | STM32_PPRE1    |
+              STM32_HPRE;
+#else
+  RCC->CFGR = STM32_MCOSEL |                STM32_PLLMUL | STM32_PLLXTPRE |
+              STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2  | STM32_PPRE1    |
+              STM32_HPRE;
+#endif
+
+  /* Flash setup and final clock selection.   */
+  FLASH->ACR = STM32_FLASHBITS;
+
+  /* Switching to the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+  /* Switches clock source.*/
+  RCC->CFGR |= STM32_SW;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;                                       /* Waits selection complete.    */
+#endif
+#endif /* !STM32_NO_INIT */
+}
+
+#elif defined(STM32F10X_CL)
+/*
+ * Clocks initialization for the CL sub-family.
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+  /* HSI setup.*/
+  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
+  while (!(RCC->CR & RCC_CR_HSIRDY))
+    ;                                       /* Wait until HSI is stable.    */
+  RCC->CFGR = 0;
+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+    ;                                       /* Wait until HSI is the source.*/
+
+#if STM32_HSE_ENABLED
+#if defined(STM32_HSE_BYPASS)
+  /* HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEBYP;
+#endif
+  /* HSE activation.*/
+  RCC->CR |= RCC_CR_HSEON;
+  while (!(RCC->CR & RCC_CR_HSERDY))
+    ;                                       /* Waits until HSE is stable.   */
+#endif
+
+#if STM32_LSI_ENABLED
+  /* LSI activation.*/
+  RCC->CSR |= RCC_CSR_LSION;
+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+    ;                                       /* Waits until LSI is stable.   */
+#endif
+
+  /* Settings of various dividers and multipliers in CFGR2.*/
+  RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 |
+               STM32_PREDIV1 | STM32_PREDIV1SRC;
+
+  /* PLL2 setup, if activated.*/
+#if STM32_ACTIVATE_PLL2
+  RCC->CR |= RCC_CR_PLL2ON;
+  while (!(RCC->CR & RCC_CR_PLL2RDY))
+    ;                                        /* Waits until PLL2 is stable. */
+#endif
+
+  /* PLL3 setup, if activated.*/
+#if STM32_ACTIVATE_PLL3
+  RCC->CR |= RCC_CR_PLL3ON;
+  while (!(RCC->CR & RCC_CR_PLL3RDY))
+    ;                                        /* Waits until PLL3 is stable. */
+#endif
+
+  /* PLL1 setup, if activated.*/
+#if STM32_ACTIVATE_PLL1
+  RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
+  RCC->CR   |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;                           /* Waits until PLL1 is stable.              */
+#endif
+
+  /* Clock settings.*/
+#if STM32_HAS_OTG1
+  RCC->CFGR = STM32_MCOSEL | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC |
+              STM32_ADCPRE | STM32_PPRE2    | STM32_PPRE1  | STM32_HPRE;
+#else
+  RCC->CFGR = STM32_MCO    |                  STM32_PLLMUL | STM32_PLLSRC |
+              STM32_ADCPRE | STM32_PPRE2    | STM32_PPRE1  | STM32_HPRE;
+#endif
+
+  /* Flash setup and final clock selection.   */
+  FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock.    */
+
+  /* Switching to the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+  RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;
+#endif
+#endif /* !STM32_NO_INIT */
+}
+#else
+void stm32_clock_init(void) {}
+#endif
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
new file mode 100644
index 000000000..1689c24e2
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -0,0 +1,788 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F0xx/hal_lld.h
+ * @brief   STM32F0xx HAL subsystem low level driver header.
+ * @pre     This module requires the following macros to be defined in the
+ *          @p board.h file:
+ *          - STM32_LSECLK.
+ *          - STM32_HSECLK.
+ *          - STM32_HSE_BYPASS (optionally).
+ *          .
+ *          One of the following macros must also be defined:
+ *          - STM32F0XX for Entry Level devices.
+ *          .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "stm32.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name    Platform identification
+ * @{
+ */
+#define PLATFORM_NAME           "STM32F0 Entry Level"
+/** @} */
+
+/**
+ * @name    Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief   Maximum system clock frequency.
+ */
+#define STM32_SYSCLK_MAX        48000000
+
+/**
+ * @brief   Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX        32000000
+
+/**
+ * @brief   Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN        1000000
+
+/**
+ * @brief   Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX        1000000
+
+/**
+ * @brief   Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN        32768
+
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX         25000000
+
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN         1000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX        48000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN        16000000
+
+/**
+ * @brief   Maximum APB clock frequency.
+ */
+#define STM32_PCLK_MAX          48000000
+
+/**
+ * @brief   Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX        14000000
+/** @} */
+
+/**
+ * @name    Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK            8000000     /**< High speed internal clock. */
+#define STM32_HSI14CLK          14000000    /**< 14MHz speed internal clock.*/
+#define STM32_LSICLK            40000       /**< Low speed internal clock.  */
+/** @} */
+
+/**
+ * @name    PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
+#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
+#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
+#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
+#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
+#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
+#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
+#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
+#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
+/** @} */
+
+/**
+ * @name    RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
+#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
+#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
+
+#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
+#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
+#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
+#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
+#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
+#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
+#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
+#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
+#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
+
+#define STM32_PPRE_DIV1         (0 << 8)    /**< HCLK divided by 1.         */
+#define STM32_PPRE_DIV2         (4 << 8)    /**< HCLK divided by 2.         */
+#define STM32_PPRE_DIV4         (5 << 8)    /**< HCLK divided by 4.         */
+#define STM32_PPRE_DIV8         (6 << 8)    /**< HCLK divided by 8.         */
+#define STM32_PPRE_DIV16        (7 << 8)    /**< HCLK divided by 16.        */
+
+#define STM32_ADCPRE_DIV2       (0 << 14)   /**< PCLK divided by 2.         */
+#define STM32_ADCPRE_DIV4       (1 << 14)   /**< PCLK divided by 4.         */
+
+#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
+#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is HSE.   */
+
+#define STM32_PLLXTPRE_DIV1     (0 << 17)   /**< HSE divided by 1.          */
+#define STM32_PLLXTPRE_DIV2     (1 << 17)   /**< HSE divided by 2.          */
+
+#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
+#define STM32_MCOSEL_HSI14      (3 << 24)   /**< HSI14 clock on MCO pin.    */
+#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
+#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
+#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
+#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
+/** @} */
+
+/**
+ * @name    RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
+#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
+#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
+#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
+#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 32 used as
+                                                 RTC clock.                 */
+/** @} */
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @name    STM32F0xx capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1          TRUE
+#define STM32_HAS_ADC2          FALSE
+#define STM32_HAS_ADC3          FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1          FALSE
+#define STM32_HAS_CAN2          FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC           TRUE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA      FALSE
+#define STM32_HAS_DMA1          TRUE
+#define STM32_HAS_DMA2          FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH           FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 28
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA         TRUE
+#define STM32_HAS_GPIOB         TRUE
+#define STM32_HAS_GPIOC         TRUE
+#define STM32_HAS_GPIOD         TRUE
+#define STM32_HAS_GPIOE         FALSE
+#define STM32_HAS_GPIOF         TRUE
+#define STM32_HAS_GPIOG         FALSE
+#define STM32_HAS_GPIOH         FALSE
+#define STM32_HAS_GPIOI         FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1          TRUE
+#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C1_RX_DMA_CHN   0x00000000
+#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C1_TX_DMA_CHN   0x00000000
+
+#define STM32_HAS_I2C2          TRUE
+#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C2_RX_DMA_CHN   0x00000000
+#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C2_TX_DMA_CHN   0x00000000
+
+#define STM32_HAS_I2C3          FALSE
+#define STM32_I2C3_RX_DMA_MSK   0
+#define STM32_I2C3_RX_DMA_CHN   0x00000000
+#define STM32_I2C3_TX_DMA_MSK   0
+#define STM32_I2C3_TX_DMA_CHN   0x00000000
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC           TRUE
+#define STM32_RTC_HAS_SUBSECONDS FALSE
+#define STM32_RTC_IS_CALENDAR   TRUE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO          FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1          TRUE
+#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_SPI1_RX_DMA_CHN   0x00000000
+#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI1_TX_DMA_CHN   0x00000000
+
+#define STM32_HAS_SPI2          TRUE
+#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_RX_DMA_CHN   0x00000000
+#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_SPI2_TX_DMA_CHN   0x00000000
+
+#define STM32_HAS_SPI3          FALSE
+#define STM32_SPI3_RX_DMA_MSK   0
+#define STM32_SPI3_RX_DMA_CHN   0x00000000
+#define STM32_SPI3_TX_DMA_MSK   0
+#define STM32_SPI3_TX_DMA_CHN   0x00000000
+
+/* TIM attributes.*/
+#define STM32_HAS_TIM1          TRUE
+#define STM32_HAS_TIM2          TRUE
+#define STM32_HAS_TIM3          TRUE
+#define STM32_HAS_TIM4          FALSE
+#define STM32_HAS_TIM5          FALSE
+#define STM32_HAS_TIM6          TRUE
+#define STM32_HAS_TIM7          FALSE
+#define STM32_HAS_TIM8          FALSE
+#define STM32_HAS_TIM9          FALSE
+#define STM32_HAS_TIM10         FALSE
+#define STM32_HAS_TIM11         FALSE
+#define STM32_HAS_TIM12         FALSE
+#define STM32_HAS_TIM13         FALSE
+#define STM32_HAS_TIM14         TRUE
+#define STM32_HAS_TIM15         TRUE
+#define STM32_HAS_TIM16         TRUE
+#define STM32_HAS_TIM17         TRUE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1        TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART2        TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART3        FALSE
+#define STM32_USART3_RX_DMA_MSK 0
+#define STM32_USART3_RX_DMA_CHN 0x00000000
+#define STM32_USART3_TX_DMA_MSK 0
+#define STM32_USART3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_UART4         FALSE
+#define STM32_UART4_RX_DMA_MSK  0
+#define STM32_UART4_RX_DMA_CHN  0x00000000
+#define STM32_UART4_TX_DMA_MSK  0
+#define STM32_UART4_TX_DMA_CHN  0x00000000
+
+#define STM32_HAS_UART5         FALSE
+#define STM32_UART5_RX_DMA_MSK  0
+#define STM32_UART5_RX_DMA_CHN  0x00000000
+#define STM32_UART5_TX_DMA_MSK  0
+#define STM32_UART5_TX_DMA_CHN  0x00000000
+
+#define STM32_HAS_USART6        FALSE
+#define STM32_USART6_RX_DMA_MSK 0
+#define STM32_USART6_RX_DMA_CHN 0x00000000
+#define STM32_USART6_TX_DMA_MSK 0
+#define STM32_USART6_TX_DMA_CHN 0x00000000
+
+/* USB attributes.*/
+#define STM32_HAS_USB           TRUE
+#define STM32_HAS_OTG1          FALSE
+#define STM32_HAS_OTG2          FALSE
+/** @} */
+
+/*===========================================================================*/
+/* Platform specific friendly IRQ names.                                     */
+/*===========================================================================*/
+
+/**
+ * @name  IRQ VECTOR names
+ * @{
+ */
+#define WWDG_IRQHandler         Vector40    /**< Window Watchdog.           */
+#define PVD_IRQHandler          Vector44    /**< PVD through EXTI Line
+                                                 detect.                    */
+#define RTC_IRQHandler          Vector48    /**< RTC.                       */
+#define FLASH_IRQHandler        Vector4C    /**< Flash.                     */
+#define RCC_IRQHandler          Vector50    /**< RCC.                       */
+#define EXTI0_1_IRQHandler      Vector54    /**< EXTI Line 0..1.            */
+#define EXTI2_3_IRQHandler      Vector58    /**< EXTI Line 2..3.            */
+#define EXTI4_15_IRQHandler     Vector5C    /**< EXTI Line 4..15.           */
+#define TS_IRQHandler           Vector60    /**< TS.                        */
+#define DMA1_Ch1_IRQHandler     Vector64    /**< DMA1 Channel 1.            */
+#define DMA1_Ch2_3_IRQHandler   Vector68    /**< DMA1 Channels 2 and 3.     */
+#define DMA1_Ch4_5_IRQHandler   Vector6C    /**< DMA1 Channels 4 and 5.     */
+#define ADC1_COMP_IRQHandler    Vector70    /**< ADC1 comparators 1 and 2.  */
+#define TIM1_BRK_UP_TRG_COM_IRQHandler Vector74 /**< TIM1 common.           */
+#define TIM1_CC_IRQHandler      Vector78    /**< TIM1 Capture Compare.      */
+#define TIM2_IRQHandler         Vector7C    /**< TIM2.                      */
+#define TIM3_IRQHandler         Vector80    /**< TIM3.                      */
+#define TIM6_DAC_IRQHandler     Vector84    /**< TIM6 and DAC.              */
+#define TIM14_IRQHandler        Vector8C    /**< TIM14.                     */
+#define TIM15_IRQHandler        Vector90    /**< TIM15.                     */
+#define TIM16_IRQHandler        Vector94    /**< TIM16.                     */
+#define TIM17_IRQHandler        Vector98    /**< TIM17.                     */
+#define I2C1_IRQHandler         Vector9C    /**< I2C1.                      */
+#define I2C2_IRQHandler         VectorA0    /**< I2C2.                      */
+#define SPI1_IRQHandler         VectorA4    /**< SPI1.                      */
+#define SPI2_IRQHandler         VectorA8    /**< SPI2.                      */
+#define USART1_IRQHandler       VectorAC    /**< USART1.                    */
+#define USART2_IRQHandler       VectorB0    /**< USART2.                    */
+#define CEC_IRQHandler          VectorB8    /**< CEC.                       */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT               FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE            FALSE
+#endif
+
+/**
+ * @brief   Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS                   STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief   Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED           TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED           FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED           TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED           FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if (STM32_LSECLK == 0)
+#error "LSE frequency not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL activation conditions.*/
+#if STM32_USB_CLOCK_REQUIRED ||                                             \
+    (STM32_SW == STM32_SW_PLL) ||                                           \
+    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL          TRUE
+#else
+#define STM32_ACTIVATE_PLL          FALSE
+#endif
+
+/* HSE prescaler setting check.*/
+#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) &&                              \
+    (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
+#error "invalid STM32_PLLXTPRE value specified"
+#endif
+
+/**
+ * @brief   PLLMUL field.
+ */
+#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
+    defined(__DOXYGEN__)
+#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
+#define STM32_PLLCLKIN              (STM32_HSECLK / 1)
+#else
+#define STM32_PLLCLKIN              (STM32_HSECLK / 2)
+#endif
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/**
+ * @brief   PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief   System clock source.
+ */
+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#define STM32_SYSCLK                STM32_PLLCLKOUT
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK                STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK                STM32_HSECLK
+#else
+#error "invalid STM32_SYSCLK_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK                  (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK                  (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK                  (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK                  (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK                  (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK                  (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK                  (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK                  (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK                  (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1                 (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1                 (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1                 (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1                 (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief   APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2                 (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2                 (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2                 (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2                 (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2                 (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief   RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
+#define STM32_RTCCLK                STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK                STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK                (STM32_HSECLK / 128)
+#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+#define STM32_RTCCLK                0
+#else
+#error "invalid source selected for RTC clock"
+#endif
+
+/**
+ * @brief   ADC frequency.
+ */
+#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
+#define STM32_ADCCLK                (STM32_PCLK2 / 2)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
+#define STM32_ADCCLK                (STM32_PCLK2 / 4)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
+#define STM32_ADCCLK                (STM32_PCLK2 / 6)
+#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
+#define STM32_ADCCLK                (STM32_PCLK2 / 8)
+#else
+#error "invalid STM32_ADCPRE value specified"
+#endif
+
+/* ADC frequency check.*/
+#if STM32_ADCCLK > STM32_ADCCLK_MAX
+#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+/**
+ * @brief   USB frequency.
+ */
+#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
+#define STM32_USBCLK                ((STM32_PLLCLKOUT * 2) / 3)
+#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
+#define STM32_USBCLK                STM32_PLLCLKOUT
+#else
+#error "invalid STM32_USBPRE value specified"
+#endif
+
+/**
+ * @brief   Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief   Timers 1, 8, 9, 10, 11 clock.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief   Flash settings.
+ */
+#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS             0x00000010
+#elif STM32_HCLK <= 48000000
+#define STM32_FLASHBITS             0x00000011
+#else
+#define STM32_FLASHBITS             0x00000012
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* STM32 DMA and RCC helpers.*/
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
-- 
cgit v1.2.3


From d25f85f0ea9b8340a9f16000c43f218a34e56477 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 16 May 2012 19:33:53 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4203
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 1689c24e2..fa5f3195b 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -354,7 +354,8 @@
 #define WWDG_IRQHandler         Vector40    /**< Window Watchdog.           */
 #define PVD_IRQHandler          Vector44    /**< PVD through EXTI Line
                                                  detect.                    */
-#define RTC_IRQHandler          Vector48    /**< RTC.                       */
+#define RTC_IRQHandler          Vector48    /**< RTC through EXTI Line
+                                                 Interrupt.                 */
 #define FLASH_IRQHandler        Vector4C    /**< Flash.                     */
 #define RCC_IRQHandler          Vector50    /**< RCC.                       */
 #define EXTI0_1_IRQHandler      Vector54    /**< EXTI Line 0..1.            */
-- 
cgit v1.2.3


From 76ac6302c73df7ab7da020b3ce412d2bdeafb2ea Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 17 May 2012 16:47:17 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4204
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.h | 236 ++++++++++++++++++++++++-----------
 1 file changed, 162 insertions(+), 74 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index fa5f3195b..74df91f54 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -193,6 +193,26 @@
                                                  RTC clock.                 */
 /** @} */
 
+/**
+ * @name    RCC_CFGR3 register bits definitions
+ * @{
+ */
+#define STM32_USART1SW_MASK     (3 << 0)    /**< RTC clock source mask.     */
+#define STM32_USART1SW_PCLK     (0 << 0)    /**< USART1 clock is PCLK.      */
+#define STM32_USART1SW_SYSCLK   (1 << 0)    /**< USART1 clock is SYSCLK.    */
+#define STM32_USART1SW_LSE      (2 << 0)    /**< USART1 clock is LSE.       */
+#define STM32_USART1SW_HSI      (3 << 0)    /**< USART1 clock is HSI.       */
+#define STM32_I2C1SW_MASK       (1 << 4)    /**< I2C clock source mask.     */
+#define STM32_I2C1SW_HSI        (0 << 4)    /**< I2C clock is HSI.          */
+#define STM32_I2C1SW_SYSCLK     (1 << 4)    /**< I2C clock is SYSCLK.       */
+#define STM32_CECSW_MASK        (1 << 6)    /**< CEC clock source mask.     */
+#define STM32_CECSW_HSI         (0 << 6)    /**< CEC clock is HSI/244.      */
+#define STM32_CECSW_LSE         (1 << 6)    /**< CEC clock is LSE.          */
+#define STM32_ADCSW_MASK        (1 << 8)    /**< ADC clock source mask.     */
+#define STM32_ADCSW_HSI14       (0 << 8)    /**< ADC clock is HSI14.        */
+#define STM32_ADCSW_PCLK        (1 << 8)    /**< ADC clock is PCLK/2|4.     */
+/** @} */
+
 /*===========================================================================*/
 /* Platform capabilities.                                                    */
 /*===========================================================================*/
@@ -420,6 +440,13 @@
 #define STM32_HSI_ENABLED           TRUE
 #endif
 
+/**
+ * @brief   Enables or disables the HSI14 clock source.
+ */
+#if !defined(STM32_HSI14_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI14_ENABLED         TRUE
+#endif
+
 /**
  * @brief   Enables or disables the LSI clock source.
  */
@@ -440,6 +467,91 @@
 #if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
 #define STM32_LSE_ENABLED           FALSE
 #endif
+/**
+ * @brief   Main clock source selection.
+ * @note    If the selected clock source is not the PLL then the PLL is not
+ *          initialized and started.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW                    STM32_SW_PLL
+#endif
+
+/**
+ * @brief   Clock source for the PLL.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC                STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief   Crystal PLL pre-divider.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
+#define STM32_PLLXTPRE              STM32_PLLXTPRE_DIV1
+#endif
+
+/**
+ * @brief   PLL multiplier value.
+ * @note    The allowed range is 2...16.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE          9
+#endif
+
+/**
+ * @brief   AHB prescaler value.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE                  STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief   APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE) || defined(__DOXYGEN__)
+#define STM32_PPRE                  STM32_PPRE_DIV2
+#endif
+
+/**
+ * @brief   ADC clock source.
+ */
+#if !defined(STM32_ADCSW) || defined(__DOXYGEN__)
+#define STM32_ADCSW                 STM32_ADCSW_HSI14
+
+/**
+ * @brief   ADC prescaler value.
+ */
+#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
+#define STM32_ADCPRE                STM32_ADCPRE_DIV4
+#endif
+
+/**
+ * @brief   MCO pin setting.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL                STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief   RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL                STM32_RTCSEL_LSI
+#endif
 /** @} */
 
 /*===========================================================================*/
@@ -468,6 +580,22 @@
 
 #endif /* !STM32_HSI_ENABLED */
 
+/*
+ * HSI14 related checks.
+ */
+#if STM32_HSI14_ENABLED
+#else /* !STM32_HSI14_ENABLED */
+
+#if STM32_MCOSEL == STM32_MCOSEL_HSI14
+#error "HSI14 not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_ADCSW == STM32_ADCSW_HSI14
+#error "HSI14 not enabled, required by STM32_ADCSW"
+#endif
+
+#endif /* !STM32_HSI14_ENABLED */
+
 /*
  * HSE related checks.
  */
@@ -490,7 +618,8 @@
 #endif
 
 #if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSE))
 #error "HSE not enabled, required by STM32_MCOSEL"
 #endif
 
@@ -534,8 +663,7 @@
 #endif /* !STM32_LSE_ENABLED */
 
 /* PLL activation conditions.*/
-#if STM32_USB_CLOCK_REQUIRED ||                                             \
-    (STM32_SW == STM32_SW_PLL) ||                                           \
+#if (STM32_SW == STM32_SW_PLL) ||                                           \
     (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
     defined(__DOXYGEN__)
 /**
@@ -641,47 +769,25 @@
 #endif
 
 /**
- * @brief   APB1 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK1                 (STM32_HCLK / 1)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV2
-#define STM32_PCLK1                 (STM32_HCLK / 2)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV4
-#define STM32_PCLK1                 (STM32_HCLK / 4)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV8
-#define STM32_PCLK1                 (STM32_HCLK / 8)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV16
-#define STM32_PCLK1                 (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE1 value specified"
-#endif
-
-/* APB1 frequency check.*/
-#if STM32_PCLK1 > STM32_PCLK1_MAX
-#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
-#endif
-
-/**
- * @brief   APB2 frequency.
+ * @brief   APB frequency.
  */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK2                 (STM32_HCLK / 1)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV2
-#define STM32_PCLK2                 (STM32_HCLK / 2)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV4
-#define STM32_PCLK2                 (STM32_HCLK / 4)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV8
-#define STM32_PCLK2                 (STM32_HCLK / 8)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV16
-#define STM32_PCLK2                 (STM32_HCLK / 16)
+#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK                  (STM32_HCLK / 1)
+#elif STM32_PPRE == STM32_PPRE_DIV2
+#define STM32_PCLK                  (STM32_HCLK / 2)
+#elif STM32_PPRE == STM32_PPRE_DIV4
+#define STM32_PCLK                  (STM32_HCLK / 4)
+#elif STM32_PPRE == STM32_PPRE_DIV8
+#define STM32_PCLK                  (STM32_HCLK / 8)
+#elif STM32_PPRE == STM32_PPRE_DIV16
+#define STM32_PCLK                  (STM32_HCLK / 16)
 #else
-#error "invalid STM32_PPRE2 value specified"
+#error "invalid STM32_PPRE value specified"
 #endif
 
-/* APB2 frequency check.*/
-#if STM32_PCLK2 > STM32_PCLK2_MAX
-#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+/* APB frequency check.*/
+#if STM32_PCLK > STM32_PCLK_MAX
+#error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)"
 #endif
 
 /**
@@ -692,7 +798,7 @@
 #elif STM32_RTCSEL == STM32_RTCSEL_LSI
 #define STM32_RTCCLK                STM32_LSICLK
 #elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK                (STM32_HSECLK / 128)
+#define STM32_RTCCLK                (STM32_HSECLK / 32)
 #elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
 #define STM32_RTCCLK                0
 #else
@@ -702,17 +808,19 @@
 /**
  * @brief   ADC frequency.
  */
+#if STM32_ADCSW == STM32_ADCSW_HSI14
+#define STM32_ADCCLK                STM32_HSI14CLK
+#elif STM32_ADCSW == STM32_ADCSW_PCLK
 #if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
-#define STM32_ADCCLK                (STM32_PCLK2 / 2)
+#define STM32_ADCCLK                (STM32_PCLK / 2)
 #elif STM32_ADCPRE == STM32_ADCPRE_DIV4
-#define STM32_ADCCLK                (STM32_PCLK2 / 4)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
-#define STM32_ADCCLK                (STM32_PCLK2 / 6)
-#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
-#define STM32_ADCCLK                (STM32_PCLK2 / 8)
+#define STM32_ADCCLK                (STM32_PCLK / 4)
 #else
 #error "invalid STM32_ADCPRE value specified"
 #endif
+#else
+#error "invalid source selected for ADC clock"
+#endif
 
 /* ADC frequency check.*/
 #if STM32_ADCCLK > STM32_ADCCLK_MAX
@@ -720,32 +828,14 @@
 #endif
 
 /**
- * @brief   USB frequency.
+ * @brief   Timers clock.
  */
-#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
-#define STM32_USBCLK                ((STM32_PLLCLKOUT * 2) / 3)
-#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
-#define STM32_USBCLK                STM32_PLLCLKOUT
+#if (STM32_PPRE == STM32_PPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1               (STM32_PCLK * 1)
+#define STM32_TIMCLK2               (STM32_PCLK * 1)
 #else
-#error "invalid STM32_USBPRE value specified"
-#endif
-
-/**
- * @brief   Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
-#else
-#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
-#endif
-
-/**
- * @brief   Timers 1, 8, 9, 10, 11 clock.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
-#else
-#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
+#define STM32_TIMCLK1               (STM32_PCLK * 2)
+#define STM32_TIMCLK2               (STM32_PCLK * 2)
 #endif
 
 /**
@@ -753,10 +843,8 @@
  */
 #if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
 #define STM32_FLASHBITS             0x00000010
-#elif STM32_HCLK <= 48000000
-#define STM32_FLASHBITS             0x00000011
 #else
-#define STM32_FLASHBITS             0x00000012
+#define STM32_FLASHBITS             0x00000011
 #endif
 
 /*===========================================================================*/
-- 
cgit v1.2.3


From c4a3d44d53f667cc73abf655542b2974a9b0bb93 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 17 May 2012 18:44:03 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4205
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.c   | 91 ----------------------------------
 os/hal/platforms/STM32F0xx/hal_lld.h   | 21 ++++----
 os/hal/platforms/STM32F0xx/platform.mk |  5 ++
 os/hal/platforms/STM32F0xx/stm32f0xx.h |  3 +-
 4 files changed, 18 insertions(+), 102 deletions(-)
 create mode 100644 os/hal/platforms/STM32F0xx/platform.mk

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
index 806ec3ea3..24dc11f5c 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -132,13 +132,6 @@ void hal_lld_init(void) {
  *
  * @special
  */
-#if defined(STM32F10X_LD) || defined(STM32F10X_LD_VL) ||                    \
-    defined(STM32F10X_MD) || defined(STM32F10X_MD_VL) ||                    \
-    defined(STM32F10X_HD) || defined(STM32F10X_XL) ||                       \
-    defined(__DOXYGEN__)
-/*
- * Clocks initialization for all sub-families except CL.
- */
 void stm32_clock_init(void) {
 
 #if !STM32_NO_INIT
@@ -198,88 +191,4 @@ void stm32_clock_init(void) {
 #endif /* !STM32_NO_INIT */
 }
 
-#elif defined(STM32F10X_CL)
-/*
- * Clocks initialization for the CL sub-family.
- */
-void stm32_clock_init(void) {
-
-#if !STM32_NO_INIT
-  /* HSI setup.*/
-  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;                                       /* Wait until HSI is stable.    */
-  RCC->CFGR = 0;
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;                                       /* Wait until HSI is the source.*/
-
-#if STM32_HSE_ENABLED
-#if defined(STM32_HSE_BYPASS)
-  /* HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEBYP;
-#endif
-  /* HSE activation.*/
-  RCC->CR |= RCC_CR_HSEON;
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;                                       /* Waits until HSE is stable.   */
-#endif
-
-#if STM32_LSI_ENABLED
-  /* LSI activation.*/
-  RCC->CSR |= RCC_CSR_LSION;
-  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
-    ;                                       /* Waits until LSI is stable.   */
-#endif
-
-  /* Settings of various dividers and multipliers in CFGR2.*/
-  RCC->CFGR2 = STM32_PLL3MUL | STM32_PLL2MUL | STM32_PREDIV2 |
-               STM32_PREDIV1 | STM32_PREDIV1SRC;
-
-  /* PLL2 setup, if activated.*/
-#if STM32_ACTIVATE_PLL2
-  RCC->CR |= RCC_CR_PLL2ON;
-  while (!(RCC->CR & RCC_CR_PLL2RDY))
-    ;                                        /* Waits until PLL2 is stable. */
-#endif
-
-  /* PLL3 setup, if activated.*/
-#if STM32_ACTIVATE_PLL3
-  RCC->CR |= RCC_CR_PLL3ON;
-  while (!(RCC->CR & RCC_CR_PLL3RDY))
-    ;                                        /* Waits until PLL3 is stable. */
-#endif
-
-  /* PLL1 setup, if activated.*/
-#if STM32_ACTIVATE_PLL1
-  RCC->CFGR |= STM32_PLLMUL | STM32_PLLSRC;
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;                           /* Waits until PLL1 is stable.              */
-#endif
-
-  /* Clock settings.*/
-#if STM32_HAS_OTG1
-  RCC->CFGR = STM32_MCOSEL | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC |
-              STM32_ADCPRE | STM32_PPRE2    | STM32_PPRE1  | STM32_HPRE;
-#else
-  RCC->CFGR = STM32_MCO    |                  STM32_PLLMUL | STM32_PLLSRC |
-              STM32_ADCPRE | STM32_PPRE2    | STM32_PPRE1  | STM32_HPRE;
-#endif
-
-  /* Flash setup and final clock selection.   */
-  FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock.    */
-
-  /* Switching to the configured clock source if it is different from HSI.*/
-#if (STM32_SW != STM32_SW_HSI)
-  RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;
-#endif
-#endif /* !STM32_NO_INIT */
-}
-#else
-void stm32_clock_init(void) {}
-#endif
-
 /** @} */
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 74df91f54..3b66910fc 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -38,7 +38,7 @@
 #ifndef _HAL_LLD_H_
 #define _HAL_LLD_H_
 
-#include "stm32.h"
+#include "stm32f0xx.h"
 
 /*===========================================================================*/
 /* Driver constants.                                                         */
@@ -471,7 +471,7 @@
  * @brief   Main clock source selection.
  * @note    If the selected clock source is not the PLL then the PLL is not
  *          initialized and started.
- * @note    The default value is calculated for a 72MHz system clock from
+ * @note    The default value is calculated for a 48MHz system clock from
  *          a 8MHz crystal using the PLL.
  */
 #if !defined(STM32_SW) || defined(__DOXYGEN__)
@@ -482,7 +482,7 @@
  * @brief   Clock source for the PLL.
  * @note    This setting has only effect if the PLL is selected as the
  *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
+ * @note    The default value is calculated for a 48MHz system clock from
  *          a 8MHz crystal using the PLL.
  */
 #if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
@@ -493,7 +493,7 @@
  * @brief   Crystal PLL pre-divider.
  * @note    This setting has only effect if the PLL is selected as the
  *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
+ * @note    The default value is calculated for a 48MHz system clock from
  *          a 8MHz crystal using the PLL.
  */
 #if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
@@ -503,16 +503,16 @@
 /**
  * @brief   PLL multiplier value.
  * @note    The allowed range is 2...16.
- * @note    The default value is calculated for a 72MHz system clock from
+ * @note    The default value is calculated for a 48MHz system clock from
  *          a 8MHz crystal using the PLL.
  */
 #if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLMUL_VALUE          9
+#define STM32_PLLMUL_VALUE          6
 #endif
 
 /**
  * @brief   AHB prescaler value.
- * @note    The default value is calculated for a 72MHz system clock from
+ * @note    The default value is calculated for a 48MHz system clock from
  *          a 8MHz crystal using the PLL.
  */
 #if !defined(STM32_HPRE) || defined(__DOXYGEN__)
@@ -523,7 +523,7 @@
  * @brief   APB1 prescaler value.
  */
 #if !defined(STM32_PPRE) || defined(__DOXYGEN__)
-#define STM32_PPRE                  STM32_PPRE_DIV2
+#define STM32_PPRE                  STM32_PPRE_DIV1
 #endif
 
 /**
@@ -531,6 +531,7 @@
  */
 #if !defined(STM32_ADCSW) || defined(__DOXYGEN__)
 #define STM32_ADCSW                 STM32_ADCSW_HSI14
+#endif
 
 /**
  * @brief   ADC prescaler value.
@@ -860,8 +861,8 @@
 /*===========================================================================*/
 
 /* STM32 DMA and RCC helpers.*/
-#include "stm32_dma.h"
-#include "stm32_rcc.h"
+/*#include "stm32_dma.h"
+#include "stm32_rcc.h"*/
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
new file mode 100644
index 000000000..c22930f58
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -0,0 +1,5 @@
+# List of all the STM32F1xx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx
\ No newline at end of file
diff --git a/os/hal/platforms/STM32F0xx/stm32f0xx.h b/os/hal/platforms/STM32F0xx/stm32f0xx.h
index 07c252c11..23ee738ec 100644
--- a/os/hal/platforms/STM32F0xx/stm32f0xx.h
+++ b/os/hal/platforms/STM32F0xx/stm32f0xx.h
@@ -213,7 +213,8 @@ typedef enum IRQn
   */
 
 #include "core_cm0.h"
-#include "system_stm32f0xx.h"
+/* CHIBIOS FIX */
+/*#include "system_stm32f0xx.h"*/
 #include <stdint.h>
 
 /** @addtogroup Exported_types
-- 
cgit v1.2.3


From 01a811d27f05c73904200aaeaf618ed657b65283 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 18 May 2012 15:29:20 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4206
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.c   |  30 +-
 os/hal/platforms/STM32F0xx/hal_lld.h   |  94 +++++-
 os/hal/platforms/STM32F0xx/platform.mk |   6 +-
 os/hal/platforms/STM32F0xx/stm32_rcc.h | 546 +++++++++++++++++++++++++++++++++
 os/hal/platforms/STM32F0xx/stm32f0xx.h |   4 +-
 5 files changed, 654 insertions(+), 26 deletions(-)
 create mode 100644 os/hal/platforms/STM32F0xx/stm32_rcc.h

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
index 24dc11f5c..401afe7e3 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -95,7 +95,7 @@ void hal_lld_init(void) {
 
   /* Reset of all peripherals.*/
   rccResetAPB1(0xFFFFFFFF);
-  rccResetAPB2(0xFFFFFFFF);
+  rccResetAPB2(!RCC_APB2RSTR_DBGMCURST);
 
   /* SysTick initialization using the system clock.*/
   SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
@@ -104,13 +104,8 @@ void hal_lld_init(void) {
                   SysTick_CTRL_ENABLE_Msk |
                   SysTick_CTRL_TICKINT_Msk;
 
-  /* DWT cycle counter enable.*/
-  SCS_DEMCR |= SCS_DEMCR_TRCENA;
-  DWT_CTRL  |= DWT_CTRL_CYCCNTENA;
-
   /* PWR and BD clocks enabled.*/
   rccEnablePWRInterface(FALSE);
-  rccEnableBKPInterface(FALSE);
 
   /* Initializes the backup domain.*/
   hal_lld_backup_domain_init();
@@ -152,6 +147,13 @@ void stm32_clock_init(void) {
     ;                                       /* Waits until HSE is stable.   */
 #endif
 
+#if STM32_HSE14_ENABLED
+  /* HSI14 activation.*/
+  RCC->CR2 |= RCC_CR2_HSI14ON;
+  while (!(RCC->CR2 & RCC_CR2_HSI14RDY))
+    ;                                       /* Waits until HSI14 is stable. */
+#endif
+
 #if STM32_LSI_ENABLED
   /* LSI activation.*/
   RCC->CSR |= RCC_CSR_LSION;
@@ -168,15 +170,9 @@ void stm32_clock_init(void) {
 #endif
 
   /* Clock settings.*/
-#if STM32_HAS_USB
-  RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE |
-              STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2  | STM32_PPRE1    |
-              STM32_HPRE;
-#else
-  RCC->CFGR = STM32_MCOSEL |                STM32_PLLMUL | STM32_PLLXTPRE |
-              STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2  | STM32_PPRE1    |
-              STM32_HPRE;
-#endif
+  RCC->CFGR  = STM32_MCOSEL |                STM32_PLLMUL | STM32_PLLXTPRE |
+               STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE   | STM32_HPRE;
+  RCC->CFGR3 = STM32_ADCSW  | STM32_CECSW  | STM32_I2C1SW | STM32_USART1SW;
 
   /* Flash setup and final clock selection.   */
   FLASH->ACR = STM32_FLASHBITS;
@@ -188,6 +184,10 @@ void stm32_clock_init(void) {
   while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
     ;                                       /* Waits selection complete.    */
 #endif
+
+  /* SYSCFG clock enabled here because it is a multi-functional unit shared
+     among multiple drivers.*/
+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
 #endif /* !STM32_NO_INIT */
 }
 
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 3b66910fc..1bd31c168 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -527,10 +527,10 @@
 #endif
 
 /**
- * @brief   ADC clock source.
+ * @brief   MCO pin setting.
  */
-#if !defined(STM32_ADCSW) || defined(__DOXYGEN__)
-#define STM32_ADCSW                 STM32_ADCSW_HSI14
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL                STM32_MCOSEL_NOCLOCK
 #endif
 
 /**
@@ -541,10 +541,31 @@
 #endif
 
 /**
- * @brief   MCO pin setting.
+ * @brief   ADC clock source.
  */
-#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
-#define STM32_MCOSEL                STM32_MCOSEL_NOCLOCK
+#if !defined(STM32_ADCSW) || defined(__DOXYGEN__)
+#define STM32_ADCSW                 STM32_ADCSW_HSI14
+#endif
+
+/**
+ * @brief   CEC clock source.
+ */
+#if !defined(STM32_CECSW) || defined(__DOXYGEN__)
+#define STM32_CECSW                 STM32_CECSW_HSI
+#endif
+
+/**
+ * @brief   I2C1 clock source.
+ */
+#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
+#define STM32_I2C1SW                STM32_I2C1SW_HSI
+#endif
+
+/**
+ * @brief   USART1 clock source.
+ */
+#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
+#define STM32_USART1SW              STM32_USART1SW_PCLK
 #endif
 
 /**
@@ -569,6 +590,18 @@
 #error "HSI not enabled, required by STM32_SW"
 #endif
 
+#if STM32_CECSW == STM32_CECSW_HSI
+#error "HSI not enabled, required by STM32_CECSW"
+#endif
+
+#if STM32_I2C1SW == STM32_I2C1SW_HSI
+#error "HSI not enabled, required by STM32_I2C1SW"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_HSI
+#error "HSI not enabled, required by STM32_USART1SW"
+#endif
+
 #if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
 #error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
 #endif
@@ -651,6 +684,14 @@
 #error "LSE frequency not defined"
 #endif
 
+#if STM32_CECSW == STM32_CECSW_LSE
+#error "LSE not enabled, required by STM32_CECSW"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_LSE
+#error "LSE not enabled, required by STM32_USART1SW"
+#endif
+
 #if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
 #error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
 #endif
@@ -828,6 +869,43 @@
 #error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
 #endif
 
+/**
+ * @brief   CEC frequency.
+ */
+#if STM32_CECSW == STM32_CECSW_HSI
+#define STM32_CECCLK                STM32_HSICLK
+#elif STM32_CECSW == STM32_CECSW_LSE
+#define STM32_CECCLK                STM32_LSECLK
+#else
+#error "invalid source selected for CEC clock"
+#endif
+
+/**
+ * @brief   I2C1 frequency.
+ */
+#if STM32_I2CSW == STM32_I2C1SW_HSI
+#define STM32_I2C1CLK               STM32_HSICLK
+#elif STM32_I2CSW == STM32_I2C1SW_SYSCLK
+#define STM32_I2C1CLK               STM32_SYSCLK
+#else
+#error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief   USART1 frequency.
+ */
+#if STM32_USART1SW == STM32_USART1SW_PCLK
+#define STM32_USART1CLK             STM32_PCLK
+#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
+#define STM32_USART1CLK             STM32_SYSCLK
+#elif STM32_USART1SW == STM32_USART1SW_LSECLK
+#define STM32_USART1CLK             STM32_LSECLK
+#elif STM32_USART1SW == STM32_USART1SW_HSICLK
+#define STM32_USART1CLK             STM32_HSICLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
 /**
  * @brief   Timers clock.
  */
@@ -861,8 +939,8 @@
 /*===========================================================================*/
 
 /* STM32 DMA and RCC helpers.*/
-/*#include "stm32_dma.h"
-#include "stm32_rcc.h"*/
+/*#include "stm32_dma.h"*/
+#include "stm32_rcc.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index c22930f58..f27c753f4 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -1,5 +1,7 @@
 # List of all the STM32F1xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/hal_lld.c
+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c
 
 # Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx
\ No newline at end of file
+PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
+              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2
diff --git a/os/hal/platforms/STM32F0xx/stm32_rcc.h b/os/hal/platforms/STM32F0xx/stm32_rcc.h
new file mode 100644
index 000000000..d10aa6de7
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/stm32_rcc.h
@@ -0,0 +1,546 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F0xx/stm32_rcc.h
+ * @brief   RCC helper driver header.
+ * @note    This file requires definitions from the ST header file
+ *          @p stm32f0xx.h.
+ *
+ * @addtogroup STM32F0xx_RCC
+ * @{
+ */
+
+#ifndef _STM32_RCC_
+#define _STM32_RCC_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Generic RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the clock of one or more peripheral on the APB1 bus.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] mask      APB1 peripherals mask
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1(mask, lp) {                                           \
+  RCC->APB1ENR |= (mask);                                                   \
+}
+
+/**
+ * @brief   Disables the clock of one or more peripheral on the APB1 bus.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] mask      APB1 peripherals mask
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB1(mask, lp) {                                          \
+  RCC->APB1ENR &= ~(mask);                                                  \
+}
+
+/**
+ * @brief   Resets one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask      APB1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1(mask) {                                                \
+  RCC->APB1RSTR |= (mask);                                                  \
+  RCC->APB1RSTR = 0;                                                        \
+}
+
+/**
+ * @brief   Enables the clock of one or more peripheral on the APB2 bus.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] mask      APB2 peripherals mask
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB2(mask, lp) {                                           \
+  RCC->APB2ENR |= (mask);                                                   \
+}
+
+/**
+ * @brief   Disables the clock of one or more peripheral on the APB2 bus.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] mask      APB2 peripherals mask
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB2(mask, lp) {                                          \
+  RCC->APB2ENR &= ~(mask);                                                  \
+}
+
+/**
+ * @brief   Resets one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask      APB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB2(mask) {                                                \
+  RCC->APB2RSTR |= (mask);                                                  \
+  RCC->APB2RSTR = 0;                                                        \
+}
+
+/**
+ * @brief   Enables the clock of one or more peripheral on the AHB bus.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] mask      AHB peripherals mask
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB(mask, lp) {                                            \
+  RCC->AHBENR |= (mask);                                                    \
+}
+
+/**
+ * @brief   Disables the clock of one or more peripheral on the AHB bus.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] mask      AHB peripherals mask
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAHB(mask, lp) {                                           \
+  RCC->AHBENR &= ~(mask);                                                   \
+}
+
+/**
+ * @brief   Resets one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask      AHB peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB(mask) {                                                 \
+  RCC->AHBRSTR |= (mask);                                                   \
+  RCC->AHBRSTR = 0;                                                         \
+}
+/** @} */
+
+/**
+ * @name    ADC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the ADC1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp)
+
+/**
+ * @brief   Disables the ADC1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp)
+
+/**
+ * @brief   Resets the ADC1 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
+/** @} */
+
+/**
+ * @name    PWR interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the PWR interface clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief   Disables PWR interface clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief   Resets the PWR interface.
+ *
+ * @api
+ */
+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
+/** @} */
+
+/**
+ * @name    DMA peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the DMA1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
+
+/**
+ * @brief   Disables the DMA1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
+
+/**
+ * @brief   Resets the DMA1 peripheral.
+ * @note    Not supported in this family, does nothing.
+ *
+ * @api
+ */
+#define rccResetDMA1()
+/** @} */
+
+/**
+ * @name    I2C peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the I2C1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief   Disables the I2C1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief   Resets the I2C1 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
+
+/**
+ * @brief   Enables the I2C2 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief   Disables the I2C2 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief   Resets the I2C2 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
+/** @} */
+
+/**
+ * @name    SPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the SPI1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief   Disables the SPI1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief   Resets the SPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
+
+/**
+ * @brief   Enables the SPI2 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief   Disables the SPI2 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief   Resets the SPI2 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
+/** @} */
+
+/**
+ * @name    TIM peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the TIM1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief   Disables the TIM1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief   Resets the TIM1 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
+
+/**
+ * @brief   Enables the TIM2 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief   Disables the TIM2 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief   Resets the TIM2 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
+
+/**
+ * @brief   Enables the TIM3 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief   Disables the TIM3 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief   Resets the TIM3 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
+/** @} */
+
+/**
+ * @name    USART/UART peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the USART1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief   Disables the USART1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief   Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
+
+/**
+ * @brief   Enables the USART2 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief   Disables the USART2 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief   Resets the USART2 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_RCC_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/stm32f0xx.h b/os/hal/platforms/STM32F0xx/stm32f0xx.h
index 23ee738ec..74bc8ff10 100644
--- a/os/hal/platforms/STM32F0xx/stm32f0xx.h
+++ b/os/hal/platforms/STM32F0xx/stm32f0xx.h
@@ -393,7 +393,8 @@ typedef struct
 /** 
   * @brief General Purpose IO
   */
-
+/* CHIBIOS FIX */
+#if 0
 typedef struct
 {
   __IO uint32_t MODER;        /*!< GPIO port mode register,                                  Address offset: 0x00 */
@@ -411,6 +412,7 @@ typedef struct
   __IO uint16_t BRR;          /*!< GPIO bit reset register,                                  Address offset: 0x28 */
   uint16_t RESERVED3;         /*!< Reserved,                                                                 0x2A */
 }GPIO_TypeDef;
+#endif
 
 /** 
   * @brief SysTem Configuration
-- 
cgit v1.2.3


From ba01b11a39f178169fe1517458cbfc9c3f5f9a0f Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 19 May 2012 12:28:14 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4214
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/platform.mk  |   1 +
 os/hal/platforms/STM32F0xx/serial_lld.c | 322 ++++++++++++++++++++++++++++++++
 os/hal/platforms/STM32F0xx/serial_lld.h | 182 ++++++++++++++++++
 3 files changed, 505 insertions(+)
 create mode 100644 os/hal/platforms/STM32F0xx/serial_lld.c
 create mode 100644 os/hal/platforms/STM32F0xx/serial_lld.h

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index f27c753f4..e34e8dd8e 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -1,5 +1,6 @@
 # List of all the STM32F1xx platform files.
 PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32F0xx/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c
 
 # Required include directories
diff --git a/os/hal/platforms/STM32F0xx/serial_lld.c b/os/hal/platforms/STM32F0xx/serial_lld.c
new file mode 100644
index 000000000..abb15b84a
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/serial_lld.c
@@ -0,0 +1,322 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32/serial_lld.c
+ * @brief   STM32 low level serial driver code.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief USART1 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+/** @brief USART2 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/** @brief Driver default configuration.*/
+static const SerialConfig default_config =
+{
+  SERIAL_DEFAULT_BITRATE,
+  0,
+  USART_CR2_STOP1_BITS | USART_CR2_LINEN,
+  0
+};
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   USART initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] config    the architecture-dependent serial driver configuration
+ */
+static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
+  USART_TypeDef *u = sdp->usart;
+
+  /*
+   * Baud rate setting.
+   */
+  if (sdp->usart == USART1)
+    u->BRR = STM32_USART1CLK / config->sc_speed;
+  else
+    u->BRR = STM32_PCLK / config->sc_speed;
+
+  /*
+   * Note that some bits are enforced.
+   */
+  u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE |
+                            USART_CR1_RXNEIE | USART_CR1_TE |
+                            USART_CR1_RE;
+  u->CR2 = config->sc_cr2 | USART_CR2_LBDIE;
+  u->CR3 = config->sc_cr3 | USART_CR3_EIE;
+  u->ICR = 0xFFFFFFFF;
+}
+
+/**
+ * @brief   USART de-initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] u         pointer to an USART I/O block
+ */
+static void usart_deinit(USART_TypeDef *u) {
+
+  u->CR1 = 0;
+  u->CR2 = 0;
+  u->CR3 = 0;
+}
+
+#if STM32_SERIAL_USE_USART1 || STM32_SERIAL_USE_USART2
+/**
+ * @brief   Error handling routine.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] isr       USART ISR register value
+ */
+static void set_error(SerialDriver *sdp, uint16_t isr) {
+  chnflags_t sts = 0;
+
+  if (isr & USART_ISR_ORE)
+    sts |= SD_OVERRUN_ERROR;
+  if (isr & USART_ISR_PE)
+    sts |= SD_PARITY_ERROR;
+  if (isr & USART_ISR_FE)
+    sts |= SD_FRAMING_ERROR;
+  if (isr & USART_ISR_NE)
+    sts |= SD_NOISE_ERROR;
+  chSysLockFromIsr();
+  chnAddFlagsI(sdp, sts);
+  chSysUnlockFromIsr();
+}
+
+/**
+ * @brief   Common IRQ handler.
+ *
+ * @param[in] sdp       communication channel associated to the USART
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+  USART_TypeDef *u = sdp->usart;
+  uint16_t cr1 = u->CR1;
+  uint16_t isr;
+
+  /* Reading and clearing status.*/
+  isr = u->ISR;
+  u->ICR = isr;
+
+  /* Error condition detection.*/
+  if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE  | USART_ISR_PE))
+    set_error(sdp, isr);
+  /* Special case, LIN break detection.*/
+  if (isr & USART_ISR_LBD) {
+    chSysLockFromIsr();
+    chnAddFlagsI(sdp, SD_BREAK_DETECTED);
+    chSysUnlockFromIsr();
+  }
+  /* Data available.*/
+  if (isr & USART_ISR_RXNE) {
+    chSysLockFromIsr();
+    sdIncomingDataI(sdp, (uint8_t)u->RDR);
+    chSysUnlockFromIsr();
+  }
+  /* Transmission buffer empty.*/
+  if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) {
+    msg_t b;
+    chSysLockFromIsr();
+    b = chOQGetI(&sdp->oqueue);
+    if (b < Q_OK) {
+      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+      u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
+    }
+    else
+      u->RDR = b;
+    chSysUnlockFromIsr();
+  }
+  /* Physical transmission end.*/
+  if (isr & USART_ISR_TC) {
+    chSysLockFromIsr();
+    chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
+    chSysUnlockFromIsr();
+    u->CR1 = cr1 & ~USART_CR1_TCIE;
+  }
+}
+#endif
+
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+static void notify1(GenericQueue *qp) {
+
+  (void)qp;
+  USART1->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+static void notify2(GenericQueue *qp) {
+
+  (void)qp;
+  USART2->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+/**
+ * @brief   USART1 interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(USART1_IRQHandler) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD1);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+/**
+ * @brief   USART2 interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(USART2_IRQHandler) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD2);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if STM32_SERIAL_USE_USART1
+  sdObjectInit(&SD1, NULL, notify1);
+  SD1.usart = USART1;
+#endif
+
+#if STM32_SERIAL_USE_USART2
+  sdObjectInit(&SD2, NULL, notify2);
+  SD2.usart = USART2;
+#endif
+}
+
+/**
+ * @brief   Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] config    the architecture-dependent serial driver configuration.
+ *                      If this parameter is set to @p NULL then a default
+ *                      configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+  if (config == NULL)
+    config = &default_config;
+
+  if (sdp->state == SD_STOP) {
+#if STM32_SERIAL_USE_USART1
+    if (&SD1 == sdp) {
+      rccEnableUSART1(FALSE);
+      nvicEnableVector(USART1_IRQn,
+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));
+    }
+#endif
+#if STM32_SERIAL_USE_USART2
+    if (&SD2 == sdp) {
+      rccEnableUSART2(FALSE);
+      nvicEnableVector(USART2_IRQn,
+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));
+    }
+#endif
+  }
+  usart_init(sdp, config);
+}
+
+/**
+ * @brief   Low level serial driver stop.
+ * @details De-initializes the USART, stops the associated clock, resets the
+ *          interrupt vector.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+  if (sdp->state == SD_READY) {
+    usart_deinit(sdp->usart);
+#if STM32_SERIAL_USE_USART1
+    if (&SD1 == sdp) {
+      rccDisableUSART1(FALSE);
+      nvicDisableVector(USART1_IRQn);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_USART2
+    if (&SD2 == sdp) {
+      rccDisableUSART2(FALSE);
+      nvicDisableVector(USART2_IRQn);
+      return;
+    }
+#endif
+  }
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/serial_lld.h b/os/hal/platforms/STM32F0xx/serial_lld.h
new file mode 100644
index 000000000..da41e66da
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/serial_lld.h
@@ -0,0 +1,182 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32/serial_lld.h
+ * @brief   STM32 low level serial driver header.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#ifndef _SERIAL_LLD_H_
+#define _SERIAL_LLD_H_
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   USART1 driver enable switch.
+ * @details If set to @p TRUE the support for USART1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART1             TRUE
+#endif
+
+/**
+ * @brief   USART2 driver enable switch.
+ * @details If set to @p TRUE the support for USART2 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART2             TRUE
+#endif
+
+/**
+ * @brief   USART1 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART1_PRIORITY        3
+#endif
+
+/**
+ * @brief   USART2 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART2_PRIORITY        3
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1
+#error "USART1 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2
+#error "USART2 not present in the selected device"
+#endif
+
+#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2
+#error "SERIAL driver activated but no USART/UART peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ *          in order to configure and start a serial driver operations.
+ * @note    This structure content is architecture dependent, each driver
+ *          implementation defines its own version and the custom static
+ *          initializers.
+ */
+typedef struct {
+  /**
+   * @brief Bit rate.
+   */
+  uint32_t                  sc_speed;
+  /**
+   * @brief Initialization value for the CR1 register.
+   */
+  uint16_t                  sc_cr1;
+  /**
+   * @brief Initialization value for the CR2 register.
+   */
+  uint16_t                  sc_cr2;
+  /**
+   * @brief Initialization value for the CR3 register.
+   */
+  uint16_t                  sc_cr3;
+} SerialConfig;
+
+/**
+ * @brief   @p SerialDriver specific data.
+ */
+#define _serial_driver_data                                                 \
+  _base_asynchronous_channel_data                                           \
+  /* Driver state.*/                                                        \
+  sdstate_t                 state;                                          \
+  /* Input queue.*/                                                         \
+  InputQueue                iqueue;                                         \
+  /* Output queue.*/                                                        \
+  OutputQueue               oqueue;                                         \
+  /* Input circular buffer.*/                                               \
+  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
+  /* Output circular buffer.*/                                              \
+  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
+  /* End of the mandatory fields.*/                                         \
+  /* Pointer to the USART registers block.*/                                \
+  USART_TypeDef             *usart;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*
+ * Extra USARTs definitions here (missing from the ST header file).
+ */
+#define USART_CR2_STOP1_BITS    (0 << 12)   /**< @brief CR2 1 stop bit value.*/
+#define USART_CR2_STOP0P5_BITS  (1 << 12)   /**< @brief CR2 0.5 stop bit value.*/
+#define USART_CR2_STOP2_BITS    (2 << 12)   /**< @brief CR2 2 stop bit value.*/
+#define USART_CR2_STOP1P5_BITS  (3 << 12)   /**< @brief CR2 1.5 stop bit value.*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
+extern SerialDriver SD2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void sd_lld_init(void);
+  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
+  void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SERIAL */
+
+#endif /* _SERIAL_LLD_H_ */
+
+/** @} */
-- 
cgit v1.2.3


From d2a9b5bfd856db84b2284e236021d01e4ff3b0a6 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 19 May 2012 15:30:51 +0000
Subject: Report for STM32F0xx, serial driver working.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4215 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/serial_lld.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/serial_lld.c b/os/hal/platforms/STM32F0xx/serial_lld.c
index abb15b84a..a611279a4 100644
--- a/os/hal/platforms/STM32F0xx/serial_lld.c
+++ b/os/hal/platforms/STM32F0xx/serial_lld.c
@@ -166,7 +166,7 @@ static void serve_interrupt(SerialDriver *sdp) {
       u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
     }
     else
-      u->RDR = b;
+      u->TDR = b;
     chSysUnlockFromIsr();
   }
   /* Physical transmission end.*/
-- 
cgit v1.2.3


From 7a6a1679a413987ffa47f2f9892e241f3448f5f0 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 24 May 2012 18:31:34 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4232
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.h    |  22 +-
 os/hal/platforms/STM32F0xx/platform.mk  |  11 +-
 os/hal/platforms/STM32F0xx/serial_lld.c | 322 --------------------------
 os/hal/platforms/STM32F0xx/serial_lld.h | 182 ---------------
 os/hal/platforms/STM32F0xx/stm32_dma.c  | 296 ++++++++++++++++++++++++
 os/hal/platforms/STM32F0xx/stm32_dma.h  | 395 ++++++++++++++++++++++++++++++++
 6 files changed, 716 insertions(+), 512 deletions(-)
 delete mode 100644 os/hal/platforms/STM32F0xx/serial_lld.c
 delete mode 100644 os/hal/platforms/STM32F0xx/serial_lld.h
 create mode 100644 os/hal/platforms/STM32F0xx/stm32_dma.c
 create mode 100644 os/hal/platforms/STM32F0xx/stm32_dma.h

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 1bd31c168..30a46fa79 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -38,7 +38,7 @@
 #ifndef _HAL_LLD_H_
 #define _HAL_LLD_H_
 
-#include "stm32f0xx.h"
+#include "stm32.h"
 
 /*===========================================================================*/
 /* Driver constants.                                                         */
@@ -223,8 +223,20 @@
  */
 /* ADC attributes.*/
 #define STM32_HAS_ADC1          TRUE
+#define STM32_ADC1_DMA_DEFAULT  STM32_DMA_STREAM_ID(1, 0)
+#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 0) |            \
+                                 STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_CHN      0x00000000
+
 #define STM32_HAS_ADC2          FALSE
+#define STM32_ADC2_DMA_DEFAULT  0
+#define STM32_ADC2_DMA_MSK      0x00000000
+#define STM32_ADC2_DMA_CHN      0x00000000
+
 #define STM32_HAS_ADC3          FALSE
+#define STM32_ADC3_DMA_DEFAULT  0
+#define STM32_ADC3_DMA_MSK      0x00000000
+#define STM32_ADC3_DMA_CHN      0x00000000
 
 /* CAN attributes.*/
 #define STM32_HAS_CAN1          FALSE
@@ -322,9 +334,11 @@
 
 /* USART attributes.*/
 #define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |            \
+                                 STM32_DMA_STREAM_ID_MSK(1, 5))
 #define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |            \
+                                 STM32_DMA_STREAM_ID_MSK(1, 4))
 #define STM32_USART1_TX_DMA_CHN 0x00000000
 
 #define STM32_HAS_USART2        TRUE
@@ -939,7 +953,7 @@
 /*===========================================================================*/
 
 /* STM32 DMA and RCC helpers.*/
-/*#include "stm32_dma.h"*/
+#include "stm32_dma.h"
 #include "stm32_rcc.h"
 
 #ifdef __cplusplus
diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index e34e8dd8e..9d13d064a 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -1,8 +1,11 @@
 # List of all the STM32F1xx platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F0xx/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c
+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
+              ${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c	\
+              ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c
 
 # Required include directories
 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2
+              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
+              ${CHIBIOS}/os/hal/platforms/STM32
diff --git a/os/hal/platforms/STM32F0xx/serial_lld.c b/os/hal/platforms/STM32F0xx/serial_lld.c
deleted file mode 100644
index a611279a4..000000000
--- a/os/hal/platforms/STM32F0xx/serial_lld.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    STM32/serial_lld.c
- * @brief   STM32 low level serial driver code.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#include "ch.h"
-#include "hal.h"
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief USART1 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-SerialDriver SD1;
-#endif
-
-/** @brief USART2 serial driver identifier.*/
-#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-SerialDriver SD2;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/** @brief Driver default configuration.*/
-static const SerialConfig default_config =
-{
-  SERIAL_DEFAULT_BITRATE,
-  0,
-  USART_CR2_STOP1_BITS | USART_CR2_LINEN,
-  0
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   USART initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
-  USART_TypeDef *u = sdp->usart;
-
-  /*
-   * Baud rate setting.
-   */
-  if (sdp->usart == USART1)
-    u->BRR = STM32_USART1CLK / config->sc_speed;
-  else
-    u->BRR = STM32_PCLK / config->sc_speed;
-
-  /*
-   * Note that some bits are enforced.
-   */
-  u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE |
-                            USART_CR1_RXNEIE | USART_CR1_TE |
-                            USART_CR1_RE;
-  u->CR2 = config->sc_cr2 | USART_CR2_LBDIE;
-  u->CR3 = config->sc_cr3 | USART_CR3_EIE;
-  u->ICR = 0xFFFFFFFF;
-}
-
-/**
- * @brief   USART de-initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] u         pointer to an USART I/O block
- */
-static void usart_deinit(USART_TypeDef *u) {
-
-  u->CR1 = 0;
-  u->CR2 = 0;
-  u->CR3 = 0;
-}
-
-#if STM32_SERIAL_USE_USART1 || STM32_SERIAL_USE_USART2
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] isr       USART ISR register value
- */
-static void set_error(SerialDriver *sdp, uint16_t isr) {
-  chnflags_t sts = 0;
-
-  if (isr & USART_ISR_ORE)
-    sts |= SD_OVERRUN_ERROR;
-  if (isr & USART_ISR_PE)
-    sts |= SD_PARITY_ERROR;
-  if (isr & USART_ISR_FE)
-    sts |= SD_FRAMING_ERROR;
-  if (isr & USART_ISR_NE)
-    sts |= SD_NOISE_ERROR;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] sdp       communication channel associated to the USART
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  USART_TypeDef *u = sdp->usart;
-  uint16_t cr1 = u->CR1;
-  uint16_t isr;
-
-  /* Reading and clearing status.*/
-  isr = u->ISR;
-  u->ICR = isr;
-
-  /* Error condition detection.*/
-  if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE  | USART_ISR_PE))
-    set_error(sdp, isr);
-  /* Special case, LIN break detection.*/
-  if (isr & USART_ISR_LBD) {
-    chSysLockFromIsr();
-    chnAddFlagsI(sdp, SD_BREAK_DETECTED);
-    chSysUnlockFromIsr();
-  }
-  /* Data available.*/
-  if (isr & USART_ISR_RXNE) {
-    chSysLockFromIsr();
-    sdIncomingDataI(sdp, (uint8_t)u->RDR);
-    chSysUnlockFromIsr();
-  }
-  /* Transmission buffer empty.*/
-  if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) {
-    msg_t b;
-    chSysLockFromIsr();
-    b = chOQGetI(&sdp->oqueue);
-    if (b < Q_OK) {
-      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-      u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
-    }
-    else
-      u->TDR = b;
-    chSysUnlockFromIsr();
-  }
-  /* Physical transmission end.*/
-  if (isr & USART_ISR_TC) {
-    chSysLockFromIsr();
-    chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
-    chSysUnlockFromIsr();
-    u->CR1 = cr1 & ~USART_CR1_TCIE;
-  }
-}
-#endif
-
-#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-static void notify1(GenericQueue *qp) {
-
-  (void)qp;
-  USART1->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-static void notify2(GenericQueue *qp) {
-
-  (void)qp;
-  USART2->CR1 |= USART_CR1_TXEIE;
-}
-#endif
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
-/**
- * @brief   USART1 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(USART1_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD1);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
-/**
- * @brief   USART2 interrupt handler.
- *
- * @isr
- */
-CH_IRQ_HANDLER(USART2_IRQHandler) {
-
-  CH_IRQ_PROLOGUE();
-
-  serve_interrupt(&SD2);
-
-  CH_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level serial driver initialization.
- *
- * @notapi
- */
-void sd_lld_init(void) {
-
-#if STM32_SERIAL_USE_USART1
-  sdObjectInit(&SD1, NULL, notify1);
-  SD1.usart = USART1;
-#endif
-
-#if STM32_SERIAL_USE_USART2
-  sdObjectInit(&SD2, NULL, notify2);
-  SD2.usart = USART2;
-#endif
-}
-
-/**
- * @brief   Low level serial driver configuration and (re)start.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration.
- *                      If this parameter is set to @p NULL then a default
- *                      configuration is used.
- *
- * @notapi
- */
-void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
-
-  if (config == NULL)
-    config = &default_config;
-
-  if (sdp->state == SD_STOP) {
-#if STM32_SERIAL_USE_USART1
-    if (&SD1 == sdp) {
-      rccEnableUSART1(FALSE);
-      nvicEnableVector(USART1_IRQn,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));
-    }
-#endif
-#if STM32_SERIAL_USE_USART2
-    if (&SD2 == sdp) {
-      rccEnableUSART2(FALSE);
-      nvicEnableVector(USART2_IRQn,
-                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));
-    }
-#endif
-  }
-  usart_init(sdp, config);
-}
-
-/**
- * @brief   Low level serial driver stop.
- * @details De-initializes the USART, stops the associated clock, resets the
- *          interrupt vector.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- *
- * @notapi
- */
-void sd_lld_stop(SerialDriver *sdp) {
-
-  if (sdp->state == SD_READY) {
-    usart_deinit(sdp->usart);
-#if STM32_SERIAL_USE_USART1
-    if (&SD1 == sdp) {
-      rccDisableUSART1(FALSE);
-      nvicDisableVector(USART1_IRQn);
-      return;
-    }
-#endif
-#if STM32_SERIAL_USE_USART2
-    if (&SD2 == sdp) {
-      rccDisableUSART2(FALSE);
-      nvicDisableVector(USART2_IRQn);
-      return;
-    }
-#endif
-  }
-}
-
-#endif /* HAL_USE_SERIAL */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F0xx/serial_lld.h b/os/hal/platforms/STM32F0xx/serial_lld.h
deleted file mode 100644
index da41e66da..000000000
--- a/os/hal/platforms/STM32F0xx/serial_lld.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
-
-    This file is part of ChibiOS/RT.
-
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    STM32/serial_lld.h
- * @brief   STM32 low level serial driver header.
- *
- * @addtogroup SERIAL
- * @{
- */
-
-#ifndef _SERIAL_LLD_H_
-#define _SERIAL_LLD_H_
-
-#if HAL_USE_SERIAL || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   USART1 driver enable switch.
- * @details If set to @p TRUE the support for USART1 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_USART1             TRUE
-#endif
-
-/**
- * @brief   USART2 driver enable switch.
- * @details If set to @p TRUE the support for USART2 is included.
- * @note    The default is @p TRUE.
- */
-#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USE_USART2             TRUE
-#endif
-
-/**
- * @brief   USART1 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USART1_PRIORITY        3
-#endif
-
-/**
- * @brief   USART2 interrupt priority level setting.
- */
-#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USART2_PRIORITY        3
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1
-#error "USART1 not present in the selected device"
-#endif
-
-#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2
-#error "USART2 not present in the selected device"
-#endif
-
-#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2
-#error "SERIAL driver activated but no USART/UART peripheral assigned"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 Serial Driver configuration structure.
- * @details An instance of this structure must be passed to @p sdStart()
- *          in order to configure and start a serial driver operations.
- * @note    This structure content is architecture dependent, each driver
- *          implementation defines its own version and the custom static
- *          initializers.
- */
-typedef struct {
-  /**
-   * @brief Bit rate.
-   */
-  uint32_t                  sc_speed;
-  /**
-   * @brief Initialization value for the CR1 register.
-   */
-  uint16_t                  sc_cr1;
-  /**
-   * @brief Initialization value for the CR2 register.
-   */
-  uint16_t                  sc_cr2;
-  /**
-   * @brief Initialization value for the CR3 register.
-   */
-  uint16_t                  sc_cr3;
-} SerialConfig;
-
-/**
- * @brief   @p SerialDriver specific data.
- */
-#define _serial_driver_data                                                 \
-  _base_asynchronous_channel_data                                           \
-  /* Driver state.*/                                                        \
-  sdstate_t                 state;                                          \
-  /* Input queue.*/                                                         \
-  InputQueue                iqueue;                                         \
-  /* Output queue.*/                                                        \
-  OutputQueue               oqueue;                                         \
-  /* Input circular buffer.*/                                               \
-  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
-  /* Output circular buffer.*/                                              \
-  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
-  /* End of the mandatory fields.*/                                         \
-  /* Pointer to the USART registers block.*/                                \
-  USART_TypeDef             *usart;
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*
- * Extra USARTs definitions here (missing from the ST header file).
- */
-#define USART_CR2_STOP1_BITS    (0 << 12)   /**< @brief CR2 1 stop bit value.*/
-#define USART_CR2_STOP0P5_BITS  (1 << 12)   /**< @brief CR2 0.5 stop bit value.*/
-#define USART_CR2_STOP2_BITS    (2 << 12)   /**< @brief CR2 2 stop bit value.*/
-#define USART_CR2_STOP1P5_BITS  (3 << 12)   /**< @brief CR2 1.5 stop bit value.*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
-extern SerialDriver SD1;
-#endif
-#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
-extern SerialDriver SD2;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void sd_lld_init(void);
-  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
-  void sd_lld_stop(SerialDriver *sdp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_SERIAL */
-
-#endif /* _SERIAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.c b/os/hal/platforms/STM32F0xx/stm32_dma.c
new file mode 100644
index 000000000..f5191f954
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.c
@@ -0,0 +1,296 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F0xx/stm32_dma.c
+ * @brief   DMA helper driver code.
+ *
+ * @addtogroup STM32F0xx_DMA
+ * @details DMA sharing helper driver. In the STM32 the DMA streams are a
+ *          shared resource, this driver allows to allocate and free DMA
+ *          streams at runtime in order to allow all the other device
+ *          drivers to coordinate the access to the resource.
+ * @note    The DMA ISR handlers are all declared into this module because
+ *          sharing, the various device drivers can associate a callback to
+ *          ISRs when allocating streams.
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+/* The following macro is only defined if some driver requiring DMA services
+   has been enabled.*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/**
+ * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA1_STREAMS_MASK     0x0000007F
+
+/**
+ * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA2_STREAMS_MASK     0x00000F80
+
+/**
+ * @brief   Post-reset value of the stream CCR register.
+ */
+#define STM32_DMA_CCR_RESET_VALUE   0x00000000
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA streams descriptors.
+ * @details This table keeps the association between an unique stream
+ *          identifier and the involved physical registers.
+ * @note    Don't use this array directly, use the appropriate wrapper macros
+ *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
+ */
+const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
+  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
+  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_3_IRQn},
+  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel2_3_IRQn},
+  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_5_IRQn},
+  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel4_5_IRQn}
+};
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA ISR redirector type.
+ */
+typedef struct {
+  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
+  void                  *dma_param;     /**< @brief DMA callback parameter. */
+} dma_isr_redir_t;
+
+/**
+ * @brief   Mask of the allocated streams.
+ */
+static uint32_t dma_streams_mask;
+
+/**
+ * @brief   DMA IRQ redirectors.
+ */
+static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA1 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
+  uint32_t flags;
+
+  CH_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
+  if (dma_isr_redir[0].dma_func)
+    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
+
+  CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 streams 2 and 3 shared interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(DMA1_Ch2_3_IRQHandler) {
+  uint32_t flags;
+
+  CH_IRQ_PROLOGUE();
+
+  /* Check on channel 2.*/
+  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
+  if (flags & STM32_DMA_ISR_MASK) {
+    DMA1->IFCR = STM32_DMA_ISR_MASK << 4;
+    if (dma_isr_redir[1].dma_func)
+      dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
+  }
+
+  /* Check on channel 3.*/
+  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
+  if (flags & STM32_DMA_ISR_MASK) {
+    DMA1->IFCR = STM32_DMA_ISR_MASK << 8;
+    if (dma_isr_redir[2].dma_func)
+      dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
+  }
+
+  CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 streams 4 and 5 shared interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(DMA1_Ch4_5_IRQHandler) {
+  uint32_t flags;
+
+  CH_IRQ_PROLOGUE();
+
+  /* Check on channel 4.*/
+  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
+  if (flags & STM32_DMA_ISR_MASK) {
+    DMA1->IFCR = STM32_DMA_ISR_MASK << 12;
+    if (dma_isr_redir[3].dma_func)
+      dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
+  }
+
+  /* Check on channel 5.*/
+  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
+  if (flags & STM32_DMA_ISR_MASK) {
+    DMA1->IFCR = STM32_DMA_ISR_MASK << 16;
+    if (dma_isr_redir[4].dma_func)
+      dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
+  }
+
+  CH_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA helper initialization.
+ *
+ * @init
+ */
+void dmaInit(void) {
+  int i;
+
+  dma_streams_mask = 0;
+  for (i = 0; i < STM32_DMA_STREAMS; i++) {
+    _stm32_dma_streams[i].channel->CCR = 0;
+    dma_isr_redir[i].dma_func = NULL;
+  }
+  DMA1->IFCR = 0xFFFFFFFF;
+}
+
+/**
+ * @brief   Allocates a DMA stream.
+ * @details The stream is allocated and, if required, the DMA clock enabled.
+ *          The function also enables the IRQ vector associated to the stream
+ *          and initializes its priority.
+ * @pre     The stream must not be already in use or an error is returned.
+ * @post    The stream is allocated and the default ISR handler redirected
+ *          to the specified function.
+ * @post    The stream ISR vector is enabled and its priority configured.
+ * @post    The stream must be freed using @p dmaStreamRelease() before it can
+ *          be reused with another peripheral.
+ * @post    The stream is in its post-reset state.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] priority  IRQ priority mask for the DMA stream
+ * @param[in] func      handling function pointer, can be @p NULL
+ * @param[in] param     a parameter to be passed to the handling function
+ * @return              The operation status.
+ * @retval FALSE        no error, stream taken.
+ * @retval TRUE         error, stream already taken.
+ *
+ * @special
+ */
+bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                         uint32_t priority,
+                         stm32_dmaisr_t func,
+                         void *param) {
+
+  chDbgCheck(dmastp != NULL, "dmaAllocate");
+
+  /* Checks if the stream is already taken.*/
+  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
+    return TRUE;
+
+  /* Marks the stream as allocated.*/
+  dma_isr_redir[dmastp->selfindex].dma_func  = func;
+  dma_isr_redir[dmastp->selfindex].dma_param = param;
+  dma_streams_mask |= (1 << dmastp->selfindex);
+
+  /* Enabling DMA clocks required by the current streams set.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
+    rccEnableDMA1(FALSE);
+
+  /* Putting the stream in a safe state.*/
+  dmaStreamDisable(dmastp);
+  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
+
+  /* Enables the associated IRQ vector if a callback is defined.*/
+  if (func != NULL)
+    nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
+
+  return FALSE;
+}
+
+/**
+ * @brief   Releases a DMA stream.
+ * @details The stream is freed and, if required, the DMA clock disabled.
+ *          Trying to release a unallocated stream is an illegal operation
+ *          and is trapped if assertions are enabled.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    The stream is again available.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
+
+  chDbgCheck(dmastp != NULL, "dmaRelease");
+
+  /* Check if the streams is not taken.*/
+  chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
+              "dmaRelease(), #1", "not allocated");
+
+  /* Disables the associated IRQ vector.*/
+  nvicDisableVector(dmastp->vector);
+
+  /* Marks the stream as not allocated.*/
+  dma_streams_mask &= ~(1 << dmastp->selfindex);
+
+  /* Shutting down clocks that are no more required, if any.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
+    rccDisableDMA1(FALSE);
+}
+
+#endif /* STM32_DMA_REQUIRED */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.h b/os/hal/platforms/STM32F0xx/stm32_dma.h
new file mode 100644
index 000000000..1677bc285
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.h
@@ -0,0 +1,395 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F0xx/stm32_dma.h
+ * @brief   DMA helper driver header.
+ * @note    This file requires definitions from the ST header file stm32l1xx.h.
+ * @note    This driver uses the new naming convention used for the STM32F2xx
+ *          so the "DMA channels" are referred as "DMA streams".
+ *
+ * @addtogroup STM32F0xx_DMA
+ * @{
+ */
+
+#ifndef _STM32_DMA_H_
+#define _STM32_DMA_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Total number of DMA streams.
+ * @note    This is the total number of streams among all the DMA units.
+ */
+#define STM32_DMA_STREAMS           5
+
+/**
+ * @brief   Mask of the ISR bits passed to the DMA callback functions.
+ */
+#define STM32_DMA_ISR_MASK          0x0F
+
+/**
+ * @brief   Returns the channel associated to the specified stream.
+ *
+ * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
+ * @param[in] c         a stream/channel association word, one channel per
+ *                      nibble, not associated channels must be set to 0xF
+ * @return              Always zero, in this platform there is no dynamic
+ *                      association between streams and channels.
+ */
+#define STM32_DMA_GETCHANNEL(n, c)  0
+
+/**
+ * @brief   Checks if a DMA priority is within the valid range.
+ * @param[in] prio      DMA priority
+ *
+ * @retval              The check result.
+ * @retval FALSE        invalid DMA priority.
+ * @retval TRUE         correct DMA priority.
+ */
+#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
+
+/**
+ * @brief   Returns an unique numeric identifier for a DMA stream.
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              An unique numeric stream identifier.
+ */
+#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1)
+
+/**
+ * @brief   Returns a DMA stream identifier mask.
+ *
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              A DMA stream identifier mask.
+ */
+#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
+  (1 << STM32_DMA_STREAM_ID(dma, stream))
+
+/**
+ * @brief   Checks if a DMA stream unique identifier belongs to a mask.
+ * @param[in] id        the stream numeric identifier
+ * @param[in] mask      the stream numeric identifiers mask
+ *
+ * @retval              The check result.
+ * @retval FALSE        id does not belong to the mask.
+ * @retval TRUE         id belongs to the mask.
+ */
+#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
+
+/**
+ * @name    DMA streams identifiers
+ * @{
+ */
+/**
+ * @brief   Returns a pointer to a stm32_dma_stream_t structure.
+ *
+ * @param[in] id        the stream numeric identifier
+ * @return              A pointer to the stm32_dma_stream_t constant structure
+ *                      associated to the DMA stream.
+ */
+#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
+
+#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
+#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
+#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
+#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
+#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
+/** @} */
+
+/**
+ * @name    CR register constants common to all DMA types
+ * @{
+ */
+#define STM32_DMA_CR_EN             DMA_CCR_EN
+#define STM32_DMA_CR_TEIE           DMA_CCR_TEIE
+#define STM32_DMA_CR_HTIE           DMA_CCR_HTIE
+#define STM32_DMA_CR_TCIE           DMA_CCR_TCIE
+#define STM32_DMA_CR_DIR_MASK       (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
+#define STM32_DMA_CR_DIR_P2M        0
+#define STM32_DMA_CR_DIR_M2P        DMA_CCR_DIR
+#define STM32_DMA_CR_DIR_M2M        DMA_CCR_MEM2MEM
+#define STM32_DMA_CR_CIRC           DMA_CCR_CIRC
+#define STM32_DMA_CR_PINC           DMA_CCR_PINC
+#define STM32_DMA_CR_MINC           DMA_CCR_MINC
+#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR_PSIZE
+#define STM32_DMA_CR_PSIZE_BYTE     0
+#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR_PSIZE_0
+#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR_PSIZE_1
+#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR_MSIZE
+#define STM32_DMA_CR_MSIZE_BYTE     0
+#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR_MSIZE_0
+#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR_MSIZE_1
+#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_MSIZE_MASK |              \
+                                     STM32_DMA_CR_MSIZE_MASK)
+#define STM32_DMA_CR_PL_MASK        DMA_CCR_PL
+#define STM32_DMA_CR_PL(n)          ((n) << 12)
+/** @} */
+
+/**
+ * @name    CR register constants only found in enhanced DMA
+ * @{
+ */
+#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
+/** @} */
+
+/**
+ * @name    Status flags passed to the ISR callbacks
+ * @{
+ */
+#define STM32_DMA_ISR_FEIF          0
+#define STM32_DMA_ISR_DMEIF         0
+#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
+#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
+#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA stream descriptor structure.
+ */
+typedef struct {
+  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
+  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
+  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
+                                             register.                      */
+  uint8_t               selfindex;      /**< @brief Index to self in array. */
+  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
+} stm32_dma_stream_t;
+
+/**
+ * @brief   STM32 DMA ISR function type.
+ *
+ * @param[in] p         parameter for the registered function
+ * @param[in] flags     pre-shifted content of the ISR register, the bits
+ *                      are aligned to bit zero
+ */
+typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Associates a peripheral data register to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CPAR register
+ *
+ * @special
+ */
+#define dmaStreamSetPeripheral(dmastp, addr) {                              \
+  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Associates a memory destination to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CMAR register
+ *
+ * @special
+ */
+#define dmaStreamSetMemory0(dmastp, addr) {                                 \
+  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Sets the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] size      value to be written in the CNDTR register
+ *
+ * @special
+ */
+#define dmaStreamSetTransactionSize(dmastp, size) {                         \
+  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
+}
+
+/**
+ * @brief   Returns the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @return              The number of transfers to be performed.
+ *
+ * @special
+ */
+#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
+
+/**
+ * @brief   Programs the stream mode settings.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register
+ *
+ * @special
+ */
+#define dmaStreamSetMode(dmastp, mode) {                                    \
+  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
+}
+
+/**
+ * @brief   DMA stream enable.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamEnable(dmastp) {                                           \
+  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
+}
+
+/**
+ * @brief   DMA stream disable.
+ * @details The function disables the specified stream and then clears any
+ *          pending interrupt.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamDisable(dmastp) {                                          \
+  (dmastp)->channel->CCR &= ~STM32_DMA_CR_EN;                               \
+  dmaStreamClearInterrupt(dmastp);                                          \
+}
+
+/**
+ * @brief   DMA stream interrupt sources clear.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamClearInterrupt(dmastp) {                                   \
+  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
+}
+
+/**
+ * @brief   Starts a memory to memory operation using the specified stream.
+ * @note    The default transfer data mode is "byte to byte" but it can be
+ *          changed by specifying extra options in the @p mode parameter.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register, this value
+ *                      is implicitly ORed with:
+ *                      - @p STM32_DMA_CR_MINC
+ *                      - @p STM32_DMA_CR_PINC
+ *                      - @p STM32_DMA_CR_DIR_M2M
+ *                      - @p STM32_DMA_CR_EN
+ *                      .
+ * @param[in] src       source address
+ * @param[in] dst       destination address
+ * @param[in] n         number of data units to copy
+ */
+#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
+  dmaStreamSetPeripheral(dmastp, src);                                      \
+  dmaStreamSetMemory0(dmastp, dst);                                         \
+  dmaStreamSetTransactionSize(dmastp, n);                                   \
+  dmaStreamSetMode(dmastp, (mode) |                                         \
+                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
+                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
+}
+
+/**
+ * @brief   Polled wait for DMA transfer end.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ */
+#define dmaWaitCompletion(dmastp) {                                         \
+  while ((dmastp)->channel->CNDTR > 0)                                      \
+    ;                                                                       \
+  dmaStreamDisable(dmastp);                                                 \
+}
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void dmaInit(void);
+  bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                           uint32_t priority,
+                           stm32_dmaisr_t func,
+                           void *param);
+  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_DMA_H_ */
+
+/** @} */
-- 
cgit v1.2.3


From 5a7b2c4fba9b17cd17c9006704d52cecc7fef169 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 24 May 2012 18:47:20 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4233
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.h | 3 ---
 1 file changed, 3 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 30a46fa79..f5c32a82d 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -223,18 +223,15 @@
  */
 /* ADC attributes.*/
 #define STM32_HAS_ADC1          TRUE
-#define STM32_ADC1_DMA_DEFAULT  STM32_DMA_STREAM_ID(1, 0)
 #define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 0) |            \
                                  STM32_DMA_STREAM_ID_MSK(1, 1))
 #define STM32_ADC1_DMA_CHN      0x00000000
 
 #define STM32_HAS_ADC2          FALSE
-#define STM32_ADC2_DMA_DEFAULT  0
 #define STM32_ADC2_DMA_MSK      0x00000000
 #define STM32_ADC2_DMA_CHN      0x00000000
 
 #define STM32_HAS_ADC3          FALSE
-#define STM32_ADC3_DMA_DEFAULT  0
 #define STM32_ADC3_DMA_MSK      0x00000000
 #define STM32_ADC3_DMA_CHN      0x00000000
 
-- 
cgit v1.2.3


From 512b78de728dfa1fe6bacadc525c8edc1dfdb041 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 26 May 2012 11:07:27 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4234
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/adc_lld.c   | 292 ++++++++++++++++++++++++++++++++
 os/hal/platforms/STM32F0xx/adc_lld.h   | 293 +++++++++++++++++++++++++++++++++
 os/hal/platforms/STM32F0xx/platform.mk |   1 +
 3 files changed, 586 insertions(+)
 create mode 100644 os/hal/platforms/STM32F0xx/adc_lld.c
 create mode 100644 os/hal/platforms/STM32F0xx/adc_lld.h

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
new file mode 100644
index 000000000..751f15afd
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -0,0 +1,292 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F0xx/adc_lld.c
+ * @brief   STM32F0xx ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Stops an ongoing conversion, if any.
+ *
+ * @param[in] adc       pointer to the ADC registers block
+ */
+static void adc_lld_stop_adc(ADC_TypeDef *adc) {
+
+  if (adc->CR & ADC_CR_ADSTART) {
+    adc->CR |= ADC_CR_ADSTP;
+    while (adc->CR & ADC_CR_ADSTP)
+      ;
+  }
+}
+
+/**
+ * @brief   ADC DMA ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    /* DMA, this could help only if the DMA tries to access an unmapped
+       address space or violates alignment rules.*/
+    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+  }
+  else {
+    /* It is possible that the conversion group has already be reset by the
+       ADC error handler, in this case this interrupt is spurious.*/
+    if (adcp->grpp != NULL) {
+      if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+        /* Half transfer processing.*/
+        _adc_isr_half_code(adcp);
+      }
+      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+        /* Transfer complete processing.*/
+        _adc_isr_full_code(adcp);
+      }
+    }
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+/**
+ * @brief   ADC interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(ADC1_IRQHandler) {
+  uint32_t isr;
+
+  CH_IRQ_PROLOGUE();
+
+  isr = ADC1->ISR;
+  ADC1->ISR = isr;
+  /* Note, an overflow may occur after the conversion ended before the driver
+     is able to stop the ADC, this is why the DMA channel is checked too.*/
+  if ((isr & ADC_ISR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
+    /* ADC overflow condition, this could happen only if the DMA is unable
+       to read data fast enough.*/
+    if (ADCD1.grpp != NULL)
+      _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
+  }
+  /* TODO: Add here analog watchdog handling.*/
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD1);
+  ADCD1.adc = ADC1;
+  ADCD1.dmastp  = STM32_DMA1_STREAM1;
+  ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE        |
+                  STM32_DMA_CR_EN;
+#endif
+
+  /* The shared vector is initialized on driver initialization and never
+     disabled.*/
+  nvicEnableVector(ADC1_COMP_IRQn,
+                   CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
+}
+
+/**
+ * @brief   Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+  /* If in stopped state then enables the ADC and DMA clocks.*/
+  if (adcp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp) {
+      bool_t b;
+      b = dmaStreamAllocate(adcp->dmastp,
+                            STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
+                            (void *)adcp);
+      chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
+      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
+      rccEnableADC1(FALSE);
+    }
+#endif /* STM32_ADC_USE_ADC1 */
+
+    /* ADC initial setup, starting the analog part here in order to reduce
+       the latency when starting a conversion.*/
+    adcp->adc->CR = ADC_CR_ADEN;
+    while (!(adcp->adc->ISR & ADC_ISR_ADRDY))
+      ;
+  }
+}
+
+/**
+ * @brief   Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+  /* If in ready state then disables the ADC clock and analog part.*/
+  if (adcp->state == ADC_READY) {
+
+    dmaStreamRelease(adcp->dmastp);
+
+    /* Disabling ADC.*/
+    if (adcp->adc->CR & ADC_CR_ADEN) {
+      adc_lld_stop_adc(adcp->adc);
+      adcp->adc->CR |= ADC_CR_ADDIS;
+      while (adcp->adc->CR & ADC_CR_ADDIS)
+        ;
+    }
+
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp)
+      rccDisableADC1(FALSE);
+#endif
+  }
+}
+
+/**
+ * @brief   Starts an ADC conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+  uint32_t mode;
+  const ADCConversionGroup *grpp = adcp->grpp;
+
+  /* DMA setup.*/
+  mode = adcp->dmamode;
+  if (grpp->circular) {
+    mode |= STM32_DMA_CR_CIRC;
+  }
+  if (adcp->depth > 1) {
+    /* If the buffer depth is greater than one then the half transfer interrupt
+       interrupt is enabled in order to allows streaming processing.*/
+    mode |= STM32_DMA_CR_HTIE;
+  }
+  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
+  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+                                            (uint32_t)adcp->depth);
+  dmaStreamSetMode(adcp->dmastp, mode);
+
+  /* ADC setup.*/
+  adcp->adc->ISR    = adcp->adc->ISR;
+  adcp->adc->IER    = ADC_IER_OVRIE;
+  adcp->adc->SMPR   = grpp->smpr;
+  adcp->adc->CHSELR = grpp->chselr;
+
+  /* ADC configuration and start.*/
+  adcp->adc->CFGR1  = grpp->cfgr1 | ADC_CFGR1_CONT  | ADC_CFGR1_DMACFG |
+                                    ADC_CFGR1_DMAEN;
+  adcp->adc->CR    |= ADC_CR_ADSTART;
+}
+
+/**
+ * @brief   Stops an ongoing conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+  dmaStreamDisable(adcp->dmastp);
+  adc_lld_stop_adc(adcp->adc);
+}
+
+/**
+ * @brief   Enables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ *          temperature sensor and internal reference voltage.
+ * @note    This is an STM32-only functionality.
+ */
+void adcSTM32EnableTSVREFE(void) {
+
+  ADC->CCR |= ADC_CCR_VREFEN;
+}
+
+/**
+ * @brief   Disables the TSVREFE bit.
+ * @details The TSVREFE bit is required in order to sample the internal
+ *          temperature sensor and internal reference voltage.
+ * @note    This is an STM32-only functionality.
+ */
+void adcSTM32DisableTSVREFE(void) {
+
+  ADC->CCR &= ~ADC_CCR_VREFEN;
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h
new file mode 100644
index 000000000..3be5a053c
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/adc_lld.h
@@ -0,0 +1,293 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F0xx/adc_lld.h
+ * @brief   STM32F0xx ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef _ADC_LLD_H_
+#define _ADC_LLD_H_
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Sampling rates
+ * @{
+ */
+#define ADC_SAMPLE_1P5          0   /**< @brief 14 cycles conversion time   */
+#define ADC_SAMPLE_7P5          1   /**< @brief 21 cycles conversion time.  */
+#define ADC_SAMPLE_13P5         2   /**< @brief 28 cycles conversion time.  */
+#define ADC_SAMPLE_28P5         3   /**< @brief 41 cycles conversion time.  */
+#define ADC_SAMPLE_41P5         4   /**< @brief 54 cycles conversion time.  */
+#define ADC_SAMPLE_55P5         5   /**< @brief 68 cycles conversion time.  */
+#define ADC_SAMPLE_71P5         6   /**< @brief 84 cycles conversion time.  */
+#define ADC_SAMPLE_239P5        7   /**< @brief 252 cycles conversion time. */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC1                  TRUE
+#endif
+
+/**
+ * @brief   ADC1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_PRIORITY         2
+#endif
+
+/**
+ * @brief   ADC interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_IRQ_PRIORITY              2
+#endif
+
+/**
+ * @brief   ADC1 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     2
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+#if !STM32_ADC_USE_ADC1
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   ADC sample data type.
+ */
+typedef uint16_t adcsample_t;
+
+/**
+ * @brief   Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief   Possible ADC failure causes.
+ * @note    Error codes are architecture dependent and should not relied
+ *          upon.
+ */
+typedef enum {
+  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
+  ADC_ERR_OVERFLOW = 1                      /**< ADC overflow condition.    */
+} adcerror_t;
+
+/**
+ * @brief   Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief   ADC notification callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] buffer    pointer to the most recent samples data
+ * @param[in] n         number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief   ADC error callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief   Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ *          operation.
+ * @note    The use of this configuration structure requires knowledge of
+ *          STM32 ADC cell registers interface, please refer to the STM32
+ *          reference manual for details.
+ */
+typedef struct {
+  /**
+   * @brief   Enables the circular buffer mode for the group.
+   */
+  bool_t                    circular;
+  /**
+   * @brief   Number of the analog channels belonging to the conversion group.
+   */
+  adc_channels_num_t        num_channels;
+  /**
+   * @brief   Callback function associated to the group or @p NULL.
+   */
+  adccallback_t             end_cb;
+  /**
+   * @brief   Error callback or @p NULL.
+   */
+  adcerrorcallback_t        error_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   ADC CFGR1 register initialization data.
+   */
+  uint32_t                  cfgr1;
+  /**
+   * @brief   ADC SMPR register initialization data.
+   */
+  uint32_t                  smpr;
+  /**
+   * @brief   ADC CHSELR register initialization data.
+   * @details The number of bits at logic level one in this register must
+   *          be equal to the number in the @p num_channels field.
+   */
+  uint32_t                  chselr;
+} ADCConversionGroup;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  uint32_t                  dummy;
+} ADCConfig;
+
+/**
+ * @brief   Structure representing an ADC driver.
+ */
+struct ADCDriver {
+  /**
+   * @brief Driver state.
+   */
+  adcstate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const ADCConfig           *config;
+  /**
+   * @brief Current samples buffer pointer or @p NULL.
+   */
+  adcsample_t               *samples;
+  /**
+   * @brief Current samples buffer depth or @p 0.
+   */
+  size_t                    depth;
+  /**
+   * @brief Current conversion group pointer or @p NULL.
+   */
+  const ADCConversionGroup  *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief Waiting thread.
+   */
+  Thread                    *thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+#if CH_USE_MUTEXES || defined(__DOXYGEN__)
+  /**
+   * @brief Mutex protecting the peripheral.
+   */
+  Mutex                     mutex;
+#elif CH_USE_SEMAPHORES
+  Semaphore                 semaphore;
+#endif
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+  ADC_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the ADCx registers block.
+   */
+  ADC_TypeDef               *adc;
+  /**
+   * @brief Pointer to associated SMA channel.
+   */
+  const stm32_dma_stream_t  *dmastp;
+  /**
+   * @brief DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void adc_lld_init(void);
+  void adc_lld_start(ADCDriver *adcp);
+  void adc_lld_stop(ADCDriver *adcp);
+  void adc_lld_start_conversion(ADCDriver *adcp);
+  void adc_lld_stop_conversion(ADCDriver *adcp);
+  void adcSTM32EnableTSVREFE(void);
+  void adcSTM32DisableTSVREFE(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* _ADC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index 9d13d064a..9c0e709df 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -1,5 +1,6 @@
 # List of all the STM32F1xx platform files.
 PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
+              ${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c	\
-- 
cgit v1.2.3


From 6e2f377dd5b17c3ab2836a5ae5406676275f9bb5 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 26 May 2012 11:24:52 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4235
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/adc_lld.c | 32 ++++++++++----------------------
 os/hal/platforms/STM32F0xx/adc_lld.h | 10 ++++++++--
 2 files changed, 18 insertions(+), 24 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
index 751f15afd..95e0ddf77 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -174,6 +174,16 @@ void adc_lld_start(ADCDriver *adcp) {
       chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
       dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
       rccEnableADC1(FALSE);
+#if STM32_ADCSW == STM32_ADCSW_HSI14
+      /* Clock from HSI14, no need for jitter removal.*/
+      ADC1->CFGR2 = 0x00001000;
+#else
+#if STM32_ADCPRE == STM32_ADCPRE_DIV2
+      ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV2;
+#else
+      ADC1->CFGR2 = 0x00001000 | ADC_CFGR2_JITOFFDIV4;
+#endif
+#endif
     }
 #endif /* STM32_ADC_USE_ADC1 */
 
@@ -265,28 +275,6 @@ void adc_lld_stop_conversion(ADCDriver *adcp) {
   adc_lld_stop_adc(adcp->adc);
 }
 
-/**
- * @brief   Enables the TSVREFE bit.
- * @details The TSVREFE bit is required in order to sample the internal
- *          temperature sensor and internal reference voltage.
- * @note    This is an STM32-only functionality.
- */
-void adcSTM32EnableTSVREFE(void) {
-
-  ADC->CCR |= ADC_CCR_VREFEN;
-}
-
-/**
- * @brief   Disables the TSVREFE bit.
- * @details The TSVREFE bit is required in order to sample the internal
- *          temperature sensor and internal reference voltage.
- * @note    This is an STM32-only functionality.
- */
-void adcSTM32DisableTSVREFE(void) {
-
-  ADC->CCR &= ~ADC_CCR_VREFEN;
-}
-
 #endif /* HAL_USE_ADC */
 
 /** @} */
diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h
index 3be5a053c..31029f31c 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.h
+++ b/os/hal/platforms/STM32F0xx/adc_lld.h
@@ -264,6 +264,14 @@ struct ADCDriver {
 /* Driver macros.                                                            */
 /*===========================================================================*/
 
+/**
+ * @brief   Changes the value of the ADC CCR register.
+ * @details Use this function in order to enable or disable the internal
+ *          analog sources. See the documentation in the STM32F0xx Reference
+ *          Manual.
+ */
+#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr))
+
 /*===========================================================================*/
 /* External declarations.                                                    */
 /*===========================================================================*/
@@ -280,8 +288,6 @@ extern "C" {
   void adc_lld_stop(ADCDriver *adcp);
   void adc_lld_start_conversion(ADCDriver *adcp);
   void adc_lld_stop_conversion(ADCDriver *adcp);
-  void adcSTM32EnableTSVREFE(void);
-  void adcSTM32DisableTSVREFE(void);
 #ifdef __cplusplus
 }
 #endif
-- 
cgit v1.2.3


From 5c1a0c2b8a9b4164b52cf5d33fca16fd9c61c462 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 26 May 2012 12:26:52 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4236
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/stm32_dma.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.h b/os/hal/platforms/STM32F0xx/stm32_dma.h
index 1677bc285..b1e06e6b5 100644
--- a/os/hal/platforms/STM32F0xx/stm32_dma.h
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.h
@@ -21,7 +21,7 @@
 /**
  * @file    STM32F0xx/stm32_dma.h
  * @brief   DMA helper driver header.
- * @note    This file requires definitions from the ST header file stm32l1xx.h.
+ * @note    This file requires definitions from the ST header file stm32f0xx.h.
  * @note    This driver uses the new naming convention used for the STM32F2xx
  *          so the "DMA channels" are referred as "DMA streams".
  *
-- 
cgit v1.2.3


From 58f95054b30907efe3135cbe5022c24c31efbe2d Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 26 May 2012 12:56:08 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4237
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/adc_lld.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h
index 31029f31c..eeeda1979 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.h
+++ b/os/hal/platforms/STM32F0xx/adc_lld.h
@@ -101,6 +101,21 @@
 #error "ADC driver activated but no ADC peripheral assigned"
 #endif
 
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC1"
+#endif
+
 #if !defined(STM32_DMA_REQUIRED)
 #define STM32_DMA_REQUIRED
 #endif
-- 
cgit v1.2.3


From 6c6bc48fd6ce57afebf20a4c513770af15100c84 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 26 May 2012 13:11:31 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4238
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/adc_lld.c | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
index 95e0ddf77..51905c3d4 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -151,6 +151,14 @@ void adc_lld_init(void) {
      disabled.*/
   nvicEnableVector(ADC1_COMP_IRQn,
                    CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));
+
+  /* Calibration procedure.*/
+  rccEnableADC1(FALSE);
+  chDbgAssert(ADC1->CR == 0, "adc_lld_init(), #1", "invalid register state");
+  ADC1->CR |= ADC_CR_ADCAL;
+  while (ADC1->CR & ADC_CR_ADCAL)
+    ;
+  rccDisableADC1(FALSE);
 }
 
 /**
-- 
cgit v1.2.3


From 2b01d72e42576594924aa12fe50571cd56cafbb5 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 27 May 2012 13:42:33 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4242
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/adc_lld.c |  2 +-
 os/hal/platforms/STM32F0xx/adc_lld.h | 26 ++++++++++++++++++--------
 2 files changed, 19 insertions(+), 9 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
index 51905c3d4..af03bd058 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -102,7 +102,7 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
  *
  * @isr
  */
-CH_IRQ_HANDLER(ADC1_IRQHandler) {
+CH_IRQ_HANDLER(ADC1_COMP_IRQHandler) {
   uint32_t isr;
 
   CH_IRQ_PROLOGUE();
diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h
index eeeda1979..dce0d7d1a 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.h
+++ b/os/hal/platforms/STM32F0xx/adc_lld.h
@@ -39,14 +39,24 @@
  * @name    Sampling rates
  * @{
  */
-#define ADC_SAMPLE_1P5          0   /**< @brief 14 cycles conversion time   */
-#define ADC_SAMPLE_7P5          1   /**< @brief 21 cycles conversion time.  */
-#define ADC_SAMPLE_13P5         2   /**< @brief 28 cycles conversion time.  */
-#define ADC_SAMPLE_28P5         3   /**< @brief 41 cycles conversion time.  */
-#define ADC_SAMPLE_41P5         4   /**< @brief 54 cycles conversion time.  */
-#define ADC_SAMPLE_55P5         5   /**< @brief 68 cycles conversion time.  */
-#define ADC_SAMPLE_71P5         6   /**< @brief 84 cycles conversion time.  */
-#define ADC_SAMPLE_239P5        7   /**< @brief 252 cycles conversion time. */
+#define ADC_SMPR_SMP_1P5        0   /**< @brief 14 cycles conversion time   */
+#define ADC_SMPR_SMP_7P5        1   /**< @brief 21 cycles conversion time.  */
+#define ADC_SMPR_SMP_13P5       2   /**< @brief 28 cycles conversion time.  */
+#define ADC_SMPR_SMP_28P5       3   /**< @brief 41 cycles conversion time.  */
+#define ADC_SMPR_SMP_41P5       4   /**< @brief 54 cycles conversion time.  */
+#define ADC_SMPR_SMP_55P5       5   /**< @brief 68 cycles conversion time.  */
+#define ADC_SMPR_SMP_71P5       6   /**< @brief 84 cycles conversion time.  */
+#define ADC_SMPR_SMP_239P5      7   /**< @brief 252 cycles conversion time. */
+/** @} */
+
+/**
+ * @name    Resolution
+ * @{
+ */
+#define ADC_CFGR1_RES_12BIT     (0 << 3)
+#define ADC_CFGR1_RES_10BIT     (1 << 3)
+#define ADC_CFGR1_RES_8BIT      (2 << 3)
+#define ADC_CFGR1_RES_6BIT      (3 << 3)
 /** @} */
 
 /*===========================================================================*/
-- 
cgit v1.2.3


From 90969496d306b28d0869b8a9cc374295c6e55bb3 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 28 May 2012 19:46:14 +0000
Subject: Analog watchdog support for F0 ADC driver (experimental).

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4245 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/adc_lld.c | 28 +++++++++++++++++++---------
 os/hal/platforms/STM32F0xx/adc_lld.h | 15 ++++++++++++++-
 2 files changed, 33 insertions(+), 10 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
index af03bd058..7f8414743 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -109,15 +109,23 @@ CH_IRQ_HANDLER(ADC1_COMP_IRQHandler) {
 
   isr = ADC1->ISR;
   ADC1->ISR = isr;
-  /* Note, an overflow may occur after the conversion ended before the driver
-     is able to stop the ADC, this is why the DMA channel is checked too.*/
-  if ((isr & ADC_ISR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
-    /* ADC overflow condition, this could happen only if the DMA is unable
-       to read data fast enough.*/
-    if (ADCD1.grpp != NULL)
+
+  /* It could be a spurious interrupt caused by overflows after DMA disabling,
+     just ignore it in this case.*/
+  if (ADCD1.grpp != NULL) {
+    /* Note, an overflow may occur after the conversion ended before the driver
+       is able to stop the ADC, this is why the DMA channel is checked too.*/
+    if ((isr & ADC_ISR_OVR) &&
+        (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
+      /* ADC overflow condition, this could happen only if the DMA is unable
+         to read data fast enough.*/
       _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
+    }
+    if (isr & ADC_ISR_AWD) {
+      /* Analog watchdog error.*/
+      _adc_isr_error_code(&ADCD1, ADC_ERR_AWD);
+    }
   }
-  /* TODO: Add here analog watchdog handling.*/
 
   CH_IRQ_EPILOGUE();
 }
@@ -258,9 +266,11 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
                                             (uint32_t)adcp->depth);
   dmaStreamSetMode(adcp->dmastp, mode);
 
-  /* ADC setup.*/
+  /* ADC setup, if it is defined a callback for the analog watch dog then it
+     is enabled.*/
   adcp->adc->ISR    = adcp->adc->ISR;
-  adcp->adc->IER    = ADC_IER_OVRIE;
+  adcp->adc->IER    = ADC_IER_OVRIE | ADC_IER_AWDIE;
+  adcp->adc->TR     = grpp->tr;
   adcp->adc->SMPR   = grpp->smpr;
   adcp->adc->CHSELR = grpp->chselr;
 
diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h
index dce0d7d1a..a0d823a8b 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.h
+++ b/os/hal/platforms/STM32F0xx/adc_lld.h
@@ -59,6 +59,13 @@
 #define ADC_CFGR1_RES_6BIT      (3 << 3)
 /** @} */
 
+/**
+ * @name    Threashold register initializer
+ * @{
+ */
+#define ADC_TR(low, high)       (((uint32_t)(high) << 16) | (uint32_t)(low))
+/** @} */
+
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
@@ -151,7 +158,8 @@ typedef uint16_t adc_channels_num_t;
  */
 typedef enum {
   ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
-  ADC_ERR_OVERFLOW = 1                      /**< ADC overflow condition.    */
+  ADC_ERR_OVERFLOW = 1,                     /**< ADC overflow condition.    */
+  ADC_ERR_AWD = 2                           /**< Analog watchdog triggered. */
 } adcerror_t;
 
 /**
@@ -174,6 +182,7 @@ typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
  *
  * @param[in] adcp      pointer to the @p ADCDriver object triggering the
  *                      callback
+ * @param[in] err       ADC error code
  */
 typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
 
@@ -207,6 +216,10 @@ typedef struct {
    * @brief   ADC CFGR1 register initialization data.
    */
   uint32_t                  cfgr1;
+  /**
+   * @brief   ADC TR register initialization data.
+   */
+  uint32_t                  tr;
   /**
    * @brief   ADC SMPR register initialization data.
    */
-- 
cgit v1.2.3


From 3626647d7b924ca07df4197f9cde4a7965b8cbdf Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 18 Jun 2012 08:52:26 +0000
Subject: Fixed bugs 3534767, 3534819, 3535887 and 3535938.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4293 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/adc_lld.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
index 7f8414743..dcc7c64f0 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -151,8 +151,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DIR_P2M |
                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE        |
-                  STM32_DMA_CR_EN;
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
 #endif
 
   /* The shared vector is initialized on driver initialization and never
@@ -265,6 +264,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
   dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
                                             (uint32_t)adcp->depth);
   dmaStreamSetMode(adcp->dmastp, mode);
+  dmaStreamEnable(adcp->dmastp);
 
   /* ADC setup, if it is defined a callback for the analog watch dog then it
      is enabled.*/
-- 
cgit v1.2.3


From de6bbbb9eff7592723d401c6340b9e4c78b24953 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 19 Jun 2012 16:47:09 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4307
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index f5c32a82d..93403c91f 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -238,6 +238,7 @@
 /* CAN attributes.*/
 #define STM32_HAS_CAN1          FALSE
 #define STM32_HAS_CAN2          FALSE
+#define STM32_CAN_MAX_FILTERS   0
 
 /* DAC attributes.*/
 #define STM32_HAS_DAC           TRUE
-- 
cgit v1.2.3


From 43011f1886d70446f3f48f79cb99be2a07b6d33f Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 21 Jun 2012 16:25:11 +0000
Subject: STM32 support enhancements, some other fixes.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4313 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/ext_lld_isr.c | 207 ++++++++++++++
 os/hal/platforms/STM32F0xx/ext_lld_isr.h | 111 ++++++++
 os/hal/platforms/STM32F0xx/hal_lld.h     |   3 +-
 os/hal/platforms/STM32F0xx/platform.mk   |  17 +-
 os/hal/platforms/STM32F0xx/stm32_isr.h   |  73 +++++
 os/hal/platforms/STM32F0xx/stm32f0xx.h   | 454 +++++++++++++++----------------
 6 files changed, 629 insertions(+), 236 deletions(-)
 create mode 100644 os/hal/platforms/STM32F0xx/ext_lld_isr.c
 create mode 100644 os/hal/platforms/STM32F0xx/ext_lld_isr.h
 create mode 100644 os/hal/platforms/STM32F0xx/stm32_isr.h

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.c b/os/hal/platforms/STM32F0xx/ext_lld_isr.c
new file mode 100644
index 000000000..acfc42024
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/ext_lld_isr.c
@@ -0,0 +1,207 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F0xx/ext_lld_isr.c
+ * @brief   STM32F0xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(EXTI0_1_IRQHandler) {
+  uint32_t pr;
+
+  CH_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 0) | (1 << 1));
+  EXTI->PR = pr;
+  if (pr & (1 << 0))
+    EXTD1.config->channels[0].cb(&EXTD1, 0);
+  if (pr & (1 << 1))
+    EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+  CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(EXTI2_3_IRQHandler) {
+  uint32_t pr;
+
+  CH_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((2 << 0) | (3 << 1));
+  EXTI->PR = pr;
+  if (pr & (1 << 2))
+    EXTD1.config->channels[2].cb(&EXTD1, 2);
+  if (pr & (1 << 3))
+    EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+  CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[4]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
+  uint32_t pr;
+
+  CH_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 4)  | (1 << 5)  | (1 << 6)  | (1 << 7)  | (1 << 8)  |
+                   (1 << 9)  | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) |
+                   (1 << 14) | (1 << 15));
+  EXTI->PR = pr;
+  if (pr & (1 << 4))
+    EXTD1.config->channels[4].cb(&EXTD1, 4);
+  if (pr & (1 << 5))
+    EXTD1.config->channels[5].cb(&EXTD1, 5);
+  if (pr & (1 << 6))
+    EXTD1.config->channels[6].cb(&EXTD1, 6);
+  if (pr & (1 << 7))
+    EXTD1.config->channels[7].cb(&EXTD1, 7);
+  if (pr & (1 << 8))
+    EXTD1.config->channels[8].cb(&EXTD1, 8);
+  if (pr & (1 << 9))
+    EXTD1.config->channels[9].cb(&EXTD1, 9);
+  if (pr & (1 << 10))
+    EXTD1.config->channels[10].cb(&EXTD1, 10);
+  if (pr & (1 << 11))
+    EXTD1.config->channels[11].cb(&EXTD1, 11);
+  if (pr & (1 << 12))
+    EXTD1.config->channels[12].cb(&EXTD1, 12);
+  if (pr & (1 << 13))
+    EXTD1.config->channels[13].cb(&EXTD1, 13);
+  if (pr & (1 << 14))
+    EXTD1.config->channels[14].cb(&EXTD1, 14);
+  if (pr & (1 << 15))
+    EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+  CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(PVD_IRQHandler) {
+
+  CH_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 16);
+  EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+  CH_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   EXTI[17] interrupt handler (RTC).
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(RTC_IRQHandler) {
+
+  CH_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 17);
+  EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+  CH_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+  nvicEnableVector(EXTI0_1_IRQn,
+                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_1_IRQ_PRIORITY));
+  nvicEnableVector(EXTI2_3_IRQn,
+                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_3_IRQ_PRIORITY));
+  nvicEnableVector(EXTI4_15_IRQn,
+                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_15_IRQ_PRIORITY));
+  nvicEnableVector(PVD_IRQn,
+                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));
+  nvicEnableVector(RTC_IRQn,
+                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));
+}
+
+/**
+ * @brief   Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+  nvicDisableVector(EXTI0_1_IRQn);
+  nvicDisableVector(EXTI2_3_IRQn);
+  nvicDisableVector(EXTI4_15_IRQn);
+  nvicDisableVector(PVD_IRQn);
+  nvicDisableVector(RTC_IRQn);
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.h b/os/hal/platforms/STM32F0xx/ext_lld_isr.h
new file mode 100644
index 000000000..6b2e49655
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/ext_lld_isr.h
@@ -0,0 +1,111 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F0xx/ext_lld_isr.h
+ * @brief   STM32F0xx EXT subsystem low level driver ISR header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef _EXT_LLD_ISR_H_
+#define _EXT_LLD_ISR_H_
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   EXTI0..1 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI0_1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI0_1_IRQ_PRIORITY      3
+#endif
+
+/**
+ * @brief   EXTI2..3 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI2_3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI2_3_IRQ_PRIORITY      3
+#endif
+
+/**
+ * @brief   EXTI4..15 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI4_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI4_15_IRQ_PRIORITY     3
+#endif
+
+/**
+ * @brief   EXTI16 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI16_IRQ_PRIORITY       3
+#endif
+
+/**
+ * @brief   EXTI17 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI17_IRQ_PRIORITY       3
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void ext_lld_exti_irq_enable(void);
+  void ext_lld_exti_irq_disable(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* _EXT_LLD_ISR_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 93403c91f..158407527 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -950,7 +950,8 @@
 /* External declarations.                                                    */
 /*===========================================================================*/
 
-/* STM32 DMA and RCC helpers.*/
+/* STM32 ISR, DMA and RCC helpers.*/
+#include "stm32_isr.h"
 #include "stm32_dma.h"
 #include "stm32_rcc.h"
 
diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index 9c0e709df..43a6d3328 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -1,12 +1,15 @@
-# List of all the STM32F1xx platform files.
+# List of all the STM32F0xx platform files.
 PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
-              ${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32F0xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c	\
-              ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c
+              ${CHIBIOS}/os/hal/platforms/STM32F0xx/adc_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32F0xx/ext_lld_isr.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c
 
 # Required include directories
 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
-              ${CHIBIOS}/os/hal/platforms/STM32
+              ${CHIBIOS}/os/hal/platforms/STM32 \
+              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2
diff --git a/os/hal/platforms/STM32F0xx/stm32_isr.h b/os/hal/platforms/STM32F0xx/stm32_isr.h
new file mode 100644
index 000000000..408636b72
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/stm32_isr.h
@@ -0,0 +1,73 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM3F0xx/stm32_isr.h
+ * @brief   ISR remapper driver header.
+ *
+ * @addtogroup STM32F0xx_ISR
+ * @{
+ */
+
+#ifndef _STM32_ISR_H_
+#define _STM32_ISR_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    ISR names and numbers remapping
+ * @{
+ */
+#define STM32_TIM1_UP_HANDLER       TIM1_BRK_UP_TRG_COM_IRQHandler
+#define STM32_TIM1_CC_HANDLER       TIM1_CC_IRQHandler
+#define STM32_TIM2_HANDLER          TIM2_IRQHandler
+#define STM32_TIM3_HANDLER          TIM3_IRQHandler
+
+#define STM32_TIM1_UP_NUMBER        TIM1_BRK_UP_TRG_COM_IRQn
+#define STM32_TIM1_CC_NUMBER        TIM1_CC_IRQn
+#define STM32_TIM2_NUMBER           TIM2_IRQn
+#define STM32_TIM3_NUMBER           TIM3_IRQn
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#endif /* _STM32_ISR_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/stm32f0xx.h b/os/hal/platforms/STM32F0xx/stm32f0xx.h
index 74bc8ff10..b041e5e12 100644
--- a/os/hal/platforms/STM32F0xx/stm32f0xx.h
+++ b/os/hal/platforms/STM32F0xx/stm32f0xx.h
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f0xx.h
   * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    23-March-2012
+  * @version V1.0.1
+  * @date    20-April-2012
   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32F0xx devices.  
@@ -61,7 +61,7 @@
   * @{
   */
   
-/* Uncomment the line below according to the target STM32F-0 device used in your 
+/* Uncomment the line below according to the target STM32F0 device used in your 
    application 
   */
 
@@ -71,8 +71,9 @@
 /*  Tip: To avoid modifying this file each time you need to switch between these
         devices, you can define the device in your toolchain compiler preprocessor.
 
- - STM32F0xx devices are STM32F050xx microcontrollers where the Flash memory 
-   density ranges between 32 and 64 Kbytes.
+ STM32F0xx devices are:
+    - STM32F050xx microcontrollers where the Flash memory density can go up to 32 Kbytes.
+    - STM32F051xx microcontrollers where the Flash memory density can go up to 64 Kbytes.
   */
 
 #if !defined (STM32F0XX)
@@ -138,11 +139,11 @@
 #endif /* LSE_VALUE */
 
 /**
- * @brief STM32F0xx Standard Peripheral Library version number V1.0.0
+ * @brief STM32F0xx Standard Peripheral Library version number V1.0.1
    */
 #define __STM32F0XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */
 #define __STM32F0XX_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
-#define __STM32F0XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F0XX_STDPERIPH_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
 #define __STM32F0XX_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32F0XX_STDPERIPH_VERSION        ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
                                              |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
@@ -2179,266 +2180,263 @@ typedef struct
 /*                                                                            */
 /******************************************************************************/
 /********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)        /*!<  */
-#define RTC_TR_HT                            ((uint32_t)0x00300000)        /*!<  */
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)        /*!<  */
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)        /*!<  */
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)        /*!<  */
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)        /*!<  */
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)        /*!<  */
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)        /*!<  */
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)        /*!<  */
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TR_ST                            ((uint32_t)0x00000070)        /*!<  */
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)        /*!<  */
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)        /*!<  */
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)        /*!<  */
+#define RTC_TR_PM                            ((uint32_t)0x00400000)
+#define RTC_TR_HT                            ((uint32_t)0x00300000)
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
+#define RTC_TR_ST                            ((uint32_t)0x00000070)
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
 
 /********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)        /*!<  */
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)        /*!<  */
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)        /*!<  */
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)        /*!<  */
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)        /*!<  */
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)        /*!<  */
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)        /*!<  */
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)        /*!<  */
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)        /*!<  */
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)        /*!<  */
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)        /*!<  */
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)        /*!<  */
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)        /*!<  */
-#define RTC_DR_MT                            ((uint32_t)0x00001000)        /*!<  */
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)        /*!<  */
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)        /*!<  */
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)        /*!<  */
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)        /*!<  */
-#define RTC_DR_DT                            ((uint32_t)0x00000030)        /*!<  */
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)        /*!<  */
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)        /*!<  */
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)        /*!<  */
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)        /*!<  */
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)        /*!<  */
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)        /*!<  */
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
+#define RTC_DR_MT                            ((uint32_t)0x00001000)
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
+#define RTC_DR_DT                            ((uint32_t)0x00000030)
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
 
 /********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)        /*!<  */
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)        /*!<  */
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)        /*!<  */
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)        /*!<  */
-#define RTC_CR_POL                           ((uint32_t)0x00100000)        /*!<  */
-#define RTC_CR_CALSEL                        ((uint32_t)0x00080000)        /*!<  */
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)        /*!<  */
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)        /*!<  */
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)        /*!<  */
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)        /*!<  */
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)        /*!<  */
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)        /*!<  */
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)        /*!<  */
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)        /*!<  */
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)        /*!<  */
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)        /*!<  */
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)        /*!<  */
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)        /*!<  */
+#define RTC_CR_COE                           ((uint32_t)0x00800000)
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
+#define RTC_CR_POL                           ((uint32_t)0x00100000)
+#define RTC_CR_CALSEL                        ((uint32_t)0x00080000)
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
+#define RTC_CR_DCE                           ((uint32_t)0x00000080)
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
 
 /********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)        /*!<  */
-#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)        /*!<  */
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)        /*!<  */
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)        /*!<  */
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)        /*!<  */
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)        /*!<  */
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)        /*!<  */
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)        /*!<  */
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)        /*!<  */
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)        /*!<  */
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)        /*!<  */
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)        /*!<  */
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
 
 /********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)        /*!<  */
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)        /*!<  */
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
 
 /********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)        /*!<  */
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)        /*!<  */
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)        /*!<  */
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)        /*!<  */
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)        /*!<  */
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)        /*!<  */
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)        /*!<  */
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)        /*!<  */
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)        /*!<  */
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)        /*!<  */
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)        /*!<  */
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)        /*!<  */
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)        /*!<  */
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)        /*!<  */
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)        /*!<  */
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)        /*!<  */
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)        /*!<  */
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)        /*!<  */
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)        /*!<  */
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)        /*!<  */
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)        /*!<  */
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)        /*!<  */
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)        /*!<  */
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)        /*!<  */
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)        /*!<  */
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)        /*!<  */
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)        /*!<  */
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)        /*!<  */
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)        /*!<  */
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)        /*!<  */
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)        /*!<  */
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)        /*!<  */
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)        /*!<  */
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)        /*!<  */
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)        /*!<  */
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)        /*!<  */
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)        /*!<  */
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
 
 /********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)        /*!<  */
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
 
 /********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)        /*!<  */
+#define RTC_SSR_SS                           ((uint32_t)0x0003FFFF)
 
 /********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)        /*!<  */
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)        /*!<  */
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
 
 /********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)        /*!<  */
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)        /*!<  */
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)        /*!<  */
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)        /*!<  */
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)        /*!<  */
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)        /*!<  */
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)        /*!<  */
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)        /*!<  */
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)        /*!<  */
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)        /*!<  */
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)        /*!<  */
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)        /*!<  */
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)        /*!<  */
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
 
 /********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)        /*!<  */
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)        /*!<  */
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)        /*!<  */
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)        /*!<  */
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)        /*!<  */
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
 
 /********************  Bits definition for RTC_TSSSR register  ****************/
 #define RTC_TSSSR_SS                         ((uint32_t)0x0003FFFF)
 
 /********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CAL_CALP                         ((uint32_t)0x00008000)        /*!<  */
-#define RTC_CAL_CALW8                        ((uint32_t)0x00004000)        /*!<  */
-#define RTC_CAL_CALW16                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_CAL_CALM                         ((uint32_t)0x000001FF)        /*!<  */
-#define RTC_CAL_CALM_0                       ((uint32_t)0x00000001)        /*!<  */
-#define RTC_CAL_CALM_1                       ((uint32_t)0x00000002)        /*!<  */
-#define RTC_CAL_CALM_2                       ((uint32_t)0x00000004)        /*!<  */
-#define RTC_CAL_CALM_3                       ((uint32_t)0x00000008)        /*!<  */
-#define RTC_CAL_CALM_4                       ((uint32_t)0x00000010)        /*!<  */
-#define RTC_CAL_CALM_5                       ((uint32_t)0x00000020)        /*!<  */
-#define RTC_CAL_CALM_6                       ((uint32_t)0x00000040)        /*!<  */
-#define RTC_CAL_CALM_7                       ((uint32_t)0x00000080)        /*!<  */
-#define RTC_CAL_CALM_8                       ((uint32_t)0x00000100)        /*!<  */
+#define RTC_CAL_CALP                         ((uint32_t)0x00008000)
+#define RTC_CAL_CALW8                        ((uint32_t)0x00004000)
+#define RTC_CAL_CALW16                       ((uint32_t)0x00002000)
+#define RTC_CAL_CALM                         ((uint32_t)0x000001FF)
+#define RTC_CAL_CALM_0                       ((uint32_t)0x00000001)
+#define RTC_CAL_CALM_1                       ((uint32_t)0x00000002)
+#define RTC_CAL_CALM_2                       ((uint32_t)0x00000004)
+#define RTC_CAL_CALM_3                       ((uint32_t)0x00000008)
+#define RTC_CAL_CALM_4                       ((uint32_t)0x00000010)
+#define RTC_CAL_CALM_5                       ((uint32_t)0x00000020)
+#define RTC_CAL_CALM_6                       ((uint32_t)0x00000040)
+#define RTC_CAL_CALM_7                       ((uint32_t)0x00000080)
+#define RTC_CAL_CALM_8                       ((uint32_t)0x00000100)
 
 /********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)        /*!<  */
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)        /*!<  */
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)        /*!<  */
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)        /*!<  */
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)        /*!<  */
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)        /*!<  */
-#define RTC_TAFCR_TAMP3EDGE                  ((uint32_t)0x00000040)        /*!<  */
-#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)        /*!<  */
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)        /*!<  */
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP2EDGE                  ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
 
 /********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)        /*!<  */
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)        /*!<  */
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)        /*!<  */
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)        /*!<  */
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)        /*!<  */
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)        /*!<  */
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
 
 /********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
 
 /********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
 
 /********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
 
 /********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
 
 /********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
 
 /******************************************************************************/
 /*                                                                            */
-- 
cgit v1.2.3


From a41017aac10f2255f13ce45044f567b021eeb474 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 21 Jun 2012 17:24:17 +0000
Subject: STM32 ICU and PWM drivers adapted to the new ISR names.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4319 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/platform.mk | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index 43a6d3328..acf4c94b3 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -5,6 +5,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32F0xx/ext_lld_isr.c \
               ${CHIBIOS}/os/hal/platforms/STM32/ext_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c
-- 
cgit v1.2.3


From 11907c39a829e1ecef33da09974028349af683f2 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 21 Jun 2012 17:39:26 +0000
Subject: STM32 CAN driver adapted to the new ISR names.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4320 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/stm32_isr.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/stm32_isr.h b/os/hal/platforms/STM32F0xx/stm32_isr.h
index 408636b72..a62fbc3cc 100644
--- a/os/hal/platforms/STM32F0xx/stm32_isr.h
+++ b/os/hal/platforms/STM32F0xx/stm32_isr.h
@@ -37,6 +37,9 @@
  * @name    ISR names and numbers remapping
  * @{
  */
+/*
+ * TIM units.
+ */
 #define STM32_TIM1_UP_HANDLER       TIM1_BRK_UP_TRG_COM_IRQHandler
 #define STM32_TIM1_CC_HANDLER       TIM1_CC_IRQHandler
 #define STM32_TIM2_HANDLER          TIM2_IRQHandler
-- 
cgit v1.2.3


From 45013b7f198dcec3021d673edba7a711d6d46cff Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 23 Jun 2012 17:29:35 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4332
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/platform.mk | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index acf4c94b3..217876573 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -9,9 +9,11 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c
+              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2\uart_lld.c
 
 # Required include directories
 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
               ${CHIBIOS}/os/hal/platforms/STM32 \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2
+              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
+              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2
-- 
cgit v1.2.3


From ae3db0129bf8fe34a660388e5066fb1328ba9e8a Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 23 Jun 2012 17:52:27 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4334
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/platform.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index 217876573..8586a6990 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -10,7 +10,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2\uart_lld.c
+              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c
 
 # Required include directories
 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
-- 
cgit v1.2.3


From 175612822f76d4e0d8b8ab354678e9767ec40214 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 24 Jun 2012 06:04:16 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4339
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/stm32_isr.h | 9 +++++++++
 1 file changed, 9 insertions(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/stm32_isr.h b/os/hal/platforms/STM32F0xx/stm32_isr.h
index a62fbc3cc..643092844 100644
--- a/os/hal/platforms/STM32F0xx/stm32_isr.h
+++ b/os/hal/platforms/STM32F0xx/stm32_isr.h
@@ -49,6 +49,15 @@
 #define STM32_TIM1_CC_NUMBER        TIM1_CC_IRQn
 #define STM32_TIM2_NUMBER           TIM2_IRQn
 #define STM32_TIM3_NUMBER           TIM3_IRQn
+
+/*
+ * USART units.
+ */
+#define STM32_USART1_HANDLER        USART1_IRQHandler
+#define STM32_USART2_HANDLER        USART2_IRQHandler
+
+#define STM32_USART1_NUMBER         USART1_IRQn
+#define STM32_USART2_NUMBER         USART2_IRQn
 /** @} */
 
 /*===========================================================================*/
-- 
cgit v1.2.3


From 79ec800cb608672f38f013ed8302aa6ad72016d0 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 21 Aug 2012 14:40:17 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4606
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.h | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 158407527..ada8d5887 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -592,6 +592,13 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F0xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F0xx_MCUCONF not defined"
+#endif
+
 /*
  * HSI related checks.
  */
-- 
cgit v1.2.3


From 35cae2a2900298061c197a19e0b6eace8eaa9312 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 21 Aug 2012 16:09:14 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4607
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/adc_lld.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h
index a0d823a8b..ecf215160 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.h
+++ b/os/hal/platforms/STM32F0xx/adc_lld.h
@@ -80,7 +80,7 @@
  * @note    The default is @p TRUE.
  */
 #if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC1                  TRUE
+#define STM32_ADC_USE_ADC1                  FALSE
 #endif
 
 /**
-- 
cgit v1.2.3


From 518fd1d0c7545ff362be8b4051d455a4e1937712 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 9 Sep 2012 07:36:08 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4643
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/platform.dox | 296 ++++++++++++++++++++++++++++++++
 os/hal/platforms/STM32F0xx/stm32_isr.h  |   2 +-
 2 files changed, 297 insertions(+), 1 deletion(-)
 create mode 100644 os/hal/platforms/STM32F0xx/platform.dox

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/platform.dox b/os/hal/platforms/STM32F0xx/platform.dox
new file mode 100644
index 000000000..dcbd78040
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/platform.dox
@@ -0,0 +1,296 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @defgroup STM32F0xx_DRIVERS STM32F0xx Drivers
+ * @details This section describes all the supported drivers on the STM32F0xx
+ *          platform and the implementation details of the single drivers.
+ *
+ * @ingroup platforms
+ */
+
+/**
+ * @defgroup STM32F0xx_HAL STM32F0xx Initialization Support
+ * @details The STM32F0xx HAL support is responsible for system initialization.
+ *
+ * @section stm32f0xx_hal_1 Supported HW resources
+ * - PLL1.
+ * - RCC.
+ * - Flash.
+ * .
+ * @section stm32f0xx_hal_2 STM32F0xx HAL driver implementation features
+ * - PLL startup and stabilization.
+ * - Clock tree initialization.
+ * - Clock source selection.
+ * - Flash wait states initialization based on the selected clock options.
+ * - SYSTICK initialization based on current clock and kernel required rate.
+ * - DMA support initialization.
+ * .
+ * @ingroup STM32F0xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_ADC STM32F0xx ADC Support
+ * @details The STM32F0xx ADC driver supports the ADC peripherals using DMA
+ *          channels for maximum performance.
+ *
+ * @section stm32f0xx_adc_1 Supported HW resources
+ * - ADC1.
+ * - DMA1.
+ * .
+ * @section stm32f0xx_adc_2 STM32F0xx ADC driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Streaming conversion using DMA for maximum performance.
+ * - Programmable ADC interrupt priority level.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - DMA errors detection.
+ * .
+ * @ingroup STM32F0xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_EXT STM32F0xx EXT Support
+ * @details The STM32F0xx EXT driver uses the EXTI peripheral.
+ *
+ * @section stm32f0xx_ext_1 Supported HW resources
+ * - EXTI.
+ * .
+ * @section stm32f0xx_ext_2 STM32F0xx EXT driver implementation features
+ * - Each EXTI channel can be independently enabled and programmed.
+ * - Programmable EXTI interrupts priority level.
+ * - Capability to work as event sources (WFE) rather than interrupt sources.
+ * .
+ * @ingroup STM32F0xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_GPT STM32F0xx GPT Support
+ * @details The STM32F0xx GPT driver uses the TIMx peripherals.
+ *
+ * @section stm32f0xx_gpt_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * .
+ * @section stm32f0xx_gpt_2 STM32F0xx GPT driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup STM32F0xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_ICU STM32F0xx ICU Support
+ * @details The STM32F0xx ICU driver uses the TIMx peripherals.
+ *
+ * @section stm32f0xx_icu_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * .
+ * @section stm32f0xx_icu_2 STM32F0xx ICU driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup STM32F0xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_PAL STM32F0xx PAL Support
+ * @details The STM32F0xx PAL driver uses the GPIO peripherals.
+ *
+ * @section stm32f0xx_pal_1 Supported HW resources
+ * - GPIOA.
+ * - GPIOB.
+ * - GPIOC.
+ * - GPIOD.
+ * - GPIOF.
+ * .
+ * @section stm32f0xx_pal_2 STM32F0xx PAL driver implementation features
+ * The PAL driver implementation fully supports the following hardware
+ * capabilities:
+ * - 16 bits wide ports.
+ * - Atomic set/reset functions.
+ * - Atomic set+reset function (atomic bus operations).
+ * - Output latched regardless of the pad setting.
+ * - Direct read of input pads regardless of the pad setting.
+ * .
+ * @section stm32f0xx_pal_3 Supported PAL setup modes
+ * The STM32F0xx PAL driver supports the following I/O modes:
+ * - @p PAL_MODE_RESET.
+ * - @p PAL_MODE_UNCONNECTED.
+ * - @p PAL_MODE_INPUT.
+ * - @p PAL_MODE_INPUT_PULLUP.
+ * - @p PAL_MODE_INPUT_PULLDOWN.
+ * - @p PAL_MODE_INPUT_ANALOG.
+ * - @p PAL_MODE_OUTPUT_PUSHPULL.
+ * - @p PAL_MODE_OUTPUT_OPENDRAIN.
+ * - @p PAL_MODE_ALTERNATE (non standard).
+ * .
+ * Any attempt to setup an invalid mode is ignored.
+ *
+ * @section stm32f0xx_pal_4 Suboptimal behavior
+ * The STM32F0xx GPIO is less than optimal in several areas, the limitations
+ * should be taken in account while using the PAL driver:
+ * - Pad/port toggling operations are not atomic.
+ * - Pad/group mode setup is not atomic.
+ * .
+ * @ingroup STM32F0xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_PWM STM32F0xx PWM Support
+ * @details The STM32F0xx PWM driver uses the TIMx peripherals.
+ *
+ * @section stm32f0xx_pwm_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * .
+ * @section stm32f0xx_pwm_2 STM32F0xx PWM driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Four independent PWM channels per timer.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup STM32F0xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_SERIAL STM32F0xx Serial Support
+ * @details The STM32F0xx Serial driver uses the USART/UART peripherals in a
+ *          buffered, interrupt driven, implementation.
+ *
+ * @section stm32f0xx_serial_1 Supported HW resources
+ * The serial driver can support any of the following hardware resources:
+ * - USART1.
+ * - USART2.
+ * .
+ * @section stm32f0xx_serial_2 STM32F0xx Serial driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART/USART can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Fully interrupt driven.
+ * - Programmable priority levels for each UART/USART.
+ * .
+ * @ingroup STM32F0xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_SPI STM32F0xx SPI Support
+ * @details The SPI driver supports the STM32F0xx SPI peripherals using DMA
+ *          channels for maximum performance.
+ *
+ * @section stm32f0xx_spi_1 Supported HW resources
+ * - SPI1.
+ * - SPI2.
+ * - DMA1.
+ * .
+ * @section stm32f0xx_spi_2 STM32F0xx SPI driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each SPI can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Programmable interrupt priority levels for each SPI.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - Programmable DMA error hook.
+ * .
+ * @ingroup STM32F0xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_UART STM32F0xx UART Support
+ * @details The UART driver supports the STM32F0xx USART peripherals using DMA
+ *          channels for maximum performance.
+ *
+ * @section stm32f0xx_uart_1 Supported HW resources
+ * The UART driver can support any of the following hardware resources:
+ * - USART1.
+ * - USART2.
+ * - DMA1.
+ * .
+ * @section stm32f0xx_uart_2 STM32F0xx UART driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART/USART can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Programmable interrupt priority levels for each UART/USART.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - Programmable DMA error hook.
+ * .
+ * @ingroup STM32F0xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_PLATFORM_DRIVERS STM32F0xx Platform Drivers
+ * @details Platform support drivers. Platform drivers do not implement HAL
+ *          standard driver templates, their role is to support platform
+ *          specific functionalities.
+ *
+ * @ingroup STM32F0xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_DMA STM32F0xx DMA Support
+ * @details This DMA helper driver is used by the other drivers in order to
+ *          access the shared DMA resources in a consistent way.
+ *
+ * @section stm32f0xx_dma_1 Supported HW resources
+ * The DMA driver can support any of the following hardware resources:
+ * - DMA1.
+ * - DMA2 (where present).
+ * .
+ * @section stm32f0xx_dma_2 STM32F0xx DMA driver implementation features
+ * - Exports helper functions/macros to the other drivers that share the
+ *   DMA resource.
+ * - Automatic DMA clock stop when not in use by any driver.
+ * - DMA streams and interrupt vectors sharing among multiple drivers.
+ * .
+ * @ingroup STM32F0xx_PLATFORM_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_ISR STM32F0xx ISR Support
+ * @details This ISR helper driver is used by the other drivers in order to
+ *          map ISR names to physical vector names.
+ *
+ * @ingroup STM32F0xx_PLATFORM_DRIVERS
+ */
+
+/**
+ * @defgroup STM32F0xx_RCC STM32F0xx RCC Support
+ * @details This RCC helper driver is used by the other drivers in order to
+ *          access the shared RCC resources in a consistent way.
+ *
+ * @section stm32f0xx_rcc_1 Supported HW resources
+ * - RCC.
+ * .
+ * @section stm32f0xx_rcc_2 STM32F0xx RCC driver implementation features
+ * - Peripherals reset.
+ * - Peripherals clock enable.
+ * - Peripherals clock disable.
+ * .
+ * @ingroup STM32F0xx_PLATFORM_DRIVERS
+ */
diff --git a/os/hal/platforms/STM32F0xx/stm32_isr.h b/os/hal/platforms/STM32F0xx/stm32_isr.h
index 643092844..8d7a2875a 100644
--- a/os/hal/platforms/STM32F0xx/stm32_isr.h
+++ b/os/hal/platforms/STM32F0xx/stm32_isr.h
@@ -19,7 +19,7 @@
 */
 
 /**
- * @file    STM3F0xx/stm32_isr.h
+ * @file    STM32F0xx/stm32_isr.h
  * @brief   ISR remapper driver header.
  *
  * @addtogroup STM32F0xx_ISR
-- 
cgit v1.2.3


From c78662c143424c4f5581b9e641d45ec75f06d704 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 13 Oct 2012 10:56:30 +0000
Subject: Fixed bug 3576193.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4756 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/ext_lld_isr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.c b/os/hal/platforms/STM32F0xx/ext_lld_isr.c
index acfc42024..8b8e81db8 100644
--- a/os/hal/platforms/STM32F0xx/ext_lld_isr.c
+++ b/os/hal/platforms/STM32F0xx/ext_lld_isr.c
@@ -83,7 +83,7 @@ CH_IRQ_HANDLER(EXTI2_3_IRQHandler) {
 
   CH_IRQ_PROLOGUE();
 
-  pr = EXTI->PR & ((2 << 0) | (3 << 1));
+  pr = EXTI->PR & ((1 << 2) | (1 << 3));
   EXTI->PR = pr;
   if (pr & (1 << 2))
     EXTD1.config->channels[2].cb(&EXTD1, 2);
@@ -98,7 +98,7 @@ CH_IRQ_HANDLER(EXTI2_3_IRQHandler) {
  *
  * @isr
  */
-CH_IRQ_HANDLER(EXTI9_5_IRQHandler) {
+CH_IRQ_HANDLER(EXTI4_15_IRQHandler) {
   uint32_t pr;
 
   CH_IRQ_PROLOGUE();
-- 
cgit v1.2.3


From efbd7db9789c18e465750646d51a5fab936c5fc6 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 22 Oct 2012 17:46:59 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4776
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.h | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index ada8d5887..4e64865ab 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -53,7 +53,7 @@
  * @name    Platform identification
  * @{
  */
-#define PLATFORM_NAME           "STM32F0 Entry Level"
+#define PLATFORM_NAME           "STM32F05x Entry Level"
 /** @} */
 
 /**
@@ -91,7 +91,7 @@
 #define STM32_PLLIN_MAX         25000000
 
 /**
- * @brief   Maximum PLLs input clock frequency.
+ * @brief   Minimum PLLs input clock frequency.
  */
 #define STM32_PLLIN_MIN         1000000
 
@@ -101,7 +101,7 @@
 #define STM32_PLLOUT_MAX        48000000
 
 /**
- * @brief   Maximum PLL output clock frequency.
+ * @brief   Minimum PLL output clock frequency.
  */
 #define STM32_PLLOUT_MIN        16000000
 
@@ -197,7 +197,7 @@
  * @name    RCC_CFGR3 register bits definitions
  * @{
  */
-#define STM32_USART1SW_MASK     (3 << 0)    /**< RTC clock source mask.     */
+#define STM32_USART1SW_MASK     (3 << 0)    /**< USART1 clock source mask.  */
 #define STM32_USART1SW_PCLK     (0 << 0)    /**< USART1 clock is PCLK.      */
 #define STM32_USART1SW_SYSCLK   (1 << 0)    /**< USART1 clock is SYSCLK.    */
 #define STM32_USART1SW_LSE      (2 << 0)    /**< USART1 clock is LSE.       */
@@ -223,8 +223,8 @@
  */
 /* ADC attributes.*/
 #define STM32_HAS_ADC1          TRUE
-#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 0) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 1))
+#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 1) |            \
+                                 STM32_DMA_STREAM_ID_MSK(1, 2))
 #define STM32_ADC1_DMA_CHN      0x00000000
 
 #define STM32_HAS_ADC2          FALSE
@@ -479,6 +479,7 @@
 #if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
 #define STM32_LSE_ENABLED           FALSE
 #endif
+
 /**
  * @brief   Main clock source selection.
  * @note    If the selected clock source is not the PLL then the PLL is not
-- 
cgit v1.2.3


From 7112dfa32e35f35998bf4ab05888317ef5aed59a Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 23 Oct 2012 20:51:36 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4777
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.c | 10 ++++++++++
 os/hal/platforms/STM32F0xx/hal_lld.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
index 401afe7e3..1e7a83e36 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -29,6 +29,10 @@
 #include "ch.h"
 #include "hal.h"
 
+/* TODO: LSEBYP like in F3.*/
+/* TODO: LSEDRV like in F3.*/
+/* TODO: PREDIV like in F3.*/
+
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
@@ -142,7 +146,13 @@ void stm32_clock_init(void) {
 
 #if STM32_HSE_ENABLED
   /* HSE activation.*/
+#if defined(STM32_HSE_BYPASS)
+  /* HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#else
+  /* No HSE Bypass.*/
   RCC->CR |= RCC_CR_HSEON;
+#endif
   while (!(RCC->CR & RCC_CR_HSERDY))
     ;                                       /* Waits until HSE is stable.   */
 #endif
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 4e64865ab..b8abe4bd5 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -792,7 +792,7 @@
 #elif (STM32_SW == STM32_SW_HSE)
 #define STM32_SYSCLK                STM32_HSECLK
 #else
-#error "invalid STM32_SYSCLK_SW value specified"
+#error "invalid STM32_SW value specified"
 #endif
 
 /* Check on the system clock.*/
-- 
cgit v1.2.3


From ca0b2a235d6b537896efeb11f263d7e103a92d82 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 24 Oct 2012 09:46:46 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4778
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
index 1e7a83e36..10b6db940 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -171,19 +171,20 @@ void stm32_clock_init(void) {
     ;                                       /* Waits until LSI is stable.   */
 #endif
 
+  /* Clock settings.*/
+  RCC->CFGR  = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE |
+               STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE     |
+               STM32_HPRE;
+  RCC->CFGR3 = STM32_ADCSW  | STM32_CECSW  | STM32_I2C1SW   |
+               STM32_USART1SW;
+
 #if STM32_ACTIVATE_PLL
   /* PLL activation.*/
-  RCC->CFGR |= STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC;
   RCC->CR   |= RCC_CR_PLLON;
   while (!(RCC->CR & RCC_CR_PLLRDY))
     ;                                       /* Waits until PLL is stable.   */
 #endif
 
-  /* Clock settings.*/
-  RCC->CFGR  = STM32_MCOSEL |                STM32_PLLMUL | STM32_PLLXTPRE |
-               STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE   | STM32_HPRE;
-  RCC->CFGR3 = STM32_ADCSW  | STM32_CECSW  | STM32_I2C1SW | STM32_USART1SW;
-
   /* Flash setup and final clock selection.   */
   FLASH->ACR = STM32_FLASHBITS;
 
-- 
cgit v1.2.3


From 14ed8520a293cedc1263442574a3d2f48d0b6df5 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 30 Nov 2012 13:15:58 +0000
Subject: STM32 Serial drivers split in two distinct versions, for old and new
 USARTs.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4850 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/platform.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index 8586a6990..54b05bdbc 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -7,9 +7,9 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c
 
 # Required include directories
-- 
cgit v1.2.3


From d65e5e6b0d687a87abfad5f92a27e5920314f0fa Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 4 Dec 2012 15:02:49 +0000
Subject: Serial support for STM32F3xx.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4871 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/hal_lld.h | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index b8abe4bd5..d38248ce5 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -926,6 +926,11 @@
 #error "invalid source selected for USART1 clock"
 #endif
 
+/**
+ * @brief   USART2 frequency.
+ */
+#define STM32_USART2CLK             STM32_PCLK
+
 /**
  * @brief   Timers clock.
  */
-- 
cgit v1.2.3


From c8f3291765c55611ef8a8f26e4a9be817d7c0cbe Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 5 Dec 2012 15:05:54 +0000
Subject: Fixed bug 3592809.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4876 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/stm32_dma.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.h b/os/hal/platforms/STM32F0xx/stm32_dma.h
index b1e06e6b5..1bf669931 100644
--- a/os/hal/platforms/STM32F0xx/stm32_dma.h
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.h
@@ -142,7 +142,7 @@
 #define STM32_DMA_CR_MSIZE_BYTE     0
 #define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR_MSIZE_0
 #define STM32_DMA_CR_MSIZE_WORD     DMA_CCR_MSIZE_1
-#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_MSIZE_MASK |              \
+#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
                                      STM32_DMA_CR_MSIZE_MASK)
 #define STM32_DMA_CR_PL_MASK        DMA_CCR_PL
 #define STM32_DMA_CR_PL(n)          ((n) << 12)
-- 
cgit v1.2.3


From 9d3e7a8fbca5679379f6bc713ed8dc1d8e880589 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 5 Dec 2012 15:07:55 +0000
Subject: STM32 SPI driver divided in two distinct implementations.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4877 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/platform.mk | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index 54b05bdbc..04b6c5f24 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -7,8 +7,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c
 
@@ -16,4 +16,5 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
               ${CHIBIOS}/os/hal/platforms/STM32 \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
+              ${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv2
-- 
cgit v1.2.3


From 633098ebcd87d2a654deede6feff0d93fdabaebc Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 6 Dec 2012 10:53:16 +0000
Subject: STM32F3 SPI working, STM32F0 support update.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4879 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/hal_lld.c | 20 ++++++++++--------
 os/hal/platforms/STM32F0xx/hal_lld.h | 40 ++++++++++++++++++++----------------
 2 files changed, 33 insertions(+), 27 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
index 10b6db940..57b548ce3 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -29,10 +29,6 @@
 #include "ch.h"
 #include "hal.h"
 
-/* TODO: LSEBYP like in F3.*/
-/* TODO: LSEDRV like in F3.*/
-/* TODO: PREDIV like in F3.*/
-
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
@@ -64,7 +60,13 @@ static void hal_lld_backup_domain_init(void) {
 
   /* If enabled then the LSE is started.*/
 #if STM32_LSE_ENABLED
-  RCC->BDCR |= RCC_BDCR_LSEON;
+#if defined(STM32_LSE_BYPASS)
+  /* LSE Bypass.*/
+  RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+  /* No LSE Bypass.*/
+  RCC->BDCR = STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
   while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
     ;                                     /* Waits until LSE is stable.   */
 #endif
@@ -172,10 +174,10 @@ void stm32_clock_init(void) {
 #endif
 
   /* Clock settings.*/
-  RCC->CFGR  = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE |
-               STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE     |
-               STM32_HPRE;
-  RCC->CFGR3 = STM32_ADCSW  | STM32_CECSW  | STM32_I2C1SW   |
+  RCC->CFGR  = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC |
+               STM32_ADCPRE | STM32_PPRE   | STM32_HPRE;
+  RCC->CFGR2 = STM32_PREDIV;
+  RCC->CFGR3 = STM32_ADCSW  | STM32_CECSW  | STM32_I2C1SW |
                STM32_USART1SW;
 
 #if STM32_ACTIVATE_PLL
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index d38248ce5..775892391 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -24,6 +24,8 @@
  * @pre     This module requires the following macros to be defined in the
  *          @p board.h file:
  *          - STM32_LSECLK.
+ *          - STM32_LSEDRV.
+ *          - STM32_LSE_BYPASS (optionally).
  *          - STM32_HSECLK.
  *          - STM32_HSE_BYPASS (optionally).
  *          .
@@ -170,9 +172,6 @@
 #define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI.   */
 #define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is HSE.   */
 
-#define STM32_PLLXTPRE_DIV1     (0 << 17)   /**< HSE divided by 1.          */
-#define STM32_PLLXTPRE_DIV2     (1 << 17)   /**< HSE divided by 2.          */
-
 #define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
 #define STM32_MCOSEL_HSI14      (3 << 24)   /**< HSI14 clock on MCO pin.    */
 #define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
@@ -506,11 +505,11 @@
  * @brief   Crystal PLL pre-divider.
  * @note    This setting has only effect if the PLL is selected as the
  *          system clock source.
- * @note    The default value is calculated for a 48MHz system clock from
+ * @note    The default value is calculated for a 72MHz system clock from
  *          a 8MHz crystal using the PLL.
  */
-#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
-#define STM32_PLLXTPRE              STM32_PLLXTPRE_DIV1
+#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PREDIV_VALUE                  1
 #endif
 
 /**
@@ -704,6 +703,18 @@
 #error "LSE frequency not defined"
 #endif
 
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined"
+#endif
+
+#if (STM32_LSEDRV >> 3) > 3
+#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
+#endif
+
 #if STM32_CECSW == STM32_CECSW_LSE
 #error "LSE not enabled, required by STM32_CECSW"
 #endif
@@ -712,10 +723,6 @@
 #error "LSE not enabled, required by STM32_USART1SW"
 #endif
 
-#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
-#endif
-
 #else /* !STM32_LSE_ENABLED */
 
 #if STM32_RTCSEL == STM32_RTCSEL_LSE
@@ -737,9 +744,10 @@
 #endif
 
 /* HSE prescaler setting check.*/
-#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) &&                              \
-    (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
-#error "invalid STM32_PLLXTPRE value specified"
+#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
+#define STM32_PREDIV                ((STM32_PREDIV_VALUE - 1) << 0)
+#else
+#error "invalid STM32_PREDIV value specified"
 #endif
 
 /**
@@ -756,11 +764,7 @@
  * @brief   PLL input clock frequency.
  */
 #if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
-#define STM32_PLLCLKIN              (STM32_HSECLK / 1)
-#else
-#define STM32_PLLCLKIN              (STM32_HSECLK / 2)
-#endif
+#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PREDIV_VALUE)
 #elif STM32_PLLSRC == STM32_PLLSRC_HSI
 #define STM32_PLLCLKIN              (STM32_HSICLK / 2)
 #else
-- 
cgit v1.2.3


From 7273d8390d8cff3ef45289a5b6797f0fae13c515 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 24 Dec 2012 18:02:49 +0000
Subject: Files for STM32F3xx ADC driver, not complete.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4970 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/adc_lld.h | 2 +-
 os/hal/platforms/STM32F0xx/hal_lld.h | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h
index ecf215160..f51b60716 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.h
+++ b/os/hal/platforms/STM32F0xx/adc_lld.h
@@ -77,7 +77,7 @@
 /**
  * @brief   ADC1 driver enable switch.
  * @details If set to @p TRUE the support for ADC1 is included.
- * @note    The default is @p TRUE.
+ * @note    The default is @p FALSE.
  */
 #if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
 #define STM32_ADC_USE_ADC1                  FALSE
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 775892391..362a553d4 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -234,6 +234,10 @@
 #define STM32_ADC3_DMA_MSK      0x00000000
 #define STM32_ADC3_DMA_CHN      0x00000000
 
+#define STM32_HAS_ADC4          FALSE
+#define STM32_ADC4_DMA_MSK      0x00000000
+#define STM32_ADC4_DMA_CHN      0x00000000
+
 /* CAN attributes.*/
 #define STM32_HAS_CAN1          FALSE
 #define STM32_HAS_CAN2          FALSE
-- 
cgit v1.2.3


From b999931853091a3683a9f9fa5a1eb2c1c5c856a2 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 25 Dec 2012 08:20:13 +0000
Subject: Code templates-related fixes.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4971 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/adc_lld.c | 4 ++++
 os/hal/platforms/STM32F0xx/hal_lld.c | 4 ++++
 2 files changed, 8 insertions(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
index dcc7c64f0..35b633344 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -31,6 +31,10 @@
 
 #if HAL_USE_ADC || defined(__DOXYGEN__)
 
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
index 57b548ce3..7c76cb272 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -29,6 +29,10 @@
 #include "ch.h"
 #include "hal.h"
 
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
-- 
cgit v1.2.3


From fdfd900d9707de137c87258c7b83882a25dc4697 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Wed, 26 Dec 2012 09:07:31 +0000
Subject: Fixed typo.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4974 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/adc_lld.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h
index f51b60716..785cb9bb8 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.h
+++ b/os/hal/platforms/STM32F0xx/adc_lld.h
@@ -289,7 +289,7 @@ struct ADCDriver {
    */
   ADC_TypeDef               *adc;
   /**
-   * @brief Pointer to associated SMA channel.
+   * @brief Pointer to associated DMA channel.
    */
   const stm32_dma_stream_t  *dmastp;
   /**
-- 
cgit v1.2.3


From c4dcbb3e9881654b9c4d96837a994ce305ab4d35 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 30 Dec 2012 17:41:53 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4999
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
index 7c76cb272..a8b73fd88 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -114,7 +114,7 @@ void hal_lld_init(void) {
                   SysTick_CTRL_ENABLE_Msk |
                   SysTick_CTRL_TICKINT_Msk;
 
-  /* PWR and BD clocks enabled.*/
+  /* PWR clock enabled.*/
   rccEnablePWRInterface(FALSE);
 
   /* Initializes the backup domain.*/
-- 
cgit v1.2.3


From 75a75a7ddcdc0ea45941ecc7593900824a088715 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 2 Feb 2013 10:01:27 +0000
Subject: Fixed bug 3602150.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5096 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/stm32_rcc.h | 54 ++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/stm32_rcc.h b/os/hal/platforms/STM32F0xx/stm32_rcc.h
index d10aa6de7..2db4b26fa 100644
--- a/os/hal/platforms/STM32F0xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F0xx/stm32_rcc.h
@@ -528,6 +528,60 @@
  * @api
  */
 #define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
+
+/**
+ * @brief   Enables the CRC peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp)
+
+/**
+ * @brief   Disables the CRC peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCRC(lp) rccDisableAHB(RCC_AHBENR_CRCEN, lp)
+
+/**
+ * @brief   Resets the CRC peripheral.
+ *
+ * @api
+ */
+#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST)
+
+/**
+ * @brief   Enables the WWDG peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableWWDG(lp) rccEnableAPB1(RCC_APB1ENR_WWDGEN, lp)
+
+/**
+ * @brief   Disables the WWDG peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableWWDG(lp) rccDisableAPB1(RCC_APB1ENR_WWDGEN, lp)
+
+/**
+ * @brief   Resets the WWDG peripheral.
+ *
+ * @api
+ */
+#define rccResetWWDG() rccResetAPB1(RCC_APB1RSTR_WWDGRST)
 /** @} */
 
 /*===========================================================================*/
-- 
cgit v1.2.3


From 184a71345c6a36a9a8664eda8fbcc3ea728267a8 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 2 Feb 2013 10:58:09 +0000
Subject: Updated license years.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5102 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/adc_lld.c     | 2 +-
 os/hal/platforms/STM32F0xx/adc_lld.h     | 2 +-
 os/hal/platforms/STM32F0xx/ext_lld_isr.c | 2 +-
 os/hal/platforms/STM32F0xx/ext_lld_isr.h | 2 +-
 os/hal/platforms/STM32F0xx/hal_lld.c     | 2 +-
 os/hal/platforms/STM32F0xx/hal_lld.h     | 2 +-
 os/hal/platforms/STM32F0xx/platform.dox  | 2 +-
 os/hal/platforms/STM32F0xx/stm32_dma.c   | 2 +-
 os/hal/platforms/STM32F0xx/stm32_dma.h   | 2 +-
 os/hal/platforms/STM32F0xx/stm32_isr.h   | 2 +-
 os/hal/platforms/STM32F0xx/stm32_rcc.h   | 2 +-
 11 files changed, 11 insertions(+), 11 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
index 35b633344..c8d25755e 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h
index 785cb9bb8..5a901646e 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.h
+++ b/os/hal/platforms/STM32F0xx/adc_lld.h
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.c b/os/hal/platforms/STM32F0xx/ext_lld_isr.c
index 8b8e81db8..8030b2623 100644
--- a/os/hal/platforms/STM32F0xx/ext_lld_isr.c
+++ b/os/hal/platforms/STM32F0xx/ext_lld_isr.c
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.h b/os/hal/platforms/STM32F0xx/ext_lld_isr.h
index 6b2e49655..11fcd3a1c 100644
--- a/os/hal/platforms/STM32F0xx/ext_lld_isr.h
+++ b/os/hal/platforms/STM32F0xx/ext_lld_isr.h
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
index a8b73fd88..bde03e23f 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 362a553d4..2dbaeb626 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
diff --git a/os/hal/platforms/STM32F0xx/platform.dox b/os/hal/platforms/STM32F0xx/platform.dox
index dcbd78040..871ecd526 100644
--- a/os/hal/platforms/STM32F0xx/platform.dox
+++ b/os/hal/platforms/STM32F0xx/platform.dox
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.c b/os/hal/platforms/STM32F0xx/stm32_dma.c
index f5191f954..3ddcdb3fd 100644
--- a/os/hal/platforms/STM32F0xx/stm32_dma.c
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.c
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.h b/os/hal/platforms/STM32F0xx/stm32_dma.h
index 1bf669931..c07aa34fb 100644
--- a/os/hal/platforms/STM32F0xx/stm32_dma.h
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.h
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
diff --git a/os/hal/platforms/STM32F0xx/stm32_isr.h b/os/hal/platforms/STM32F0xx/stm32_isr.h
index 8d7a2875a..2332ea0e8 100644
--- a/os/hal/platforms/STM32F0xx/stm32_isr.h
+++ b/os/hal/platforms/STM32F0xx/stm32_isr.h
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
diff --git a/os/hal/platforms/STM32F0xx/stm32_rcc.h b/os/hal/platforms/STM32F0xx/stm32_rcc.h
index 2db4b26fa..2ff8cea35 100644
--- a/os/hal/platforms/STM32F0xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F0xx/stm32_rcc.h
@@ -1,6 +1,6 @@
 /*
     ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012 Giovanni Di Sirio.
+                 2011,2012,2013 Giovanni Di Sirio.
 
     This file is part of ChibiOS/RT.
 
-- 
cgit v1.2.3


From f116535a69d7b1c6a5af7a2392eb7a4fb2bb7e40 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 10 Feb 2013 11:16:47 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5148
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 2dbaeb626..40cc595f3 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -332,6 +332,8 @@
 #define STM32_HAS_TIM15         TRUE
 #define STM32_HAS_TIM16         TRUE
 #define STM32_HAS_TIM17         TRUE
+#define STM32_HAS_TIM18         FALSE
+#define STM32_HAS_TIM19         FALSE
 
 /* USART attributes.*/
 #define STM32_HAS_USART1        TRUE
-- 
cgit v1.2.3


From 01f971ba1d63d8568789adf51cde22fb35f69e73 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 28 Feb 2013 16:23:19 +0000
Subject: Adjusted C file templates.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5339 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/adc_lld.c | 2 +-
 os/hal/platforms/STM32F0xx/hal_lld.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
index c8d25755e..a697d9245 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -45,7 +45,7 @@ ADCDriver ADCD1;
 #endif
 
 /*===========================================================================*/
-/* Driver local variables.                                                   */
+/* Driver local variables and types.                                         */
 /*===========================================================================*/
 
 /*===========================================================================*/
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
index bde03e23f..bf1f26e39 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -38,7 +38,7 @@
 /*===========================================================================*/
 
 /*===========================================================================*/
-/* Driver local variables.                                                   */
+/* Driver local variables and types.                                         */
 /*===========================================================================*/
 
 /*===========================================================================*/
-- 
cgit v1.2.3


From f9a52f29e05620f3ba4a849072f861faefd028eb Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 4 Mar 2013 08:28:44 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5352
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/stm32_dma.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.c b/os/hal/platforms/STM32F0xx/stm32_dma.c
index 3ddcdb3fd..ae8bda30a 100644
--- a/os/hal/platforms/STM32F0xx/stm32_dma.c
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.c
@@ -233,7 +233,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
                          stm32_dmaisr_t func,
                          void *param) {
 
-  chDbgCheck(dmastp != NULL, "dmaAllocate");
+  chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
 
   /* Checks if the stream is already taken.*/
   if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
@@ -274,11 +274,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
  */
 void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
 
-  chDbgCheck(dmastp != NULL, "dmaRelease");
+  chDbgCheck(dmastp != NULL, "dmaStreamRelease");
 
   /* Check if the streams is not taken.*/
   chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
-              "dmaRelease(), #1", "not allocated");
+              "dmaStreamRelease(), #1", "not allocated");
 
   /* Disables the associated IRQ vector.*/
   nvicDisableVector(dmastp->vector);
-- 
cgit v1.2.3


From 4e3ffc5134a06a4e6b87a02fc85bd16e77656bd4 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 10 Mar 2013 11:04:37 +0000
Subject: Fixed bug 3607518.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5401 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/stm32_dma.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.h b/os/hal/platforms/STM32F0xx/stm32_dma.h
index c07aa34fb..b7a07d6ea 100644
--- a/os/hal/platforms/STM32F0xx/stm32_dma.h
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.h
@@ -309,7 +309,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
  * @special
  */
 #define dmaStreamDisable(dmastp) {                                          \
-  (dmastp)->channel->CCR &= ~STM32_DMA_CR_EN;                               \
+  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
+                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
   dmaStreamClearInterrupt(dmastp);                                          \
 }
 
-- 
cgit v1.2.3


From de0bd4b20d026659defa6dbfa664723acedf1443 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 10 Mar 2013 13:57:25 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5404
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/stm32_dma.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.h b/os/hal/platforms/STM32F0xx/stm32_dma.h
index b7a07d6ea..61838a2c9 100644
--- a/os/hal/platforms/STM32F0xx/stm32_dma.h
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.h
@@ -301,6 +301,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
  * @details The function disables the specified stream and then clears any
  *          pending interrupt.
  * @note    This function can be invoked in both ISR or thread context.
+ * @note    Interrupts enabling flags are set to zero after this call, see
+ *          bug 3607518.
  * @pre     The stream must have been allocated using @p dmaStreamAllocate().
  * @post    After use the stream can be released using @p dmaStreamRelease().
  *
-- 
cgit v1.2.3


From a084bc7d1b620378710eb6468066b5576d9850f4 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 17 Mar 2013 13:37:57 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5448
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/platform.mk | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index 04b6c5f24..1c2de5103 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -8,6 +8,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/pal_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c
@@ -16,5 +17,6 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F0xx \
               ${CHIBIOS}/os/hal/platforms/STM32 \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
+              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2 \
               ${CHIBIOS}/os/hal/platforms/STM32/SPIv2 \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv2
-- 
cgit v1.2.3


From f24f61dc0ee1dd8a4b538bdcbfaac870aa39816a Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 18 Mar 2013 10:47:25 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5450
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/platform.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index 1c2de5103..c04d85c76 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -8,7 +8,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/I2Cv2/i2c_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/SPIv2/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c
-- 
cgit v1.2.3


From 853216256ad4cdacf5f94edb7d6b738c6be165a1 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 30 Mar 2013 10:32:37 +0000
Subject: Relicensing parts of the tree under the Apache 2.0 license.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5521 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/adc_lld.c     | 24 ++++++++++--------------
 os/hal/platforms/STM32F0xx/adc_lld.h     | 24 ++++++++++--------------
 os/hal/platforms/STM32F0xx/ext_lld_isr.c | 24 ++++++++++--------------
 os/hal/platforms/STM32F0xx/ext_lld_isr.h | 24 ++++++++++--------------
 os/hal/platforms/STM32F0xx/hal_lld.c     | 24 ++++++++++--------------
 os/hal/platforms/STM32F0xx/hal_lld.h     | 24 ++++++++++--------------
 os/hal/platforms/STM32F0xx/platform.dox  | 24 ++++++++++--------------
 os/hal/platforms/STM32F0xx/stm32_dma.c   | 24 ++++++++++--------------
 os/hal/platforms/STM32F0xx/stm32_dma.h   | 24 ++++++++++--------------
 os/hal/platforms/STM32F0xx/stm32_isr.h   | 24 ++++++++++--------------
 os/hal/platforms/STM32F0xx/stm32_rcc.h   | 24 ++++++++++--------------
 11 files changed, 110 insertions(+), 154 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
index a697d9245..2fad88cda 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/os/hal/platforms/STM32F0xx/adc_lld.h b/os/hal/platforms/STM32F0xx/adc_lld.h
index 5a901646e..411e31581 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.h
+++ b/os/hal/platforms/STM32F0xx/adc_lld.h
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.c b/os/hal/platforms/STM32F0xx/ext_lld_isr.c
index 8030b2623..d4fd06155 100644
--- a/os/hal/platforms/STM32F0xx/ext_lld_isr.c
+++ b/os/hal/platforms/STM32F0xx/ext_lld_isr.c
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.h b/os/hal/platforms/STM32F0xx/ext_lld_isr.h
index 11fcd3a1c..9885fbc65 100644
--- a/os/hal/platforms/STM32F0xx/ext_lld_isr.h
+++ b/os/hal/platforms/STM32F0xx/ext_lld_isr.h
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
index bf1f26e39..7c5bdce8e 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 40cc595f3..48a3be448 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/os/hal/platforms/STM32F0xx/platform.dox b/os/hal/platforms/STM32F0xx/platform.dox
index 871ecd526..c8caa2b89 100644
--- a/os/hal/platforms/STM32F0xx/platform.dox
+++ b/os/hal/platforms/STM32F0xx/platform.dox
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.c b/os/hal/platforms/STM32F0xx/stm32_dma.c
index ae8bda30a..44f10cbf6 100644
--- a/os/hal/platforms/STM32F0xx/stm32_dma.c
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.c
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.h b/os/hal/platforms/STM32F0xx/stm32_dma.h
index 61838a2c9..277ebf4d4 100644
--- a/os/hal/platforms/STM32F0xx/stm32_dma.h
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.h
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/os/hal/platforms/STM32F0xx/stm32_isr.h b/os/hal/platforms/STM32F0xx/stm32_isr.h
index 2332ea0e8..745885f41 100644
--- a/os/hal/platforms/STM32F0xx/stm32_isr.h
+++ b/os/hal/platforms/STM32F0xx/stm32_isr.h
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
diff --git a/os/hal/platforms/STM32F0xx/stm32_rcc.h b/os/hal/platforms/STM32F0xx/stm32_rcc.h
index 2ff8cea35..88e47f2c0 100644
--- a/os/hal/platforms/STM32F0xx/stm32_rcc.h
+++ b/os/hal/platforms/STM32F0xx/stm32_rcc.h
@@ -1,21 +1,17 @@
 /*
-    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
-                 2011,2012,2013 Giovanni Di Sirio.
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
 
-    This file is part of ChibiOS/RT.
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
 
-    ChibiOS/RT is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
+        http://www.apache.org/licenses/LICENSE-2.0
 
-    ChibiOS/RT is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
 */
 
 /**
-- 
cgit v1.2.3


From b0b6214a6253eedb438e003dcfd408d52ed0a6c4 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 31 Mar 2013 10:37:06 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5522
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/hal_lld.h        | 210 +---------------------------
 os/hal/platforms/STM32F0xx/stm32_isr.h      |  34 +++--
 os/hal/platforms/STM32F0xx/stm32_registry.h | 198 ++++++++++++++++++++++++++
 3 files changed, 221 insertions(+), 221 deletions(-)
 create mode 100644 os/hal/platforms/STM32F0xx/stm32_registry.h

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.h b/os/hal/platforms/STM32F0xx/hal_lld.h
index 48a3be448..dcff57a5c 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.h
+++ b/os/hal/platforms/STM32F0xx/hal_lld.h
@@ -37,6 +37,7 @@
 #define _HAL_LLD_H_
 
 #include "stm32.h"
+#include "stm32_registry.h"
 
 /*===========================================================================*/
 /* Driver constants.                                                         */
@@ -208,215 +209,6 @@
 #define STM32_ADCSW_PCLK        (1 << 8)    /**< ADC clock is PCLK/2|4.     */
 /** @} */
 
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    STM32F0xx capabilities
- * @{
- */
-/* ADC attributes.*/
-#define STM32_HAS_ADC1          TRUE
-#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 1) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_ADC1_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC2          FALSE
-#define STM32_ADC2_DMA_MSK      0x00000000
-#define STM32_ADC2_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC3          FALSE
-#define STM32_ADC3_DMA_MSK      0x00000000
-#define STM32_ADC3_DMA_CHN      0x00000000
-
-#define STM32_HAS_ADC4          FALSE
-#define STM32_ADC4_DMA_MSK      0x00000000
-#define STM32_ADC4_DMA_CHN      0x00000000
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1          FALSE
-#define STM32_HAS_CAN2          FALSE
-#define STM32_CAN_MAX_FILTERS   0
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC           TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA      FALSE
-#define STM32_HAS_DMA1          TRUE
-#define STM32_HAS_DMA2          FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH           FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS 28
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA         TRUE
-#define STM32_HAS_GPIOB         TRUE
-#define STM32_HAS_GPIOC         TRUE
-#define STM32_HAS_GPIOD         TRUE
-#define STM32_HAS_GPIOE         FALSE
-#define STM32_HAS_GPIOF         TRUE
-#define STM32_HAS_GPIOG         FALSE
-#define STM32_HAS_GPIOH         FALSE
-#define STM32_HAS_GPIOI         FALSE
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1          TRUE
-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 3))
-#define STM32_I2C1_RX_DMA_CHN   0x00000000
-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 2))
-#define STM32_I2C1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C2          TRUE
-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_I2C2_RX_DMA_CHN   0x00000000
-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_I2C2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_I2C3          FALSE
-#define STM32_I2C3_RX_DMA_MSK   0
-#define STM32_I2C3_RX_DMA_CHN   0x00000000
-#define STM32_I2C3_TX_DMA_MSK   0
-#define STM32_I2C3_TX_DMA_CHN   0x00000000
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC           TRUE
-#define STM32_RTC_HAS_SUBSECONDS FALSE
-#define STM32_RTC_IS_CALENDAR   TRUE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO          FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1          TRUE
-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
-#define STM32_SPI1_RX_DMA_CHN   0x00000000
-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
-#define STM32_SPI1_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI2          TRUE
-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
-#define STM32_SPI2_RX_DMA_CHN   0x00000000
-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
-#define STM32_SPI2_TX_DMA_CHN   0x00000000
-
-#define STM32_HAS_SPI3          FALSE
-#define STM32_SPI3_RX_DMA_MSK   0
-#define STM32_SPI3_RX_DMA_CHN   0x00000000
-#define STM32_SPI3_TX_DMA_MSK   0
-#define STM32_SPI3_TX_DMA_CHN   0x00000000
-
-/* TIM attributes.*/
-#define STM32_HAS_TIM1          TRUE
-#define STM32_HAS_TIM2          TRUE
-#define STM32_HAS_TIM3          TRUE
-#define STM32_HAS_TIM4          FALSE
-#define STM32_HAS_TIM5          FALSE
-#define STM32_HAS_TIM6          TRUE
-#define STM32_HAS_TIM7          FALSE
-#define STM32_HAS_TIM8          FALSE
-#define STM32_HAS_TIM9          FALSE
-#define STM32_HAS_TIM10         FALSE
-#define STM32_HAS_TIM11         FALSE
-#define STM32_HAS_TIM12         FALSE
-#define STM32_HAS_TIM13         FALSE
-#define STM32_HAS_TIM14         TRUE
-#define STM32_HAS_TIM15         TRUE
-#define STM32_HAS_TIM16         TRUE
-#define STM32_HAS_TIM17         TRUE
-#define STM32_HAS_TIM18         FALSE
-#define STM32_HAS_TIM19         FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1        TRUE
-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART1_RX_DMA_CHN 0x00000000
-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |            \
-                                 STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART1_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART2        TRUE
-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
-#define STM32_USART2_RX_DMA_CHN 0x00000000
-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART2_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_USART3        FALSE
-#define STM32_USART3_RX_DMA_MSK 0
-#define STM32_USART3_RX_DMA_CHN 0x00000000
-#define STM32_USART3_TX_DMA_MSK 0
-#define STM32_USART3_TX_DMA_CHN 0x00000000
-
-#define STM32_HAS_UART4         FALSE
-#define STM32_UART4_RX_DMA_MSK  0
-#define STM32_UART4_RX_DMA_CHN  0x00000000
-#define STM32_UART4_TX_DMA_MSK  0
-#define STM32_UART4_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_UART5         FALSE
-#define STM32_UART5_RX_DMA_MSK  0
-#define STM32_UART5_RX_DMA_CHN  0x00000000
-#define STM32_UART5_TX_DMA_MSK  0
-#define STM32_UART5_TX_DMA_CHN  0x00000000
-
-#define STM32_HAS_USART6        FALSE
-#define STM32_USART6_RX_DMA_MSK 0
-#define STM32_USART6_RX_DMA_CHN 0x00000000
-#define STM32_USART6_TX_DMA_MSK 0
-#define STM32_USART6_TX_DMA_CHN 0x00000000
-
-/* USB attributes.*/
-#define STM32_HAS_USB           TRUE
-#define STM32_HAS_OTG1          FALSE
-#define STM32_HAS_OTG2          FALSE
-/** @} */
-
-/*===========================================================================*/
-/* Platform specific friendly IRQ names.                                     */
-/*===========================================================================*/
-
-/**
- * @name  IRQ VECTOR names
- * @{
- */
-#define WWDG_IRQHandler         Vector40    /**< Window Watchdog.           */
-#define PVD_IRQHandler          Vector44    /**< PVD through EXTI Line
-                                                 detect.                    */
-#define RTC_IRQHandler          Vector48    /**< RTC through EXTI Line
-                                                 Interrupt.                 */
-#define FLASH_IRQHandler        Vector4C    /**< Flash.                     */
-#define RCC_IRQHandler          Vector50    /**< RCC.                       */
-#define EXTI0_1_IRQHandler      Vector54    /**< EXTI Line 0..1.            */
-#define EXTI2_3_IRQHandler      Vector58    /**< EXTI Line 2..3.            */
-#define EXTI4_15_IRQHandler     Vector5C    /**< EXTI Line 4..15.           */
-#define TS_IRQHandler           Vector60    /**< TS.                        */
-#define DMA1_Ch1_IRQHandler     Vector64    /**< DMA1 Channel 1.            */
-#define DMA1_Ch2_3_IRQHandler   Vector68    /**< DMA1 Channels 2 and 3.     */
-#define DMA1_Ch4_5_IRQHandler   Vector6C    /**< DMA1 Channels 4 and 5.     */
-#define ADC1_COMP_IRQHandler    Vector70    /**< ADC1 comparators 1 and 2.  */
-#define TIM1_BRK_UP_TRG_COM_IRQHandler Vector74 /**< TIM1 common.           */
-#define TIM1_CC_IRQHandler      Vector78    /**< TIM1 Capture Compare.      */
-#define TIM2_IRQHandler         Vector7C    /**< TIM2.                      */
-#define TIM3_IRQHandler         Vector80    /**< TIM3.                      */
-#define TIM6_DAC_IRQHandler     Vector84    /**< TIM6 and DAC.              */
-#define TIM14_IRQHandler        Vector8C    /**< TIM14.                     */
-#define TIM15_IRQHandler        Vector90    /**< TIM15.                     */
-#define TIM16_IRQHandler        Vector94    /**< TIM16.                     */
-#define TIM17_IRQHandler        Vector98    /**< TIM17.                     */
-#define I2C1_IRQHandler         Vector9C    /**< I2C1.                      */
-#define I2C2_IRQHandler         VectorA0    /**< I2C2.                      */
-#define SPI1_IRQHandler         VectorA4    /**< SPI1.                      */
-#define SPI2_IRQHandler         VectorA8    /**< SPI2.                      */
-#define USART1_IRQHandler       VectorAC    /**< USART1.                    */
-#define USART2_IRQHandler       VectorB0    /**< USART2.                    */
-#define CEC_IRQHandler          VectorB8    /**< CEC.                       */
-/** @} */
-
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
diff --git a/os/hal/platforms/STM32F0xx/stm32_isr.h b/os/hal/platforms/STM32F0xx/stm32_isr.h
index 745885f41..52421a4d5 100644
--- a/os/hal/platforms/STM32F0xx/stm32_isr.h
+++ b/os/hal/platforms/STM32F0xx/stm32_isr.h
@@ -33,27 +33,37 @@
  * @name    ISR names and numbers remapping
  * @{
  */
+
+/*
+ * I2C units.
+ */
+#define STM32_I2C1_GLOBAL_HANDLER   Vector9C
+#define STM32_I2C1_GLOBAL_NUMBER    23
+
+#define STM32_I2C2_GLOBAL_HANDLER   VectorA0
+#define STM32_I2C2_GLOBAL_NUMBER    24
+
 /*
  * TIM units.
  */
-#define STM32_TIM1_UP_HANDLER       TIM1_BRK_UP_TRG_COM_IRQHandler
-#define STM32_TIM1_CC_HANDLER       TIM1_CC_IRQHandler
-#define STM32_TIM2_HANDLER          TIM2_IRQHandler
-#define STM32_TIM3_HANDLER          TIM3_IRQHandler
+#define STM32_TIM1_UP_HANDLER       Vector74
+#define STM32_TIM1_CC_HANDLER       Vector78
+#define STM32_TIM2_HANDLER          Vector7C
+#define STM32_TIM3_HANDLER          Vector80
 
-#define STM32_TIM1_UP_NUMBER        TIM1_BRK_UP_TRG_COM_IRQn
-#define STM32_TIM1_CC_NUMBER        TIM1_CC_IRQn
-#define STM32_TIM2_NUMBER           TIM2_IRQn
-#define STM32_TIM3_NUMBER           TIM3_IRQn
+#define STM32_TIM1_UP_NUMBER        13
+#define STM32_TIM1_CC_NUMBER        14
+#define STM32_TIM2_NUMBER           15
+#define STM32_TIM3_NUMBER           16
 
 /*
  * USART units.
  */
-#define STM32_USART1_HANDLER        USART1_IRQHandler
-#define STM32_USART2_HANDLER        USART2_IRQHandler
+#define STM32_USART1_HANDLER        VectorAC
+#define STM32_USART2_HANDLER        VectorB0
 
-#define STM32_USART1_NUMBER         USART1_IRQn
-#define STM32_USART2_NUMBER         USART2_IRQn
+#define STM32_USART1_NUMBER         27
+#define STM32_USART2_NUMBER         28
 /** @} */
 
 /*===========================================================================*/
diff --git a/os/hal/platforms/STM32F0xx/stm32_registry.h b/os/hal/platforms/STM32F0xx/stm32_registry.h
new file mode 100644
index 000000000..ccef92730
--- /dev/null
+++ b/os/hal/platforms/STM32F0xx/stm32_registry.h
@@ -0,0 +1,198 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F0xx/stm32_registry.h
+ * @brief   STM32F0xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _STM32_REGISTRY_H_
+#define _STM32_REGISTRY_H_
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @name    STM32F0xx capabilities
+ * @{
+ */
+/* ADC attributes.*/
+#define STM32_HAS_ADC1          TRUE
+#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 1) |            \
+                                 STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_ADC1_DMA_CHN      0x00000000
+
+#define STM32_HAS_ADC2          FALSE
+#define STM32_ADC2_DMA_MSK      0x00000000
+#define STM32_ADC2_DMA_CHN      0x00000000
+
+#define STM32_HAS_ADC3          FALSE
+#define STM32_ADC3_DMA_MSK      0x00000000
+#define STM32_ADC3_DMA_CHN      0x00000000
+
+#define STM32_HAS_ADC4          FALSE
+#define STM32_ADC4_DMA_MSK      0x00000000
+#define STM32_ADC4_DMA_CHN      0x00000000
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1          FALSE
+#define STM32_HAS_CAN2          FALSE
+#define STM32_CAN_MAX_FILTERS   0
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC           TRUE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA      FALSE
+#define STM32_HAS_DMA1          TRUE
+#define STM32_HAS_DMA2          FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH           FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 28
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA         TRUE
+#define STM32_HAS_GPIOB         TRUE
+#define STM32_HAS_GPIOC         TRUE
+#define STM32_HAS_GPIOD         TRUE
+#define STM32_HAS_GPIOE         FALSE
+#define STM32_HAS_GPIOF         TRUE
+#define STM32_HAS_GPIOG         FALSE
+#define STM32_HAS_GPIOH         FALSE
+#define STM32_HAS_GPIOI         FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1          TRUE
+#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 3))
+#define STM32_I2C1_RX_DMA_CHN   0x00000000
+#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 2))
+#define STM32_I2C1_TX_DMA_CHN   0x00000000
+
+#define STM32_HAS_I2C2          TRUE
+#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_I2C2_RX_DMA_CHN   0x00000000
+#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_I2C2_TX_DMA_CHN   0x00000000
+
+#define STM32_HAS_I2C3          FALSE
+#define STM32_I2C3_RX_DMA_MSK   0
+#define STM32_I2C3_RX_DMA_CHN   0x00000000
+#define STM32_I2C3_TX_DMA_MSK   0
+#define STM32_I2C3_TX_DMA_CHN   0x00000000
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC           TRUE
+#define STM32_RTC_HAS_SUBSECONDS FALSE
+#define STM32_RTC_IS_CALENDAR   TRUE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO          FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1          TRUE
+#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)
+#define STM32_SPI1_RX_DMA_CHN   0x00000000
+#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)
+#define STM32_SPI1_TX_DMA_CHN   0x00000000
+
+#define STM32_HAS_SPI2          TRUE
+#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)
+#define STM32_SPI2_RX_DMA_CHN   0x00000000
+#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)
+#define STM32_SPI2_TX_DMA_CHN   0x00000000
+
+#define STM32_HAS_SPI3          FALSE
+#define STM32_SPI3_RX_DMA_MSK   0
+#define STM32_SPI3_RX_DMA_CHN   0x00000000
+#define STM32_SPI3_TX_DMA_MSK   0
+#define STM32_SPI3_TX_DMA_CHN   0x00000000
+
+/* TIM attributes.*/
+#define STM32_HAS_TIM1          TRUE
+#define STM32_HAS_TIM2          TRUE
+#define STM32_HAS_TIM3          TRUE
+#define STM32_HAS_TIM4          FALSE
+#define STM32_HAS_TIM5          FALSE
+#define STM32_HAS_TIM6          TRUE
+#define STM32_HAS_TIM7          FALSE
+#define STM32_HAS_TIM8          FALSE
+#define STM32_HAS_TIM9          FALSE
+#define STM32_HAS_TIM10         FALSE
+#define STM32_HAS_TIM11         FALSE
+#define STM32_HAS_TIM12         FALSE
+#define STM32_HAS_TIM13         FALSE
+#define STM32_HAS_TIM14         TRUE
+#define STM32_HAS_TIM15         TRUE
+#define STM32_HAS_TIM16         TRUE
+#define STM32_HAS_TIM17         TRUE
+#define STM32_HAS_TIM18         FALSE
+#define STM32_HAS_TIM19         FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1        TRUE
+#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |            \
+                                 STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART1_RX_DMA_CHN 0x00000000
+#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |            \
+                                 STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART1_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART2        TRUE
+#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
+#define STM32_USART2_RX_DMA_CHN 0x00000000
+#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
+#define STM32_USART2_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_USART3        FALSE
+#define STM32_USART3_RX_DMA_MSK 0
+#define STM32_USART3_RX_DMA_CHN 0x00000000
+#define STM32_USART3_TX_DMA_MSK 0
+#define STM32_USART3_TX_DMA_CHN 0x00000000
+
+#define STM32_HAS_UART4         FALSE
+#define STM32_UART4_RX_DMA_MSK  0
+#define STM32_UART4_RX_DMA_CHN  0x00000000
+#define STM32_UART4_TX_DMA_MSK  0
+#define STM32_UART4_TX_DMA_CHN  0x00000000
+
+#define STM32_HAS_UART5         FALSE
+#define STM32_UART5_RX_DMA_MSK  0
+#define STM32_UART5_RX_DMA_CHN  0x00000000
+#define STM32_UART5_TX_DMA_MSK  0
+#define STM32_UART5_TX_DMA_CHN  0x00000000
+
+#define STM32_HAS_USART6        FALSE
+#define STM32_USART6_RX_DMA_MSK 0
+#define STM32_USART6_RX_DMA_CHN 0x00000000
+#define STM32_USART6_TX_DMA_MSK 0
+#define STM32_USART6_TX_DMA_CHN 0x00000000
+
+/* USB attributes.*/
+#define STM32_HAS_USB           TRUE
+#define STM32_HAS_OTG1          FALSE
+#define STM32_HAS_OTG2          FALSE
+/** @} */
+
+#endif /* _STM32_REGISTRY_H_ */
+
+/** @} */
-- 
cgit v1.2.3


From c02afef7dfff3e1fd2645c9e94947342e0ee35ad Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sun, 14 Apr 2013 09:01:19 +0000
Subject: Fixed bug #400.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5589 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/adc_lld.c     |  2 +-
 os/hal/platforms/STM32F0xx/ext_lld_isr.c | 14 +++++++-------
 os/hal/platforms/STM32F0xx/stm32_dma.c   |  6 +++---
 3 files changed, 11 insertions(+), 11 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/adc_lld.c b/os/hal/platforms/STM32F0xx/adc_lld.c
index 2fad88cda..5fa419679 100644
--- a/os/hal/platforms/STM32F0xx/adc_lld.c
+++ b/os/hal/platforms/STM32F0xx/adc_lld.c
@@ -102,7 +102,7 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
  *
  * @isr
  */
-CH_IRQ_HANDLER(ADC1_COMP_IRQHandler) {
+CH_IRQ_HANDLER(Vector70) {
   uint32_t isr;
 
   CH_IRQ_PROLOGUE();
diff --git a/os/hal/platforms/STM32F0xx/ext_lld_isr.c b/os/hal/platforms/STM32F0xx/ext_lld_isr.c
index d4fd06155..afccfdd8c 100644
--- a/os/hal/platforms/STM32F0xx/ext_lld_isr.c
+++ b/os/hal/platforms/STM32F0xx/ext_lld_isr.c
@@ -50,11 +50,11 @@
 /*===========================================================================*/
 
 /**
- * @brief   EXTI[0] interrupt handler.
+ * @brief   EXTI[0]...EXTI[1] interrupt handler.
  *
  * @isr
  */
-CH_IRQ_HANDLER(EXTI0_1_IRQHandler) {
+CH_IRQ_HANDLER(Vector54) {
   uint32_t pr;
 
   CH_IRQ_PROLOGUE();
@@ -70,11 +70,11 @@ CH_IRQ_HANDLER(EXTI0_1_IRQHandler) {
 }
 
 /**
- * @brief   EXTI[1] interrupt handler.
+ * @brief   EXTI[2]...EXTI[3] interrupt handler.
  *
  * @isr
  */
-CH_IRQ_HANDLER(EXTI2_3_IRQHandler) {
+CH_IRQ_HANDLER(Vector58) {
   uint32_t pr;
 
   CH_IRQ_PROLOGUE();
@@ -94,7 +94,7 @@ CH_IRQ_HANDLER(EXTI2_3_IRQHandler) {
  *
  * @isr
  */
-CH_IRQ_HANDLER(EXTI4_15_IRQHandler) {
+CH_IRQ_HANDLER(Vector5C) {
   uint32_t pr;
 
   CH_IRQ_PROLOGUE();
@@ -136,7 +136,7 @@ CH_IRQ_HANDLER(EXTI4_15_IRQHandler) {
  *
  * @isr
  */
-CH_IRQ_HANDLER(PVD_IRQHandler) {
+CH_IRQ_HANDLER(Vector44) {
 
   CH_IRQ_PROLOGUE();
 
@@ -151,7 +151,7 @@ CH_IRQ_HANDLER(PVD_IRQHandler) {
  *
  * @isr
  */
-CH_IRQ_HANDLER(RTC_IRQHandler) {
+CH_IRQ_HANDLER(Vector48) {
 
   CH_IRQ_PROLOGUE();
 
diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.c b/os/hal/platforms/STM32F0xx/stm32_dma.c
index 44f10cbf6..2305d952d 100644
--- a/os/hal/platforms/STM32F0xx/stm32_dma.c
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.c
@@ -109,7 +109,7 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
  *
  * @isr
  */
-CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
+CH_IRQ_HANDLER(Vector64) {
   uint32_t flags;
 
   CH_IRQ_PROLOGUE();
@@ -127,7 +127,7 @@ CH_IRQ_HANDLER(DMA1_Ch1_IRQHandler) {
  *
  * @isr
  */
-CH_IRQ_HANDLER(DMA1_Ch2_3_IRQHandler) {
+CH_IRQ_HANDLER(Vector68) {
   uint32_t flags;
 
   CH_IRQ_PROLOGUE();
@@ -156,7 +156,7 @@ CH_IRQ_HANDLER(DMA1_Ch2_3_IRQHandler) {
  *
  * @isr
  */
-CH_IRQ_HANDLER(DMA1_Ch4_5_IRQHandler) {
+CH_IRQ_HANDLER(Vector6C) {
   uint32_t flags;
 
   CH_IRQ_PROLOGUE();
-- 
cgit v1.2.3


From eff9b74c9c3714a8aec6a61f86e84f38edfd213a Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Sat, 11 May 2013 07:05:28 +0000
Subject: Fixed bug #409.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5703 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/platforms/STM32F0xx/hal_lld.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os/hal/platforms/STM32F0xx')

diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
index 7c5bdce8e..debc51ea3 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -101,7 +101,7 @@ void hal_lld_init(void) {
 
   /* Reset of all peripherals.*/
   rccResetAPB1(0xFFFFFFFF);
-  rccResetAPB2(!RCC_APB2RSTR_DBGMCURST);
+  rccResetAPB2(~RCC_APB2RSTR_DBGMCURST);
 
   /* SysTick initialization using the system clock.*/
   SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;
-- 
cgit v1.2.3