From 01a811d27f05c73904200aaeaf618ed657b65283 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 18 May 2012 15:29:20 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4206 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/stm32_rcc.h | 546 +++++++++++++++++++++++++++++++++ 1 file changed, 546 insertions(+) create mode 100644 os/hal/platforms/STM32F0xx/stm32_rcc.h (limited to 'os/hal/platforms/STM32F0xx/stm32_rcc.h') diff --git a/os/hal/platforms/STM32F0xx/stm32_rcc.h b/os/hal/platforms/STM32F0xx/stm32_rcc.h new file mode 100644 index 000000000..d10aa6de7 --- /dev/null +++ b/os/hal/platforms/STM32F0xx/stm32_rcc.h @@ -0,0 +1,546 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file STM32F0xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32f0xx.h. + * + * @addtogroup STM32F0xx_RCC + * @{ + */ + +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB(mask, lp) { \ + RCC->AHBENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB bus. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] mask AHB peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB(mask, lp) { \ + RCC->AHBENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB bus. + * + * @param[in] mask AHB peripherals mask + * + * @api + */ +#define rccResetAHB(mask) { \ + RCC->AHBRSTR |= (mask); \ + RCC->AHBRSTR = 0; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) +/** @} */ + +/** + * @name DMA peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * @note Not supported in this family, does nothing. + * + * @api + */ +#define rccResetDMA1() +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ -- cgit v1.2.3 From 75a75a7ddcdc0ea45941ecc7593900824a088715 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 2 Feb 2013 10:01:27 +0000 Subject: Fixed bug 3602150. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5096 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/stm32_rcc.h | 54 ++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'os/hal/platforms/STM32F0xx/stm32_rcc.h') diff --git a/os/hal/platforms/STM32F0xx/stm32_rcc.h b/os/hal/platforms/STM32F0xx/stm32_rcc.h index d10aa6de7..2db4b26fa 100644 --- a/os/hal/platforms/STM32F0xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F0xx/stm32_rcc.h @@ -528,6 +528,60 @@ * @api */ #define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the CRC peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp) + +/** + * @brief Disables the CRC peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCRC(lp) rccDisableAHB(RCC_AHBENR_CRCEN, lp) + +/** + * @brief Resets the CRC peripheral. + * + * @api + */ +#define rccResetCRC() rccResetAHB(RCC_AHBRSTR_CRCRST) + +/** + * @brief Enables the WWDG peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableWWDG(lp) rccEnableAPB1(RCC_APB1ENR_WWDGEN, lp) + +/** + * @brief Disables the WWDG peripheral clock. + * @note The @p lp parameter is ignored in this family. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableWWDG(lp) rccDisableAPB1(RCC_APB1ENR_WWDGEN, lp) + +/** + * @brief Resets the WWDG peripheral. + * + * @api + */ +#define rccResetWWDG() rccResetAPB1(RCC_APB1RSTR_WWDGRST) /** @} */ /*===========================================================================*/ -- cgit v1.2.3 From 184a71345c6a36a9a8664eda8fbcc3ea728267a8 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 2 Feb 2013 10:58:09 +0000 Subject: Updated license years. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5102 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/stm32_rcc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'os/hal/platforms/STM32F0xx/stm32_rcc.h') diff --git a/os/hal/platforms/STM32F0xx/stm32_rcc.h b/os/hal/platforms/STM32F0xx/stm32_rcc.h index 2db4b26fa..2ff8cea35 100644 --- a/os/hal/platforms/STM32F0xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F0xx/stm32_rcc.h @@ -1,6 +1,6 @@ /* ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012 Giovanni Di Sirio. + 2011,2012,2013 Giovanni Di Sirio. This file is part of ChibiOS/RT. -- cgit v1.2.3 From 853216256ad4cdacf5f94edb7d6b738c6be165a1 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 30 Mar 2013 10:32:37 +0000 Subject: Relicensing parts of the tree under the Apache 2.0 license. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5521 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32F0xx/stm32_rcc.h | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) (limited to 'os/hal/platforms/STM32F0xx/stm32_rcc.h') diff --git a/os/hal/platforms/STM32F0xx/stm32_rcc.h b/os/hal/platforms/STM32F0xx/stm32_rcc.h index 2ff8cea35..88e47f2c0 100644 --- a/os/hal/platforms/STM32F0xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F0xx/stm32_rcc.h @@ -1,21 +1,17 @@ /* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - This file is part of ChibiOS/RT. + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. + http://www.apache.org/licenses/LICENSE-2.0 - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. */ /** -- cgit v1.2.3