From abbc1097778c5718dd314af045f40b037ccb4cb5 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 20 Aug 2013 12:33:49 +0000
Subject: git-svn-id:
 svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6188
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/STM32F0xx/stm32_dma.c | 29 ++++++++++++++---------------
 1 file changed, 14 insertions(+), 15 deletions(-)

(limited to 'os/hal/platforms/STM32F0xx/stm32_dma.c')

diff --git a/os/hal/platforms/STM32F0xx/stm32_dma.c b/os/hal/platforms/STM32F0xx/stm32_dma.c
index 2305d952d..623c9d11b 100644
--- a/os/hal/platforms/STM32F0xx/stm32_dma.c
+++ b/os/hal/platforms/STM32F0xx/stm32_dma.c
@@ -29,7 +29,6 @@
  * @{
  */
 
-#include "ch.h"
 #include "hal.h"
 
 /* The following macro is only defined if some driver requiring DMA services
@@ -109,17 +108,17 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
  *
  * @isr
  */
-CH_IRQ_HANDLER(Vector64) {
+OSAL_IRQ_HANDLER(Vector64) {
   uint32_t flags;
 
-  CH_IRQ_PROLOGUE();
+  OSAL_IRQ_PROLOGUE();
 
   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
   DMA1->IFCR = STM32_DMA_ISR_MASK << 0;
   if (dma_isr_redir[0].dma_func)
     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
 
-  CH_IRQ_EPILOGUE();
+  OSAL_IRQ_EPILOGUE();
 }
 
 /**
@@ -127,10 +126,10 @@ CH_IRQ_HANDLER(Vector64) {
  *
  * @isr
  */
-CH_IRQ_HANDLER(Vector68) {
+OSAL_IRQ_HANDLER(Vector68) {
   uint32_t flags;
 
-  CH_IRQ_PROLOGUE();
+  OSAL_IRQ_PROLOGUE();
 
   /* Check on channel 2.*/
   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
@@ -148,7 +147,7 @@ CH_IRQ_HANDLER(Vector68) {
       dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
   }
 
-  CH_IRQ_EPILOGUE();
+  OSAL_IRQ_EPILOGUE();
 }
 
 /**
@@ -156,10 +155,10 @@ CH_IRQ_HANDLER(Vector68) {
  *
  * @isr
  */
-CH_IRQ_HANDLER(Vector6C) {
+OSAL_IRQ_HANDLER(Vector6C) {
   uint32_t flags;
 
-  CH_IRQ_PROLOGUE();
+  OSAL_IRQ_PROLOGUE();
 
   /* Check on channel 4.*/
   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
@@ -177,7 +176,7 @@ CH_IRQ_HANDLER(Vector6C) {
       dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
   }
 
-  CH_IRQ_EPILOGUE();
+  OSAL_IRQ_EPILOGUE();
 }
 
 /*===========================================================================*/
@@ -229,7 +228,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
                          stm32_dmaisr_t func,
                          void *param) {
 
-  chDbgCheck(dmastp != NULL, "dmaStreamAllocate");
+  osalDbgCheck(dmastp != NULL);
 
   /* Checks if the stream is already taken.*/
   if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
@@ -250,7 +249,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
 
   /* Enables the associated IRQ vector if a callback is defined.*/
   if (func != NULL)
-    nvicEnableVector(dmastp->vector, CORTEX_PRIORITY_MASK(priority));
+    nvicEnableVector(dmastp->vector, priority);
 
   return FALSE;
 }
@@ -270,11 +269,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
  */
 void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
 
-  chDbgCheck(dmastp != NULL, "dmaStreamRelease");
+  osalDbgCheck(dmastp != NULL);
 
   /* Check if the streams is not taken.*/
-  chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
-              "dmaStreamRelease(), #1", "not allocated");
+  osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
+                "not allocated");
 
   /* Disables the associated IRQ vector.*/
   nvicDisableVector(dmastp->vector);
-- 
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