From ac6372224526c8de6f6a040d33e0309c501df73d Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 15 Jan 2011 08:01:07 +0000 Subject: Added OTG clock setting to the STM32 HAL. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2641 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/STM32/hal_lld.c | 9 +++++++-- os/hal/platforms/STM32/hal_lld.h | 14 +++++++------- os/hal/platforms/STM32/hal_lld_f105_f107.h | 18 ++++++++++++++++++ 3 files changed, 32 insertions(+), 9 deletions(-) (limited to 'os/hal/platforms/STM32') diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c index df99c3b53..97fbabcfc 100644 --- a/os/hal/platforms/STM32/hal_lld.c +++ b/os/hal/platforms/STM32/hal_lld.c @@ -180,8 +180,13 @@ void stm32_clock_init(void) { #endif /* Clock settings.*/ - RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC | - STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; +#if STM32_HAS_OTG1 + RCC->CFGR = STM32_MCO | STM32_OTGFSPRE | STM32_PLLMUL | STM32_PLLSRC | + STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; +#else + RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLSRC | + STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; +#endif /* Flash setup and final clock selection. */ FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */ diff --git a/os/hal/platforms/STM32/hal_lld.h b/os/hal/platforms/STM32/hal_lld.h index 9cca9401f..0abac770c 100644 --- a/os/hal/platforms/STM32/hal_lld.h +++ b/os/hal/platforms/STM32/hal_lld.h @@ -125,7 +125,7 @@ #define STM32_HAS_UART4 FALSE #define STM32_HAS_USB FALSE -#define STM32_HAS_USBOTG FALSE +#define STM32_HAS_OTG1 FALSE #elif defined(STM32F10X_MD_VL) /* @@ -192,7 +192,7 @@ #define STM32_HAS_UART4 FALSE #define STM32_HAS_USB FALSE -#define STM32_HAS_USBOTG FALSE +#define STM32_HAS_OTG1 FALSE #elif defined(STM32F10X_LD) /* @@ -259,7 +259,7 @@ #define STM32_HAS_UART4 FALSE #define STM32_HAS_USB FALSE -#define STM32_HAS_USBOTG FALSE +#define STM32_HAS_OTG1 FALSE #elif defined(STM32F10X_MD) /* @@ -326,7 +326,7 @@ #define STM32_HAS_UART4 FALSE #define STM32_HAS_USB TRUE -#define STM32_HAS_USBOTG FALSE +#define STM32_HAS_OTG1 FALSE #elif defined(STM32F10X_HD) /* @@ -393,7 +393,7 @@ #define STM32_HAS_UART4 TRUE #define STM32_HAS_USB TRUE -#define STM32_HAS_USBOTG FALSE +#define STM32_HAS_OTG1 FALSE #elif defined(STM32F10X_XD) /* @@ -460,7 +460,7 @@ #define STM32_HAS_UART4 TRUE #define STM32_HAS_USB TRUE -#define STM32_HAS_USBOTG FALSE +#define STM32_HAS_OTG1 FALSE #elif defined(STM32F10X_CL) /* @@ -527,7 +527,7 @@ #define STM32_HAS_UART4 TRUE #define STM32_HAS_USB FALSE -#define STM32_HAS_USBOTG TRUE +#define STM32_HAS_OTG1 TRUE #else #error "unspecified, unsupported or invalid STM32 platform" diff --git a/os/hal/platforms/STM32/hal_lld_f105_f107.h b/os/hal/platforms/STM32/hal_lld_f105_f107.h index 8345917cc..d4477e705 100644 --- a/os/hal/platforms/STM32/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32/hal_lld_f105_f107.h @@ -276,6 +276,13 @@ #define STM32_ADCPRE STM32_ADCPRE_DIV4 #endif +/** + * @brief OTG prescaler initialization. + */ +#if !defined(STM32_OTGFSPRE) || defined(__DOXYGEN__) +#define STM32_OTGFSPRE STM32_OTGFSPRE_DIV3 +#endif + /** * @brief MCO pin setting. */ @@ -504,6 +511,17 @@ #error "STM32_ADCCLK exceeding maximum frequency (14MHz)" #endif +/** + * @brief OTG frequency. + */ +#if (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV3) || defined(__DOXYGEN__) +#define STM32_OTGFSCLK ((STM32_PLLCLKOUT * 2) / 3) +#elif (STM32_OTGFSPRE == STM32_OTGFSPRE_DIV2) +#define STM32_OTGFSCLK STM32_PLLCLKOUT +#else +#error "invalid STM32_OTGFSPRE value specified" +#endif + /** * @brief Timers 2, 3, 4, 5, 6, 7 clock. */ -- cgit v1.2.3