From c57e3842293e0396bfa7653428dc81585e7717de Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 19 Nov 2012 11:50:14 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4829 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/SPC560Pxx/hal_lld.c | 16 ++++++++-------- os/hal/platforms/SPC560Pxx/hal_lld.h | 36 ++++++++++++++++++------------------ 2 files changed, 26 insertions(+), 26 deletions(-) (limited to 'os/hal/platforms/SPC560Pxx') diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.c b/os/hal/platforms/SPC560Pxx/hal_lld.c index de1467e97..5d3402703 100644 --- a/os/hal/platforms/SPC560Pxx/hal_lld.c +++ b/os/hal/platforms/SPC560Pxx/hal_lld.c @@ -79,7 +79,7 @@ void hal_lld_init(void) { /* The system is switched to the RUN0 mode, the default for normal operations.*/ - if (halSPC560PSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) + if (halSPCSetRunMode(SPC5_RUNMODE_RUN0) == CH_FAILED) chSysHalt(); /* INTC initialization, software vector mode, 4 bytes vectors, starting @@ -92,9 +92,9 @@ void hal_lld_init(void) { to run in DRUN,RUN0...RUN3 and HALT0 modes, the clock is gated in other modes.*/ INTC.PSR[127].R = SPC5_PIT3_IRQ_PRIORITY; - halSPC560PSetPeripheralClockMode(92, + halSPCSetPeripheralClockMode(92, SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2)); - reg = halSPC560PGetSystemClock() / CH_FREQUENCY - 1; + reg = halSPCGetSystemClock() / CH_FREQUENCY - 1; PIT.PITMCR.R = 1; /* PIT clock enabled, stop while debugging. */ PIT.CH[3].LDVAL.R = reg; PIT.CH[3].CVAL.R = reg; @@ -110,7 +110,7 @@ void hal_lld_init(void) { * * @special */ -void spc560p_clock_init(void) { +void spc_clock_init(void) { /* Waiting for IRC stabilization before attempting anything else.*/ while (!ME.GS.B.S_RC) @@ -166,7 +166,7 @@ void spc560p_clock_init(void) { /* Switches again to DRUN mode (current mode) in order to update the settings.*/ - if (halSPC560PSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) + if (halSPCSetRunMode(SPC5_RUNMODE_DRUN) == CH_FAILED) chSysHalt(); /* CFLASH settings calculated for a maximum clock of 64MHz.*/ @@ -187,7 +187,7 @@ void spc560p_clock_init(void) { * @retval CH_SUCCESS if the switch operation has been completed. * @retval CH_FAILED if the switch operation failed. */ -bool_t halSPC560PSetRunMode(spc560prunmode_t mode) { +bool_t halSPCSetRunMode(spc560prunmode_t mode) { /* Starts a transition process.*/ ME.MCTL.R = SPC5_ME_MCTL_MODE(mode) | SPC5_ME_MCTL_KEY; @@ -216,7 +216,7 @@ bool_t halSPC560PSetRunMode(spc560prunmode_t mode) { * * @notapi */ -void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl) { +void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl) { uint32_t mode; ME.PCTL[n].R = pctl; @@ -231,7 +231,7 @@ void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl) { * * @return The system clock in Hertz. */ -uint32_t halSPC560PGetSystemClock(void) { +uint32_t halSPCGetSystemClock(void) { uint32_t sysclk; sysclk = ME.GS.B.S_SYSCLK; diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.h b/os/hal/platforms/SPC560Pxx/hal_lld.h index a4e439fe9..7095cf0c4 100644 --- a/os/hal/platforms/SPC560Pxx/hal_lld.h +++ b/os/hal/platforms/SPC560Pxx/hal_lld.h @@ -136,15 +136,15 @@ * @{ */ #define SPC5_ME_ME_RESET (1U << 0) -#define SPC5_ME_ME_TEST (2U << 0) -#define SPC5_ME_ME_SAFE (4U << 0) -#define SPC5_ME_ME_DRUN (8U << 0) -#define SPC5_ME_ME_RUN0 (16U << 0) -#define SPC5_ME_ME_RUN1 (32U << 0) -#define SPC5_ME_ME_RUN2 (64U << 0) -#define SPC5_ME_ME_RUN3 (128U << 0) -#define SPC5_ME_ME_HALT0 (256U << 0) -#define SPC5_ME_ME_STOP0 (1024U << 0) +#define SPC5_ME_ME_TEST (1U << 1) +#define SPC5_ME_ME_SAFE (1U << 2) +#define SPC5_ME_ME_DRUN (1U << 3) +#define SPC5_ME_ME_RUN0 (1U << 4) +#define SPC5_ME_ME_RUN1 (1U << 5) +#define SPC5_ME_ME_RUN2 (1U << 6) +#define SPC5_ME_ME_RUN3 (1U << 7) +#define SPC5_ME_ME_HALT0 (1U << 8) +#define SPC5_ME_ME_STOP0 (1U << 10) /** @} */ /** @@ -153,11 +153,11 @@ */ #define SPC5_ME_MC_SYSCLK_MASK (15U << 0) #define SPC5_ME_MC_SYSCLK(n) ((n) << 0) -#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0) -#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2) -#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4) -#define SPC5_ME_MC_SYSCLK_FMPLL1 SPC5_ME_MC_SYSCLK(5) -#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15) +#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0) +#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2) +#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4) +#define SPC5_ME_MC_SYSCLK_FMPLL1 SPC5_ME_MC_SYSCLK(5) +#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15) #define SPC5_ME_MC_IRCON (1U << 4) #define SPC5_ME_MC_XOSC0ON (1U << 5) #define SPC5_ME_MC_PLL0ON (1U << 6) @@ -720,11 +720,11 @@ typedef enum { extern "C" { #endif void hal_lld_init(void); - void spc560p_clock_init(void); - bool_t halSPC560PSetRunMode(spc560prunmode_t mode); - void halSPC560PSetPeripheralClockMode(uint32_t n, uint32_t pctl); + void spc_clock_init(void); + bool_t halSPCSetRunMode(spc560prunmode_t mode); + void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl); #if !SPC5_NO_INIT - uint32_t halSPC560PGetSystemClock(void); + uint32_t halSPCGetSystemClock(void); #endif #ifdef __cplusplus } -- cgit v1.2.3