From 9c15492e2d30c70c95e3b7f3b42f7d86bb24f2d6 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 19 Feb 2013 10:23:33 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5257
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/SPC560BCxx/hal_lld.c           |  5 +++
 os/hal/platforms/SPC560BCxx/hal_lld.h           | 54 +++++++++++++++++++++++++
 os/hal/platforms/SPC560BCxx/spc560bc_registry.h |  4 ++
 3 files changed, 63 insertions(+)

(limited to 'os/hal/platforms/SPC560BCxx')

diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.c b/os/hal/platforms/SPC560BCxx/hal_lld.c
index aa4c7f538..c24eb1ee1 100644
--- a/os/hal/platforms/SPC560BCxx/hal_lld.c
+++ b/os/hal/platforms/SPC560BCxx/hal_lld.c
@@ -144,6 +144,11 @@ void spc_clock_init(void) {
   CGM.OSC_CTL.B.OSCBYP = TRUE;
 #endif /* SPC5_OSC_BYPASS */
 
+  /* Setting the various dividers and source selectors.*/
+  CGM.SC_DC[0].R    = SPC5_CGM_SC_DC0;
+  CGM.SC_DC[1].R    = SPC5_CGM_SC_DC1;
+  CGM.SC_DC[2].R    = SPC5_CGM_SC_DC2;
+
   /* Initialization of the FMPLLs settings.*/
   CGM.FMPLL_CR.R = SPC5_FMPLL0_ODF |
                    ((SPC5_FMPLL0_IDF_VALUE - 1) << 26) |
diff --git a/os/hal/platforms/SPC560BCxx/hal_lld.h b/os/hal/platforms/SPC560BCxx/hal_lld.h
index 701e2f4a7..d92fb53bf 100644
--- a/os/hal/platforms/SPC560BCxx/hal_lld.h
+++ b/os/hal/platforms/SPC560BCxx/hal_lld.h
@@ -283,6 +283,30 @@
 #define SPC5_FMPLL0_ODF                     SPC5_FMPLL_ODF_DIV4
 #endif
 
+/**
+ * @brief   Peripherals Set 1 clock divider value.
+ * @note    Zero means disabled clock.
+ */
+#if !defined(SPC5_PHERIPERAL1_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PHERIPERAL1_CLK_DIV_VALUE      2
+#endif
+
+/**
+ * @brief   Peripherals Set 2 clock divider value.
+ * @note    Zero means disabled clock.
+ */
+#if !defined(SPC5_PHERIPERAL2_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PHERIPERAL2_CLK_DIV_VALUE      2
+#endif
+
+/**
+ * @brief   Peripherals Set 3 clock divider value.
+ * @note    Zero means disabled clock.
+ */
+#if !defined(SPC5_PHERIPERAL3_CLK_DIV_VALUE) || defined(__DOXYGEN__)
+#define SPC5_PHERIPERAL3_CLK_DIV_VALUE      2
+#endif
+
 /**
  * @brief   Active run modes in ME_ME register.
  * @note    Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
@@ -678,6 +702,36 @@
 #error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
 #endif
 
+/* Check on the peripherals set 1 clock divider settings.*/
+#if SPC5_PHERIPERAL1_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC0         0
+#elif (SPC5_PHERIPERAL1_CLK_DIV_VALUE >= 1) &&                              \
+      (SPC5_PHERIPERAL1_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC0         (0x80 | (SPC5_PHERIPERAL1_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PHERIPERAL1_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 2 clock divider settings.*/
+#if SPC5_PHERIPERAL2_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC1         0
+#elif (SPC5_PHERIPERAL2_CLK_DIV_VALUE >= 1) &&                              \
+      (SPC5_PHERIPERAL2_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC1         (0x80 | (SPC5_PHERIPERAL2_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PHERIPERAL2_CLK_DIV_VALUE value specified"
+#endif
+
+/* Check on the peripherals set 3 clock divider settings.*/
+#if SPC5_PHERIPERAL3_CLK_DIV_VALUE == 0
+#define SPC5_CGM_SC_DC2         0
+#elif (SPC5_PHERIPERAL3_CLK_DIV_VALUE >= 1) &&                              \
+      (SPC5_PHERIPERAL3_CLK_DIV_VALUE <= 16)
+#define SPC5_CGM_SC_DC2         (0x80 | (SPC5_PHERIPERAL3_CLK_DIV_VALUE - 1))
+#else
+#error "invalid SPC5_PHERIPERAL3_CLK_DIV_VALUE value specified"
+#endif
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
diff --git a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
index 39563dbd1..417b73912 100644
--- a/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
+++ b/os/hal/platforms/SPC560BCxx/spc560bc_registry.h
@@ -40,6 +40,8 @@
 #define SPC5_LINFLEX0_RXI_NUMBER            79
 #define SPC5_LINFLEX0_TXI_NUMBER            80
 #define SPC5_LINFLEX0_ERR_NUMBER            81
+#define SPC5_LINFLEX0_CLK                   (halSPCGetSystemClock() /       \
+                                             SPC5_PHERIPERAL1_CLK_DIV_VALUE)
 
 #define SPC5_HAS_LINFLEX1                   TRUE
 #define SPC5_LINFLEX1_PCTL                  49
@@ -49,6 +51,8 @@
 #define SPC5_LINFLEX1_RXI_NUMBER            99
 #define SPC5_LINFLEX1_TXI_NUMBER            100
 #define SPC5_LINFLEX1_ERR_NUMBER            101
+#define SPC5_LINFLEX1_CLK                   (halSPCGetSystemClock() /       \
+                                             SPC5_PHERIPERAL1_CLK_DIV_VALUE)
 
 #define SPC5_HAS_LINFLEX2                   TRUE
 #define SPC5_LINFLEX2_PCTL                  50
-- 
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