From 8ca210a4af9fd039e290cfcc309adde543999c1f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Fri, 9 Aug 2013 08:24:22 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6108 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/platforms/LPC11Uxx/LPC11Uxx.h | 668 ---------------------------- os/hal/platforms/LPC11Uxx/ext_lld.c | 167 ------- os/hal/platforms/LPC11Uxx/ext_lld.h | 152 ------- os/hal/platforms/LPC11Uxx/ext_lld_isr.c | 194 -------- os/hal/platforms/LPC11Uxx/ext_lld_isr.h | 129 ------ os/hal/platforms/LPC11Uxx/gpt_lld.c | 338 -------------- os/hal/platforms/LPC11Uxx/gpt_lld.h | 204 --------- os/hal/platforms/LPC11Uxx/hal_lld.c | 116 ----- os/hal/platforms/LPC11Uxx/hal_lld.h | 218 --------- os/hal/platforms/LPC11Uxx/pal_lld.c | 99 ----- os/hal/platforms/LPC11Uxx/pal_lld.h | 311 ------------- os/hal/platforms/LPC11Uxx/platform.mk | 11 - os/hal/platforms/LPC11Uxx/serial_lld.c | 296 ------------ os/hal/platforms/LPC11Uxx/serial_lld.h | 206 --------- os/hal/platforms/LPC11Uxx/spi_lld.c | 391 ---------------- os/hal/platforms/LPC11Uxx/spi_lld.h | 311 ------------- os/hal/platforms/LPC11Uxx/system_LPC11Uxx.h | 64 --- 17 files changed, 3875 deletions(-) delete mode 100644 os/hal/platforms/LPC11Uxx/LPC11Uxx.h delete mode 100644 os/hal/platforms/LPC11Uxx/ext_lld.c delete mode 100644 os/hal/platforms/LPC11Uxx/ext_lld.h delete mode 100644 os/hal/platforms/LPC11Uxx/ext_lld_isr.c delete mode 100644 os/hal/platforms/LPC11Uxx/ext_lld_isr.h delete mode 100644 os/hal/platforms/LPC11Uxx/gpt_lld.c delete mode 100644 os/hal/platforms/LPC11Uxx/gpt_lld.h delete mode 100644 os/hal/platforms/LPC11Uxx/hal_lld.c delete mode 100644 os/hal/platforms/LPC11Uxx/hal_lld.h delete mode 100644 os/hal/platforms/LPC11Uxx/pal_lld.c delete mode 100644 os/hal/platforms/LPC11Uxx/pal_lld.h delete mode 100644 os/hal/platforms/LPC11Uxx/platform.mk delete mode 100644 os/hal/platforms/LPC11Uxx/serial_lld.c delete mode 100644 os/hal/platforms/LPC11Uxx/serial_lld.h delete mode 100644 os/hal/platforms/LPC11Uxx/spi_lld.c delete mode 100644 os/hal/platforms/LPC11Uxx/spi_lld.h delete mode 100644 os/hal/platforms/LPC11Uxx/system_LPC11Uxx.h (limited to 'os/hal/platforms/LPC11Uxx') diff --git a/os/hal/platforms/LPC11Uxx/LPC11Uxx.h b/os/hal/platforms/LPC11Uxx/LPC11Uxx.h deleted file mode 100644 index 81d37a704..000000000 --- a/os/hal/platforms/LPC11Uxx/LPC11Uxx.h +++ /dev/null @@ -1,668 +0,0 @@ - -/****************************************************************************************************//** - * @file LPC11Uxx.h - * - * - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for - * default LPC11Uxx Device Series - * - * @version V0.1 - * @date 21. March 2011 - * - * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45 - * - * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1, - * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40 - * - *******************************************************************************************************/ - - - -/** @addtogroup NXP - * @{ - */ - -/** @addtogroup LPC11Uxx - * @{ - */ - -#ifndef __LPC11UXX_H__ -#define __LPC11UXX_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -#if defined ( __CC_ARM ) - #pragma anon_unions -#endif - - /* Interrupt Number Definition */ - -typedef enum { -// ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------ -FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */ - FLEX_INT1_IRQn = 1, - FLEX_INT2_IRQn = 2, - FLEX_INT3_IRQn = 3, - FLEX_INT4_IRQn = 4, - FLEX_INT5_IRQn = 5, - FLEX_INT6_IRQn = 6, - FLEX_INT7_IRQn = 7, - GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */ - GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */ - Reserved0_IRQn = 10, /*!< Reserved Interrupt */ - Reserved1_IRQn = 11, - Reserved2_IRQn = 12, - Reserved3_IRQn = 13, - SSP1_IRQn = 14, /*!< SSP1 Interrupt */ - I2C_IRQn = 15, /*!< I2C Interrupt */ - TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */ - TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */ - TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */ - TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */ - SSP0_IRQn = 20, /*!< SSP0 Interrupt */ - UART_IRQn = 21, /*!< UART Interrupt */ - USB_IRQn = 22, /*!< USB IRQ Interrupt */ - USB_FIQn = 23, /*!< USB FIQ Interrupt */ - ADC_IRQn = 24, /*!< A/D Converter Interrupt */ - WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ - BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */ - FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */ - Reserved4_IRQn = 28, /*!< Reserved Interrupt */ - Reserved5_IRQn = 29, /*!< Reserved Interrupt */ - USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */ - Reserved6_IRQn = 31, /*!< Reserved Interrupt */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - -/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */ - -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ -#include "system_LPC11Uxx.h" /*!< LPC11Uxx System */ - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -// ------------------------------------------------------------------------------------------------ -// ----- I2C ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C) - */ - -typedef struct { /*!< (@ 0x40000000) I2C Structure */ - __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */ - __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */ - __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */ - __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */ - __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */ - __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */ - __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/ - __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/ - __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/ - __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/ - __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/ - __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */ -union{ - __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */ - struct{ - __IO uint32_t MASK0; - __IO uint32_t MASK1; - __IO uint32_t MASK2; - __IO uint32_t MASK3; - }; - }; -} LPC_I2C_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- WWDT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT) - */ - -typedef struct { /*!< (@ 0x40004000) WWDT Structure */ - __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/ - __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */ - __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */ - __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */ - __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */ - __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */ - __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */ -} LPC_WWDT_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- USART ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART) - */ - -typedef struct { /*!< (@ 0x40008000) USART Structure */ - - union { - __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ - __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */ - __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */ - }; - - union { - __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */ - __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ - }; - - union { - __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */ - __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ - }; - __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */ - __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */ - __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ - __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */ - __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */ - __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ - __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */ - __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ - __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */ - __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */ - __I uint32_t RESERVED0[3]; - __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */ - __I uint32_t RESERVED1; - __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */ - __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ - __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ - __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */ - __IO uint32_t SYNCCTRL; -} LPC_USART_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- Timer ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3 - */ - -typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */ - __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */ - __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */ - __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */ - __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */ - __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */ - __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */ - union { - __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */ - struct{ - __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */ - __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */ - __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */ - __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */ - }; - }; - __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */ - union{ - __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */ - struct{ - __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */ - __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */ - __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */ - __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */ - }; - }; -__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */ - __I uint32_t RESERVED0[12]; - __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */ - __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */ -} LPC_CTxxBx_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- ADC ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC) - */ - -typedef struct { /*!< (@ 0x4001C000) ADC Structure */ - __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */ - __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */ - __I uint32_t RESERVED0[1]; - __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */ - union{ - __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/ - struct{ - __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/ - __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/ - __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/ - __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/ - __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/ - __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/ - __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/ - __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/ - }; - }; - __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */ -} LPC_ADC_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- PMU ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU) - */ - -typedef struct { /*!< (@ 0x40038000) PMU Structure */ - __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */ - union{ - __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */ - struct{ - __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */ - __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */ - __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */ - __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */ - }; - }; -} LPC_PMU_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- FLASHCTRL ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL) - */ - -typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */ - __I uint32_t RESERVED0[4]; - __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */ - __I uint32_t RESERVED1[3]; - __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */ - __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */ - __I uint32_t RESERVED2[1]; - __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */ - __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */ - __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */ - __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */ - __I uint32_t RESERVED3[1001]; - __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */ - __I uint32_t RESERVED4[1]; - __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */ -} LPC_FLASHCTRL_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- SSP0/1 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0) - */ - -typedef struct { /*!< (@ 0x40040000) SSP0 Structure */ - __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */ - __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */ - __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ - __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */ - __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */ - __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */ - __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */ - __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */ -} LPC_SSPx_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- IOCONFIG ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) - */ - -typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ - __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */ - __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */ - __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */ - __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */ - __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */ - __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */ - __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */ - __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */ - __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */ - __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */ - __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */ - __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */ - __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */ - __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */ - __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */ - __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */ - __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */ - __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */ - __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */ - __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */ - __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */ - __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */ - __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */ - __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */ - __IO uint32_t PIO1_0; /*!< Offset: 0x060 */ - __IO uint32_t PIO1_1; - __IO uint32_t PIO1_2; - __IO uint32_t PIO1_3; - __IO uint32_t PIO1_4; /*!< Offset: 0x070 */ - __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */ - __IO uint32_t PIO1_6; - __IO uint32_t PIO1_7; - __IO uint32_t PIO1_8; /*!< Offset: 0x080 */ - __IO uint32_t PIO1_9; - __IO uint32_t PIO1_10; - __IO uint32_t PIO1_11; - __IO uint32_t PIO1_12; /*!< Offset: 0x090 */ - __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */ - __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */ - __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */ - __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */ - __IO uint32_t PIO1_17; - __IO uint32_t PIO1_18; - __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */ - __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */ - __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */ - __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */ - __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */ - __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */ - __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */ - __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */ - __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */ - __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */ - __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */ - __IO uint32_t PIO1_30; - __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */ -} LPC_IOCON_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- SYSCON ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON) - */ - -typedef struct { /*!< (@ 0x40048000) SYSCON Structure */ - __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */ - __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */ - __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */ - __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */ - __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */ - __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */ - __I uint32_t RESERVED0[2]; - __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */ - __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */ - __I uint32_t RESERVED1[2]; - __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */ - __I uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */ - __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */ - __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */ - __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */ - __I uint32_t RESERVED3[8]; - __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */ - __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */ - __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */ - __I uint32_t RESERVED4[1]; - __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */ - __I uint32_t RESERVED5[4]; - __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */ - __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */ - __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */ - __I uint32_t RESERVED6[8]; - __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */ - __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */ - __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */ - __I uint32_t RESERVED7[5]; - __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */ - __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */ - __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */ - __I uint32_t RESERVED8[5]; - __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */ - __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */ - __I uint32_t RESERVED9[18]; - __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */ - __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */ - __I uint32_t RESERVED10[6]; - __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */ - __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ - __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ - __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */ - __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */ - __I uint32_t RESERVED11[25]; - __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */ - __I uint32_t RESERVED12[3]; - __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */ - __I uint32_t RESERVED13[6]; - __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */ - __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */ - __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */ - __I uint32_t RESERVED14[110]; - __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */ -} LPC_SYSCON_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PIN_INT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT) - */ - -typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */ - __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */ - __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */ - __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */ - __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */ - __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ - __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */ - __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */ - __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */ -} LPC_GPIO_PIN_INT_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_GROUP_INT0/1 ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0) - */ - -typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */ - __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */ - __I uint32_t RESERVED0[7]; - __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */ - __I uint32_t RESERVED1[6]; - __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */ -} LPC_GPIO_GROUP_INTx_Type; - - - -// ------------------------------------------------------------------------------------------------ -// ----- USB ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB) - */ - -typedef struct { /*!< (@ 0x40080000) USB Structure */ - __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */ - __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */ - __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */ - __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */ - __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */ - __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */ - __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */ - __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */ - __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */ - __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */ - __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */ - __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */ - __I uint32_t RESERVED0[1]; - __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */ -} LPC_USB_Type; - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PORT ----- -// ------------------------------------------------------------------------------------------------ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) - */ - -typedef struct { - union { - struct { - __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */ - __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */ - }; - __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */ - }; - __I uint32_t RESERVED0[1008]; - union { - struct { - __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */ - __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */ - }; - __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */ - }; - uint32_t RESERVED1[960]; - __IO uint32_t DIR[2]; /* 0x2000 */ - uint32_t RESERVED2[30]; - __IO uint32_t MASK[2]; /* 0x2080 */ - uint32_t RESERVED3[30]; - __IO uint32_t PIN[2]; /* 0x2100 */ - uint32_t RESERVED4[30]; - __IO uint32_t MPIN[2]; /* 0x2180 */ - uint32_t RESERVED5[30]; - __IO uint32_t SET[2]; /* 0x2200 */ - uint32_t RESERVED6[30]; - __O uint32_t CLR[2]; /* 0x2280 */ - uint32_t RESERVED7[30]; - __O uint32_t NOT[2]; /* 0x2300 */ -} LPC_GPIO_Type; - - -#if defined ( __CC_ARM ) - #pragma no_anon_unions -#endif - - -// ------------------------------------------------------------------------------------------------ -// ----- Peripheral memory map ----- -// ------------------------------------------------------------------------------------------------ - -#define LPC_I2C_BASE (0x40000000) -#define LPC_WWDT_BASE (0x40004000) -#define LPC_USART_BASE (0x40008000) -#define LPC_CT16B0_BASE (0x4000C000) -#define LPC_CT16B1_BASE (0x40010000) -#define LPC_CT32B0_BASE (0x40014000) -#define LPC_CT32B1_BASE (0x40018000) -#define LPC_ADC_BASE (0x4001C000) -#define LPC_PMU_BASE (0x40038000) -#define LPC_FLASHCTRL_BASE (0x4003C000) -#define LPC_SSP0_BASE (0x40040000) -#define LPC_SSP1_BASE (0x40058000) -#define LPC_IOCON_BASE (0x40044000) -#define LPC_SYSCON_BASE (0x40048000) -#define LPC_GPIO_PIN_INT_BASE (0x4004C000) -#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000) -#define LPC_GPIO_GROUP_INT1_BASE (0x40060000) -#define LPC_USB_BASE (0x40080000) -#define LPC_GPIO_BASE (0x50000000) - - -// ------------------------------------------------------------------------------------------------ -// ----- Peripheral declaration ----- -// ------------------------------------------------------------------------------------------------ - -#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE) -#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) -#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE) -#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE) -#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE) -#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE) -#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE) -#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE) -#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE) -#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) -#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE) -#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE) -#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE) -#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE) -#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE) -#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE) -#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE) -#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE) -#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group (null) */ -/** @} */ /* End of group LPC11Uxx */ - -#ifdef __cplusplus -} -#endif - - -#endif // __LPC11UXX_H__ diff --git a/os/hal/platforms/LPC11Uxx/ext_lld.c b/os/hal/platforms/LPC11Uxx/ext_lld.c deleted file mode 100644 index 81cdaf4aa..000000000 --- a/os/hal/platforms/LPC11Uxx/ext_lld.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/ext_lld.c - * @brief LPC11Uxx EXT subsystem low level driver source. - * - * @addtogroup EXT - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EXTD1 driver identifier. - */ -EXTDriver EXTD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level EXT driver initialization. - * - * @notapi - */ -void ext_lld_init(void) { - - /* Driver initialization.*/ - extObjectInit(&EXTD1); -} - -/** - * @brief Configures and activates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_start(EXTDriver *extp) { - int i; - - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<19); - /* Configuration of automatic channels.*/ - for (i = 0; i < EXT_MAX_CHANNELS; i++) - if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) - ext_lld_channel_enable(extp, i); - else - ext_lld_channel_disable(extp, i); -} - -/** - * @brief Deactivates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_stop(EXTDriver *extp) { - int i; - - if (extp->state == EXT_ACTIVE) - for (i = 0; i < EXT_MAX_CHANNELS; i++) - ext_lld_exti_irq_disable(i); - - LPC_GPIO_PIN_INT->ISEL = 0; - LPC_GPIO_PIN_INT->CIENR = EXT_CHANNELS_MASK; - LPC_GPIO_PIN_INT->RISE = EXT_CHANNELS_MASK; - LPC_GPIO_PIN_INT->FALL = EXT_CHANNELS_MASK; - LPC_GPIO_PIN_INT->IST = EXT_CHANNELS_MASK; - - LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<19); -} - -/** - * @brief Enables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @notapi - */ -void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) { - - /* program the IOpin for this channel */ - LPC_SYSCON->PINTSEL[channel] = extp->config->channels[channel].iopin; - - /* Programming edge irq enables */ - if (extp->config->channels[channel].mode & EXT_CH_MODE_RISING_EDGE) - LPC_GPIO_PIN_INT->SIENR = (1 << channel); - else - LPC_GPIO_PIN_INT->CIENR = (1 << channel); - - if (extp->config->channels[channel].mode & EXT_CH_MODE_FALLING_EDGE) - LPC_GPIO_PIN_INT->SIENF = (1 << channel); - else - LPC_GPIO_PIN_INT->CIENF = (1 << channel); - - LPC_GPIO_PIN_INT->RISE = (1<FALL = (1<IST = (1<ISEL &= ~(1 << channel); - LPC_GPIO_PIN_INT->CIENR = (1 << channel); - LPC_GPIO_PIN_INT->RISE = (1 << channel); - LPC_GPIO_PIN_INT->FALL = (1 << channel); - LPC_GPIO_PIN_INT->IST = (1 << channel); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/ext_lld.h b/os/hal/platforms/LPC11Uxx/ext_lld.h deleted file mode 100644 index 9ec20f9f1..000000000 --- a/os/hal/platforms/LPC11Uxx/ext_lld.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/ext_lld.h - * @brief LPC11Uxx EXT subsystem low level driver header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_H_ -#define _EXT_LLD_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Available number of EXT channels. - */ -#define EXT_MAX_CHANNELS 8 - -/** - * @brief Mask of the available channels. - */ -#define EXT_CHANNELS_MASK ((1 << EXT_MAX_CHANNELS) - 1) - -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief EXT channel identifier. - */ -typedef uint32_t expchannel_t; - -/** - - * @brief EXT channel callback reason. - */ -typedef uint32_t expreason_t; - -/** - * @brief Type of an EXT generic notification callback. - * - * @param[in] extp pointer to the @p EXPDriver object triggering the - * callback - */ -typedef void (*extcallback_t)(EXTDriver *extp, - expchannel_t channel, - expreason_t reason); - -/** - * @brief Channel configuration structure. - */ -typedef struct { - /** - * @brief Channel mode. - */ - uint8_t mode; - /** - * @brief IO Pin. - */ - uint8_t iopin; - /** - * @brief Channel callback. - */ - extcallback_t cb; -} EXTChannelConfig; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Channel configurations. - */ - EXTChannelConfig channels[EXT_MAX_CHANNELS]; - /* End of the mandatory fields.*/ -} EXTConfig; - -/** - * @brief Structure representing an EXT driver. - */ -struct EXTDriver { - /** - * @brief Driver state. - */ - extstate_t state; - /** - * @brief Current configuration data. - */ - const EXTConfig *config; - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern EXTDriver EXTD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_init(void); - void ext_lld_start(EXTDriver *extp); - void ext_lld_stop(EXTDriver *extp); - void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); - void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/ext_lld_isr.c b/os/hal/platforms/LPC11Uxx/ext_lld_isr.c deleted file mode 100644 index 818d493e3..000000000 --- a/os/hal/platforms/LPC11Uxx/ext_lld_isr.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/ext_lld_isr.c - * @brief LPC11Uxx EXT subsystem low level driver ISR code. - * - * @addtogroup EXT - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -#include "ext_lld_isr.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ -static void ext_lld_interrupt( uint32_t n ) { - uint32_t reason; - - reason = ((LPC_GPIO_PIN_INT->RISE)>> n ) & 0x01; - reason |= ((LPC_GPIO_PIN_INT->FALL)>>(n-1)) & 0x02; - LPC_GPIO_PIN_INT->RISE = (1<FALL = (1<IST = (1<channels[n].cb(&EXTD1, n, reason); -} - -/** - * @brief EXT[0] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector40) { - - CH_IRQ_PROLOGUE(); - ext_lld_interrupt(0); - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXT[1] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector44) { - - CH_IRQ_PROLOGUE(); - ext_lld_interrupt(1); - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXT[2] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector48) { - - CH_IRQ_PROLOGUE(); - ext_lld_interrupt(2); - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXT[3] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector4C) { - - CH_IRQ_PROLOGUE(); - ext_lld_interrupt(3); - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXT[4] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector50) { - - CH_IRQ_PROLOGUE(); - ext_lld_interrupt(4); - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXT[5] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector54) { - - CH_IRQ_PROLOGUE(); - ext_lld_interrupt(5); - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXT[6] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector58) { - - CH_IRQ_PROLOGUE(); - ext_lld_interrupt(6); - CH_IRQ_EPILOGUE(); -} - -/** - * @brief EXT[7] interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector5C) { - - CH_IRQ_PROLOGUE(); - ext_lld_interrupt(7); - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ -static const uint8_t LPC11_EXT_EXTIn_IRQ_PRIORITY[] = - { LPC11_EXT_EXTI0_IRQ_PRIORITY, - LPC11_EXT_EXTI1_IRQ_PRIORITY, - LPC11_EXT_EXTI2_IRQ_PRIORITY, - LPC11_EXT_EXTI3_IRQ_PRIORITY, - LPC11_EXT_EXTI4_IRQ_PRIORITY, - LPC11_EXT_EXTI5_IRQ_PRIORITY, - LPC11_EXT_EXTI6_IRQ_PRIORITY, - LPC11_EXT_EXTI7_IRQ_PRIORITY }; - -/** - * @brief Enables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_enable( uint32_t exti_n ) { - - nvicEnableVector(FLEX_INT0_IRQn + exti_n, - CORTEX_PRIORITY_MASK(LPC11_EXT_EXTIn_IRQ_PRIORITY[exti_n])); -} - -/** - * @brief Disables EXTI IRQ sources. - * - * @notapi - */ -void ext_lld_exti_irq_disable( uint32_t exti_n ) { - - nvicDisableVector(FLEX_INT0_IRQn + exti_n); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/ext_lld_isr.h b/os/hal/platforms/LPC11Uxx/ext_lld_isr.h deleted file mode 100644 index 4fbbff862..000000000 --- a/os/hal/platforms/LPC11Uxx/ext_lld_isr.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/ext_lld_isr.h - * @brief LPC11Uxx EXT subsystem low level driver ISR header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef _EXT_LLD_ISR_H_ -#define _EXT_LLD_ISR_H_ - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief EXTI0 interrupt priority level setting. - */ -#if !defined(LPC11_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC11_EXT_EXTI0_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI1 interrupt priority level setting. - */ -#if !defined(LPC11_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC11_EXT_EXTI1_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI2 interrupt priority level setting. - */ -#if !defined(LPC11_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC11_EXT_EXTI2_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI3 interrupt priority level setting. - */ -#if !defined(LPC11_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC11_EXT_EXTI3_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI4 interrupt priority level setting. - */ -#if !defined(LPC11_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC11_EXT_EXTI4_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI5 interrupt priority level setting. - */ -#if !defined(LPC11_EXT_EXTI5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC11_EXT_EXTI5_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI6 interrupt priority level setting. - */ -#if !defined(LPC11_EXT_EXTI6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC11_EXT_EXTI6_IRQ_PRIORITY 3 -#endif - -/** - * @brief EXTI7 interrupt priority level setting. - */ -#if !defined(LPC11_EXT_EXTI7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC11_EXT_EXTI7_IRQ_PRIORITY 3 -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_exti_irq_enable( uint32_t exti_n ); - void ext_lld_exti_irq_disable( uint32_t exti_n ); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* _EXT_LLD_ISR_H_ */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/gpt_lld.c b/os/hal/platforms/LPC11Uxx/gpt_lld.c deleted file mode 100644 index 15a1c6068..000000000 --- a/os/hal/platforms/LPC11Uxx/gpt_lld.c +++ /dev/null @@ -1,338 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/gpt_lld.c - * @brief LPC11Uxx GPT subsystem low level driver source. - * - * @addtogroup GPT - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_GPT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief GPT1 driver identifier. - * @note The driver GPT1 allocates the complex timer CT16B0 when enabled. - */ -#if LPC_GPT_USE_CT16B0 || defined(__DOXYGEN__) -GPTDriver GPTD1; -#endif - -/** - * @brief GPT2 driver identifier. - * @note The driver GPT2 allocates the timer CT16B1 when enabled. - */ -#if LPC_GPT_USE_CT16B1 || defined(__DOXYGEN__) -GPTDriver GPTD2; -#endif - -/** - * @brief GPT3 driver identifier. - * @note The driver GPT3 allocates the timer CT32B0 when enabled. - */ -#if LPC_GPT_USE_CT32B0 || defined(__DOXYGEN__) -GPTDriver GPTD3; -#endif - -/** - * @brief GPT4 driver identifier. - * @note The driver GPT4 allocates the timer CT32B1 when enabled. - */ -#if LPC_GPT_USE_CT32B1 || defined(__DOXYGEN__) -GPTDriver GPTD4; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared IRQ handler. - * - * @param[in] gptp pointer to a @p GPTDriver object - */ -static void gpt_lld_serve_interrupt(GPTDriver *gptp) { - - gptp->tmr->IR = 1; /* Clear interrupt on match MR0.*/ - if (gptp->state == GPT_ONESHOT) { - gptp->state = GPT_READY; /* Back in GPT_READY state. */ - gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ - } - gptp->config->callback(gptp); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if LPC_GPT_USE_CT16B0 -/** - * @brief CT16B0 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector80) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD1); - - CH_IRQ_EPILOGUE(); -} -#endif /* LPC_GPT_USE_CT16B0 */ - -#if LPC_GPT_USE_CT16B1 -/** - * @brief CT16B1 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector84) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD2); - - CH_IRQ_EPILOGUE(); -} -#endif /* LPC_GPT_USE_CT16B0 */ - -#if LPC_GPT_USE_CT32B0 -/** - * @brief CT32B0 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector88) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD3); - - CH_IRQ_EPILOGUE(); -} -#endif /* LPC_GPT_USE_CT32B0 */ - -#if LPC_GPT_USE_CT32B1 -/** - * @brief CT32B1 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector8C) { - - CH_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD4); - - CH_IRQ_EPILOGUE(); -} -#endif /* LPC_GPT_USE_CT32B1 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level GPT driver initialization. - * - * @notapi - */ -void gpt_lld_init(void) { - -#if LPC_GPT_USE_CT16B0 - /* Driver initialization.*/ - GPTD1.tmr = LPC_CT16B0; - gptObjectInit(&GPTD1); -#endif - -#if LPC_GPT_USE_CT16B1 - /* Driver initialization.*/ - GPTD2.tmr = LPC_CT16B1; - gptObjectInit(&GPTD2); -#endif - -#if LPC_GPT_USE_CT32B0 - /* Driver initialization.*/ - GPTD3.tmr = LPC_CT32B0; - gptObjectInit(&GPTD3); -#endif - -#if LPC_GPT_USE_CT32B1 - /* Driver initialization.*/ - GPTD4.tmr = LPC_CT32B1; - gptObjectInit(&GPTD4); -#endif -} - -/** - * @brief Configures and activates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_start(GPTDriver *gptp) { - uint32_t pr; - - if (gptp->state == GPT_STOP) { - /* Clock activation.*/ -#if LPC_GPT_USE_CT16B0 - if (&GPTD1 == gptp) { - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); - nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2)); - } -#endif -#if LPC_GPT_USE_CT16B1 - if (&GPTD2 == gptp) { - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); - nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3)); - } -#endif -#if LPC_GPT_USE_CT32B0 - if (&GPTD3 == gptp) { - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); - nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2)); - } -#endif -#if LPC_GPT_USE_CT32B1 - if (&GPTD4 == gptp) { - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); - nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2)); - } -#endif - } - - /* Prescaler value calculation.*/ - pr = (uint16_t)((LPC_SYSCLK / gptp->config->frequency) - 1); - chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC_SYSCLK, - "gpt_lld_start(), #1", "invalid frequency"); - - /* Timer configuration.*/ - gptp->tmr->PR = pr; - gptp->tmr->IR = 1; - gptp->tmr->MCR = 0; - gptp->tmr->TCR = 0; -} - -/** - * @brief Deactivates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_stop(GPTDriver *gptp) { - - if (gptp->state == GPT_READY) { - gptp->tmr->MCR = 0; - gptp->tmr->TCR = 0; - -#if LPC_GPT_USE_CT16B0 - if (&GPTD1 == gptp) { - nvicDisableVector(TIMER_16_0_IRQn); - LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); - } -#endif -#if LPC_GPT_USE_CT16B1 - if (&GPTD2 == gptp) { - nvicDisableVector(TIMER_16_1_IRQn); - LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); - } -#endif -#if LPC_GPT_USE_CT32B0 - if (&GPTD3 == gptp) { - nvicDisableVector(TIMER_32_0_IRQn); - LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); - } -#endif -#if LPC_GPT_USE_CT32B1 - if (&GPTD4 == gptp) { - nvicDisableVector(TIMER_32_1_IRQn); - LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); - } -#endif - } -} - -/** - * @brief Starts the timer in continuous mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval period in ticks - * - * @notapi - */ -void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { - - gptp->tmr->MR0 = interval - 1; - gptp->tmr->IR = 1; - gptp->tmr->MCR = 3; /* IRQ and clr TC on match MR0. */ - gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ - gptp->tmr->TCR = 1; /* Timer enabled. */ -} - -/** - * @brief Stops the timer. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_stop_timer(GPTDriver *gptp) { - - gptp->tmr->IR = 1; - gptp->tmr->MCR = 0; - gptp->tmr->TCR = 0; -} - -/** - * @brief Starts the timer in one shot mode and waits for completion. - * @details This function specifically polls the timer waiting for completion - * in order to not have extra delays caused by interrupt servicing, - * this function is only recommended for short delays. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval time interval in ticks - * - * @notapi - */ -void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { - - gptp->tmr->MR0 = interval - 1; - gptp->tmr->IR = 1; - gptp->tmr->MCR = 4; /* Stop TC on match MR0. */ - gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ - gptp->tmr->TCR = 1; /* Timer enabled. */ - while (gptp->tmr->TCR & 1) - ; -} - -#endif /* HAL_USE_GPT */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/gpt_lld.h b/os/hal/platforms/LPC11Uxx/gpt_lld.h deleted file mode 100644 index 674960c7b..000000000 --- a/os/hal/platforms/LPC11Uxx/gpt_lld.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/gpt_lld.h - * @brief LPC11Uxx GPT subsystem low level driver header. - * - * @addtogroup GPT - * @{ - */ - -#ifndef _GPT_LLD_H_ -#define _GPT_LLD_H_ - -#if HAL_USE_GPT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief GPT1 driver enable switch. - * @details If set to @p TRUE the support for GPT1 is included. - * @note The default is @p TRUE. - */ -#if !defined(LPC_GPT_USE_CT16B0) || defined(__DOXYGEN__) -#define LPC_GPT_USE_CT16B0 TRUE -#endif - -/** - * @brief GPT2 driver enable switch. - * @details If set to @p TRUE the support for GPT2 is included. - * @note The default is @p TRUE. - */ -#if !defined(LPC_GPT_USE_CT16B1) || defined(__DOXYGEN__) -#define LPC_GPT_USE_CT16B1 TRUE -#endif - -/** - * @brief GPT3 driver enable switch. - * @details If set to @p TRUE the support for GPT3 is included. - * @note The default is @p TRUE. - */ -#if !defined(LPC_GPT_USE_CT32B0) || defined(__DOXYGEN__) -#define LPC_GPT_USE_CT32B0 TRUE -#endif - -/** - * @brief GPT4 driver enable switch. - * @details If set to @p TRUE the support for GPT4 is included. - * @note The default is @p TRUE. - */ -#if !defined(LPC_GPT_USE_CT32B1) || defined(__DOXYGEN__) -#define LPC_GPT_USE_CT32B1 TRUE -#endif - -/** - * @brief GPT1 interrupt priority level setting. - */ -#if !defined(LPC_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC_GPT_CT16B0_IRQ_PRIORITY 2 -#endif - -/** - * @brief GPT2 interrupt priority level setting. - */ -#if !defined(LPC_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC_GPT_CT16B1_IRQ_PRIORITY 2 -#endif - -/** - * @brief GPT3 interrupt priority level setting. - */ -#if !defined(LPC_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC_GPT_CT32B0_IRQ_PRIORITY 2 -#endif - -/** - * @brief GPT4 interrupt priority level setting. - */ -#if !defined(LPC_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC_GPT_CT32B1_IRQ_PRIORITY 2 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !LPC_GPT_USE_CT16B0 && !LPC_GPT_USE_CT16B1 && \ - !LPC_GPT_USE_CT32B0 && !LPC_GPT_USE_CT32B1 -#error "GPT driver activated but no CT peripheral assigned" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief GPT frequency type. - */ -typedef uint32_t gptfreq_t; - -/** - * @brief GPT counter type. - */ -typedef uint32_t gptcnt_t; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - gptfreq_t frequency; - /** - * @brief Timer callback pointer. - * @note This callback is invoked on GPT counter events. - */ - gptcallback_t callback; - /* End of the mandatory fields.*/ -} GPTConfig; - -/** - * @brief Structure representing a GPT driver. - */ -struct GPTDriver { - /** - * @brief Driver state. - */ - gptstate_t state; - /** - * @brief Current configuration data. - */ - const GPTConfig *config; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the CTxxBy registers block. - */ - LPC_CTxxBx_Type *tmr; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if LPC_GPT_USE_CT16B0 && !defined(__DOXYGEN__) -extern GPTDriver GPTD1; -#endif - -#if LPC_GPT_USE_CT16B1 && !defined(__DOXYGEN__) -extern GPTDriver GPTD2; -#endif - -#if LPC_GPT_USE_CT32B0 && !defined(__DOXYGEN__) -extern GPTDriver GPTD3; -#endif - -#if LPC_GPT_USE_CT32B1 && !defined(__DOXYGEN__) -extern GPTDriver GPTD4; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void gpt_lld_init(void); - void gpt_lld_start(GPTDriver *gptp); - void gpt_lld_stop(GPTDriver *gptp); - void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); - void gpt_lld_stop_timer(GPTDriver *gptp); - void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_GPT */ - -#endif /* _GPT_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/hal_lld.c b/os/hal/platforms/LPC11Uxx/hal_lld.c deleted file mode 100644 index 6a16de6f5..000000000 --- a/os/hal/platforms/LPC11Uxx/hal_lld.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/hal_lld.c - * @brief LPC11Uxx HAL subsystem low level driver source. - * - * @addtogroup HAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level HAL driver initialization. - * - * @notapi - */ -void hal_lld_init(void) { - - /* SysTick initialization using the system clock.*/ - nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); - SysTick->LOAD = LPC_SYSCLK / CH_CFG_FREQUENCY - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief LPC11Uxx clocks and PLL initialization. - * @note All the involved constants come from the file @p board.h. - * @note This function must be invoked only after the system reset. - * - * @special - */ -void lpc_clock_init(void) { - unsigned i; - - /* Flash wait states setting, the code takes care to not touch TBD bits.*/ - LPC_FLASHCTRL->FLASHCFG = (LPC_FLASHCTRL->FLASHCFG & ~3) | - LPC_FLASHCFG_FLASHTIM; - - /* System oscillator initialization if required.*/ -#if LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT -#if LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC - LPC_SYSCON->SYSOSCCTRL = LPC_SYSOSCCTRL; - LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */ - for (i = 0; i < 200; i++) - __NOP(); /* Stabilization delay. */ -#endif /* LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */ - - /* PLL initialization if required.*/ - LPC_SYSCON->SYSPLLCLKSEL = LPC_PLLCLK_SOURCE; - LPC_SYSCON->SYSPLLCLKUEN = 1; /* Really required? */ - LPC_SYSCON->SYSPLLCLKUEN = 0; - LPC_SYSCON->SYSPLLCLKUEN = 1; - LPC_SYSCON->SYSPLLCTRL = LPC_SYSPLLCTRL_MSEL | LPC_SYSPLLCTRL_PSEL; - LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */ - while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */ - ; -#endif /* LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */ - - /* Main clock source selection.*/ - LPC_SYSCON->MAINCLKSEL = LPC_MAINCLK_SOURCE; - LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */ - LPC_SYSCON->MAINCLKUEN = 0; - LPC_SYSCON->MAINCLKUEN = 1; - while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */ - ; - - /* ABH divider initialization, peripheral clocks are initially disabled, - the various device drivers will handle their own setup except GPIO and - IOCON that are left enabled.*/ - LPC_SYSCON->SYSAHBCLKDIV = LPC_SYSABHCLK_DIV; - LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F; - - /* Memory remapping, vectors always in ROM.*/ - LPC_SYSCON->SYSMEMREMAP = 2; -} - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/hal_lld.h b/os/hal/platforms/LPC11Uxx/hal_lld.h deleted file mode 100644 index 057dd47e3..000000000 --- a/os/hal/platforms/LPC11Uxx/hal_lld.h +++ /dev/null @@ -1,218 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/hal_lld.h - * @brief HAL subsystem low level driver header template. - * - * @addtogroup HAL - * @{ - */ - -#ifndef _HAL_LLD_H_ -#define _HAL_LLD_H_ - -#include "LPC11Uxx.h" -#include "nvic.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Defines the support for realtime counters in the HAL. - */ -#define HAL_IMPLEMENTS_COUNTERS FALSE - -/** - * @brief Platform name. - */ -#define PLATFORM_NAME "LPC11Uxx" - -#define IRCOSCCLK 12000000 /**< High speed internal clock. */ -#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */ - -#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator - clock source. */ -#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock - source. */ - -#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */ -#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */ -#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */ -#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief System PLL clock source. - */ -#if !defined(LPC_PLLCLK_SOURCE) || defined(__DOXYGEN__) -#define LPC_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC -#endif - -/** - * @brief System PLL multiplier. - * @note The value must be in the 1..32 range and the final frequency - * must not exceed the CCO ratings. - */ -#if !defined(LPC_SYSPLL_MUL) || defined(__DOXYGEN__) -#define LPC_SYSPLL_MUL 4 -#endif - -/** - * @brief System PLL divider. - * @note The value must be chosen between (2, 4, 8, 16). - */ -#if !defined(LPC_SYSPLL_DIV) || defined(__DOXYGEN__) -#define LPC_SYSPLL_DIV 4 -#endif - -/** - * @brief System main clock source. - */ -#if !defined(LPC_MAINCLK_SOURCE) || defined(__DOXYGEN__) -#define LPC_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT -#endif - -/** - * @brief AHB clock divider. - * @note The value must be chosen between (1...255). - */ -#if !defined(LPC_SYSCLK_DIV) || defined(__DOXYGEN__) -#define LPC_SYSABHCLK_DIV 1 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @brief Calculated SYSOSCCTRL setting. - */ -#if (SYSOSCCLK < 20000000) || defined(__DOXYGEN__) -#define LPC_SYSOSCCTRL 0 -#else -#define LPC_SYSOSCCTRL 1 -#endif - -/** - * @brief PLL input clock frequency. - */ -#if (LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__) -#define LPC_SYSPLLCLKIN SYSOSCCLK -#elif LPC_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC -#define LPC_SYSPLLCLKIN IRCOSCCLK -#else -#error "invalid LPC_PLLCLK_SOURCE clock source specified" -#endif - -/** - * @brief MSEL mask in SYSPLLCTRL register. - */ -#if (LPC_SYSPLL_MUL >= 1) && (LPC_SYSPLL_MUL <= 32) || defined(__DOXYGEN__) -#define LPC_SYSPLLCTRL_MSEL (LPC_SYSPLL_MUL - 1) -#else -#error "LPC_SYSPLL_MUL out of range (1...32)" -#endif - -/** - * @brief PSEL mask in SYSPLLCTRL register. - */ -#if (LPC_SYSPLL_DIV == 2) || defined(__DOXYGEN__) -#define LPC_SYSPLLCTRL_PSEL (0 << 5) -#elif LPC_SYSPLL_DIV == 4 -#define LPC_SYSPLLCTRL_PSEL (1 << 5) -#elif LPC_SYSPLL_DIV == 8 -#define LPC_SYSPLLCTRL_PSEL (2 << 5) -#elif LPC_SYSPLL_DIV == 16 -#define LPC_SYSPLLCTRL_PSEL (3 << 5) -#else -#error "invalid LPC_SYSPLL_DIV value (2,4,8,16)" -#endif - -/** - * @brief CCP frequency. - */ -#define LPC_SYSPLLCCO (LPC_SYSPLLCLKIN * LPC_SYSPLL_MUL * \ - LPC_SYSPLL_DIV) - -#if (LPC_SYSPLLCCO < 156000000) || (LPC_SYSPLLCCO > 320000000) -#error "CCO frequency out of the acceptable range (156...320)" -#endif - -/** - * @brief PLL output clock frequency. - */ -#define LPC_SYSPLLCLKOUT (LPC_SYSPLLCCO / LPC_SYSPLL_DIV) - -#if (LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__) -#define LPC_MAINCLK IRCOSCCLK -#elif LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN -#define LPC_MAINCLK LPC_SYSPLLCLKIN -#elif LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC -#define LPC_MAINCLK WDGOSCCLK -#elif LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT -#define LPC_MAINCLK LPC_SYSPLLCLKOUT -#else -#error "invalid LPC_MAINCLK_SOURCE clock source specified" -#endif - -/** - * @brief AHB clock. - */ -#define LPC_SYSCLK (LPC_MAINCLK / LPC_SYSABHCLK_DIV) -#if LPC_SYSCLK > 50000000 -#error "AHB clock frequency out of the acceptable range (50MHz max)" -#endif - -/** - * @brief Flash wait states. - */ -#if (LPC_SYSCLK <= 20000000) || defined(__DOXYGEN__) -#define LPC_FLASHCFG_FLASHTIM 0 -#elif LPC_SYSCLK <= 40000000 -#define LPC_FLASHCFG_FLASHTIM 1 -#else -#define LPC_FLASHCFG_FLASHTIM 2 -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void hal_lld_init(void); - void lpc_clock_init(void); -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/pal_lld.c b/os/hal/platforms/LPC11Uxx/pal_lld.c deleted file mode 100644 index 0b9d21391..000000000 --- a/os/hal/platforms/LPC11Uxx/pal_lld.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/pal_lld.c - * @brief LPC11Uxx GPIO low level driver code. - * - * @addtogroup PAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ -/** - * @brief LPC11Uxx I/O ports configuration. - * @details GPIO unit registers initialization. - * - * @param[in] config the LPC11Uxx ports configuration - * - * @notapi - */ -void _pal_lld_init(const PALConfig *config) { - - LPC_GPIO->DIR[0] = config->P0.dir; - LPC_GPIO->DIR[1] = config->P1.dir; - LPC_GPIO->PIN[0] = config->P0.data; - LPC_GPIO->PIN[1] = config->P1.data; -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with - * high state. - * @note This function does not alter the @p PINSELx registers. Alternate - * functions setup must be handled by device-specific code. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @notapi - */ -void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode) { - - switch (mode) { - case PAL_MODE_RESET: - case PAL_MODE_INPUT: - LPC_GPIO->DIR[port] &= ~mask; - break; - case PAL_MODE_UNCONNECTED: - palSetPort(port, PAL_WHOLE_PORT); - case PAL_MODE_OUTPUT_PUSHPULL: - LPC_GPIO->DIR[port] |= mask; - break; - } -} - -#endif /* HAL_USE_PAL */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/pal_lld.h b/os/hal/platforms/LPC11Uxx/pal_lld.h deleted file mode 100644 index a5072e70b..000000000 --- a/os/hal/platforms/LPC11Uxx/pal_lld.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/pal_lld.h - * @brief LPC11Uxx GPIO low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef _PAL_LLD_H_ -#define _PAL_LLD_H_ - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Unsupported modes and specific modes */ -/*===========================================================================*/ - -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_INPUT_ANALOG -#undef PAL_MODE_OUTPUT_OPENDRAIN - -/*===========================================================================*/ -/* I/O Ports Types and constants. */ -/*===========================================================================*/ - -/** - * @brief GPIO port setup info. - */ -typedef struct { - /** Initial value for FIO_PIN register.*/ - uint32_t data; - /** Initial value for FIO_DIR register.*/ - uint32_t dir; -} gpio_setup_t; - -/** - * @brief GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - * @note The @p IOCON block is not configured, initially all pins have - * enabled pullups and are programmed as GPIO. It is responsibility - * of the various drivers to reprogram the pins in the proper mode. - * Pins that are not handled by any driver may be programmed in - * @p board.c. - */ -typedef struct { - /** @brief GPIO 0 setup data.*/ - gpio_setup_t P0; - /** @brief GPIO 1 setup data.*/ - gpio_setup_t P1; -} PALConfig; - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 32 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Port Identifier. - */ -typedef uint32_t ioportid_t; - -/*===========================================================================*/ -/* I/O Ports Identifiers. */ -/*===========================================================================*/ - -/** - * @brief GPIO0 port identifier. - */ -#define IOPORT1 0 -#define GPIO0 0 - -/** - * @brief GPIO1 port identifier. - */ -#define IOPORT2 1 -#define GPIO1 1 - -/*===========================================================================*/ -/* Implementation, some of the following macros could be implemented as */ -/* functions, if so please put them in pal_lld.c. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - * - * @notapi - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) (LPC_GPIO->PIN[(port)]) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) (LPC_GPIO->SET[(port)]) - -/** - * @brief Writes a bits mask on a I/O port. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) (LPC_GPIO->PIN[(port)] = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @notapi - */ -#define pal_lld_setport(port, bits) (LPC_GPIO->SET[(port)] = (bits)) - -/** - * @brief Clears a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @notapi - */ -#define pal_lld_clearport(port, bits) (LPC_GPIO->CLR[(port)] = (bits)) - -/** - * @brief Toggles a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be XORed on the specified port - * - * @notapi - */ -#define pal_lld_toggleport(port, bits) (LPC_GPIO->NOT[(port)] = (bits)) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -/** - * @brief Reads a logical state from an I/O pad. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @return The logical state. - * @retval PAL_LOW low logical state. - * @retval PAL_HIGH high logical state. - * - * @notapi - */ -#define pal_lld_readpad(port, pad) \ - (LPC_GPIO->B[((port) * 32) + (pad)]) - -/** - * @brief Writes a logical state on an output pad. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @notapi - */ -#define pal_lld_writepad(port, pad, bit) \ - ((LPC_GPIO->B[((port) * 32) + (pad)]) = (bit)) - -/** - * @brief Sets a pad logical state to @p PAL_HIGH. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_setpad(port, pad) \ - (LPC_GPIO->SET[(port)] = 1 << (pad)) - -/** - * @brief Clears a pad logical state to @p PAL_LOW. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_clearpad(port, pad) \ - (LPC_GPIO->CLR[(port)] = 1 << (pad)) - -/** - * @brief Toggles a pad logical state. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_togglepad(port, pad) \ - (LPC_GPIO->NOT[(port)] = 1 << (pad)) - -#if !defined(__DOXYGEN__) -extern const PALConfig pal_default_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* _PAL_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/platform.mk b/os/hal/platforms/LPC11Uxx/platform.mk deleted file mode 100644 index 508238833..000000000 --- a/os/hal/platforms/LPC11Uxx/platform.mk +++ /dev/null @@ -1,11 +0,0 @@ -# List of all the LPC11Uxx platform files. -PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC11Uxx/hal_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC11Uxx/gpt_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC11Uxx/pal_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC11Uxx/spi_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC11Uxx/serial_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC11Uxx/ext_lld.c \ - ${CHIBIOS}/os/hal/platforms/LPC11Uxx/ext_lld_isr.c - -# Required include directories -PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC11Uxx diff --git a/os/hal/platforms/LPC11Uxx/serial_lld.c b/os/hal/platforms/LPC11Uxx/serial_lld.c deleted file mode 100644 index 17587cbb0..000000000 --- a/os/hal/platforms/LPC11Uxx/serial_lld.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/serial_lld.c - * @brief LPC11Uxx low level serial driver code. - * - * @addtogroup SERIAL - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -#if LPC_SERIAL_USE_UART0 || defined(__DOXYGEN__) -/** @brief UART0 serial driver identifier.*/ -SerialDriver SD1; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/** @brief Driver default configuration.*/ -static const SerialConfig default_config = { - SERIAL_DEFAULT_BITRATE, - LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, - FCR_TRIGGER0 -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief USART initialization. - * - * @param[in] sdp communication channel associated to the USART - * @param[in] config the architecture-dependent serial driver configuration - */ -static void uart_init(SerialDriver *sdp, const SerialConfig *config) { - LPC_USART_Type *u = sdp->uart; - - uint32_t div = LPC_SERIAL_UART0_PCLK / (config->sc_speed << 4); - u->LCR = config->sc_lcr | LCR_DLAB; - u->DLL = div; - u->DLM = div >> 8; - u->LCR = config->sc_lcr; - u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | config->sc_fcr; - u->ACR = 0; - u->FDR = 0x10; - u->TER = TER_ENABLE; - u->IER = IER_RBR | IER_STATUS; -} - -/** - * @brief USART de-initialization. - * - * @param[in] u pointer to an USART I/O block - */ -static void uart_deinit(LPC_USART_Type *u) { - - u->LCR = LCR_DLAB; - u->DLL = 1; - u->DLM = 0; - u->LCR = 0; - u->FDR = 0x10; - u->IER = 0; - u->FCR = FCR_RXRESET | FCR_TXRESET; - u->ACR = 0; - u->TER = TER_ENABLE; -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp communication channel associated to the UART - * @param[in] err UART LSR register value - */ -static void set_error(SerialDriver *sdp, IOREG32 err) { - flagsmask_t sts = 0; - - if (err & LSR_OVERRUN) - sts |= SD_OVERRUN_ERROR; - if (err & LSR_PARITY) - sts |= SD_PARITY_ERROR; - if (err & LSR_FRAMING) - sts |= SD_FRAMING_ERROR; - if (err & LSR_BREAK) - sts |= SD_BREAK_DETECTED; - chSysLockFromIsr(); - chnAddFlagsI(sdp, sts); - chSysUnlockFromIsr(); -} - -/** - * @brief Common IRQ handler. - * @note Tries hard to clear all the pending interrupt sources, we don't - * want to go through the whole ISR and have another interrupt soon - * after. - * - * @param[in] u pointer to an UART I/O block - * @param[in] sdp communication channel associated to the UART - */ -static void serve_interrupt(SerialDriver *sdp) { - LPC_USART_Type *u = sdp->uart; - - while (TRUE) { - switch (u->IIR & IIR_SRC_MASK) { - case IIR_SRC_NONE: - return; - case IIR_SRC_ERROR: - set_error(sdp, u->LSR); - break; - case IIR_SRC_TIMEOUT: - case IIR_SRC_RX: - chSysLockFromIsr(); - if (chIQIsEmptyI(&sdp->iqueue)) - chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); - chSysUnlockFromIsr(); - while (u->LSR & LSR_RBR_FULL) { - chSysLockFromIsr(); - if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK) - chnAddFlagsI(sdp, SD_OVERRUN_ERROR); - chSysUnlockFromIsr(); - } - break; - case IIR_SRC_TX: - { - int i = LPC_SERIAL_FIFO_PRELOAD; - do { - msg_t b; - - chSysLockFromIsr(); - b = chOQGetI(&sdp->oqueue); - chSysUnlockFromIsr(); - if (b < Q_OK) { - u->IER &= ~IER_THRE; - chSysLockFromIsr(); - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - chSysUnlockFromIsr(); - break; - } - u->THR = b; - } while (--i); - } - break; - default: - (void) u->THR; - (void) u->RBR; - } - } -} - -/** - * @brief Attempts a TX FIFO preload. - */ -static void preload(SerialDriver *sdp) { - LPC_USART_Type *u = sdp->uart; - - if (u->LSR & LSR_THRE) { - int i = LPC_SERIAL_FIFO_PRELOAD; - do { - msg_t b = chOQGetI(&sdp->oqueue); - if (b < Q_OK) { - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - return; - } - u->THR = b; - } while (--i); - } - u->IER |= IER_THRE; -} - -/** - * @brief Driver SD1 output notification. - */ -#if LPC_SERIAL_USE_UART0 || defined(__DOXYGEN__) -static void notify1(GenericQueue *qp) { - - (void)qp; - preload(&SD1); -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief UART0 IRQ handler. - * - * @isr - */ -#if LPC_SERIAL_USE_UART0 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(Vector94) { - - CH_IRQ_PROLOGUE(); - - serve_interrupt(&SD1); - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - * - * @notapi - */ -void sd_lld_init(void) { - -#if LPC_SERIAL_USE_UART0 - sdObjectInit(&SD1, NULL, notify1); - SD1.uart = LPC_USART; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - * - * @notapi - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { - - if (config == NULL) - config = &default_config; - - if (sdp->state == SD_STOP) { -#if LPC_SERIAL_USE_UART0 - if (&SD1 == sdp) { - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12); - LPC_SYSCON->UARTCLKDIV = LPC_SERIAL_UART0CLKDIV; - nvicEnableVector(UART_IRQn, - CORTEX_PRIORITY_MASK(LPC_SERIAL_UART0_IRQ_PRIORITY)); - } -#endif - } - uart_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the UART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - * - * @notapi - */ -void sd_lld_stop(SerialDriver *sdp) { - - if (sdp->state == SD_READY) { - uart_deinit(sdp->uart); -#if LPC_SERIAL_USE_UART0 - if (&SD1 == sdp) { - LPC_SYSCON->UARTCLKDIV = 0; - LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12); - nvicDisableVector(UART_IRQn); - return; - } -#endif - } -} - -#endif /* HAL_USE_SERIAL */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/serial_lld.h b/os/hal/platforms/LPC11Uxx/serial_lld.h deleted file mode 100644 index 162e9ae16..000000000 --- a/os/hal/platforms/LPC11Uxx/serial_lld.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/serial_lld.h - * @brief LPC11Uxx low level serial driver header. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef _SERIAL_LLD_H_ -#define _SERIAL_LLD_H_ - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define IIR_SRC_MASK 0x0F -#define IIR_SRC_NONE 0x01 -#define IIR_SRC_MODEM 0x00 -#define IIR_SRC_TX 0x02 -#define IIR_SRC_RX 0x04 -#define IIR_SRC_ERROR 0x06 -#define IIR_SRC_TIMEOUT 0x0C - -#define IER_RBR 1 -#define IER_THRE 2 -#define IER_STATUS 4 - -#define LCR_WL5 0 -#define LCR_WL6 1 -#define LCR_WL7 2 -#define LCR_WL8 3 -#define LCR_STOP1 0 -#define LCR_STOP2 4 -#define LCR_NOPARITY 0 -#define LCR_PARITYODD 0x08 -#define LCR_PARITYEVEN 0x18 -#define LCR_PARITYONE 0x28 -#define LCR_PARITYZERO 0x38 -#define LCR_BREAK_ON 0x40 -#define LCR_DLAB 0x80 - -#define FCR_ENABLE 1 -#define FCR_RXRESET 2 -#define FCR_TXRESET 4 -#define FCR_TRIGGER0 0 -#define FCR_TRIGGER1 0x40 -#define FCR_TRIGGER2 0x80 -#define FCR_TRIGGER3 0xC0 - -#define LSR_RBR_FULL 1 -#define LSR_OVERRUN 2 -#define LSR_PARITY 4 -#define LSR_FRAMING 8 -#define LSR_BREAK 0x10 -#define LSR_THRE 0x20 -#define LSR_TEMT 0x40 -#define LSR_RXFE 0x80 - -#define TER_ENABLE 0x80 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief UART0 driver enable switch. - * @details If set to @p TRUE the support for UART0 is included. - * @note The default is @p TRUE . - */ -#if !defined(LPC_SERIAL_USE_UART0) || defined(__DOXYGEN__) -#define LPC_SERIAL_USE_UART0 TRUE -#endif - -/** - * @brief FIFO preload parameter. - * @details Configuration parameter, this values defines how many bytes are - * preloaded in the HW transmit FIFO for each interrupt, the maximum - * value is 16 the minimum is 1. - * @note An high value reduces the number of interrupts generated but can - * also increase the worst case interrupt response time because the - * preload loops. - */ -#if !defined(LPC_SERIAL_FIFO_PRELOAD) || defined(__DOXYGEN__) -#define LPC_SERIAL_FIFO_PRELOAD 16 -#endif - -/** - * @brief UART0 PCLK divider. - */ -#if !defined(LPC_SERIAL_UART0CLKDIV) || defined(__DOXYGEN__) -#define LPC_SERIAL_UART0CLKDIV 1 -#endif - -/** - * @brief UART0 interrupt priority level setting. - */ -#if !defined(LPC_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC_SERIAL_UART0_IRQ_PRIORITY 3 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (LPC_SERIAL_UART0CLKDIV < 1) || (LPC_SERIAL_UART0CLKDIV > 255) -#error "invalid LPC_SERIAL_UART0CLKDIV setting" -#endif - -#if (LPC_SERIAL_FIFO_PRELOAD < 1) || (LPC_SERIAL_FIFO_PRELOAD > 16) -#error "invalid LPC_SERIAL_FIFO_PRELOAD setting" -#endif - -/** - * @brief UART0 clock. - */ -#define LPC_SERIAL_UART0_PCLK \ - (LPC_MAINCLK / LPC_SERIAL_UART0CLKDIV) - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief LPC11xx Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t sc_speed; - /** - * @brief Initialization value for the LCR register. - */ - uint32_t sc_lcr; - /** - * @brief Initialization value for the FCR register. - */ - uint32_t sc_fcr; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - InputQueue iqueue; \ - /* Output queue.*/ \ - OutputQueue oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the USART registers block.*/ \ - LPC_USART_Type *uart; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if LPC_SERIAL_USE_UART0 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* _SERIAL_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/spi_lld.c b/os/hal/platforms/LPC11Uxx/spi_lld.c deleted file mode 100644 index 67282e8a4..000000000 --- a/os/hal/platforms/LPC11Uxx/spi_lld.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/spi_lld.c - * @brief LPC11Uxx low level SPI driver code. - * - * @addtogroup SPI - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -#if LPC_SPI_USE_SSP0 || defined(__DOXYGEN__) -/** @brief SPI1 driver identifier.*/ -SPIDriver SPID1; -#endif - -#if LPC_SPI_USE_SSP1 || defined(__DOXYGEN__) -/** @brief SPI2 driver identifier.*/ -SPIDriver SPID2; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Preloads the transmit FIFO. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -static void ssp_fifo_preload(SPIDriver *spip) { - LPC_SSPx_Type *ssp = spip->ssp; - uint32_t n = spip->txcnt > LPC_SSP_FIFO_DEPTH ? - LPC_SSP_FIFO_DEPTH : spip->txcnt; - - while(((ssp->SR & SR_TNF) != 0) && (n > 0)) { - if (spip->txptr != NULL) { - if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { - const uint16_t *p = spip->txptr; - ssp->DR = *p++; - spip->txptr = p; - } - else { - const uint8_t *p = spip->txptr; - ssp->DR = *p++; - spip->txptr = p; - } - } - else - ssp->DR = 0xFFFFFFFF; - n--; - spip->txcnt--; - } -} - -/** - * @brief Common IRQ handler. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -static void spi_serve_interrupt(SPIDriver *spip) { - LPC_SSPx_Type *ssp = spip->ssp; - - if ((ssp->MIS & MIS_ROR) != 0) { - /* The overflow condition should never happen because priority is given - to receive but a hook macro is provided anyway...*/ - LPC_SPI_SSP_ERROR_HOOK(spip); - } - ssp->ICR = ICR_RT | ICR_ROR; - while ((ssp->SR & SR_RNE) != 0) { - if (spip->rxptr != NULL) { - if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { - uint16_t *p = spip->rxptr; - *p++ = ssp->DR; - spip->rxptr = p; - } - else { - uint8_t *p = spip->rxptr; - *p++ = ssp->DR; - spip->rxptr = p; - } - } - else - (void)ssp->DR; - if (--spip->rxcnt == 0) { - chDbgAssert(spip->txcnt == 0, - "spi_serve_interrupt(), #1", "counter out of synch"); - /* Stops the IRQ sources.*/ - ssp->IMSC = 0; - /* Portable SPI ISR code defined in the high level driver, note, it is - a macro.*/ - _spi_isr_code(spip); - return; - } - } - ssp_fifo_preload(spip); - if (spip->txcnt == 0) - ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if LPC_SPI_USE_SSP0 || defined(__DOXYGEN__) -/** - * @brief SSP0 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector90) { - - CH_IRQ_PROLOGUE(); - - spi_serve_interrupt(&SPID1); - - CH_IRQ_EPILOGUE(); -} -#endif - -#if LPC_SPI_USE_SSP1 || defined(__DOXYGEN__) -/** - * @brief SSP1 interrupt handler. - * - * @isr - */ -CH_IRQ_HANDLER(Vector78) { - - CH_IRQ_PROLOGUE(); - - spi_serve_interrupt(&SPID2); - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - * - * @notapi - */ -void spi_lld_init(void) { - -#if LPC_SPI_USE_SSP0 - spiObjectInit(&SPID1); - SPID1.ssp = LPC_SSP0; -#endif /* LPC_SPI_USE_SSP0 */ - -#if LPC_SPI_USE_SSP1 - spiObjectInit(&SPID2); - SPID2.ssp = LPC_SSP1; -#endif /* LPC_SPI_USE_SSP0 */ -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_start(SPIDriver *spip) { - - if (spip->state == SPI_STOP) { - /* Clock activation.*/ -#if LPC_SPI_USE_SSP0 - if (&SPID1 == spip) { - LPC_SYSCON->SSP0CLKDIV = LPC_SPI_SSP0CLKDIV; - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11); - LPC_SYSCON->PRESETCTRL |= 1; - nvicEnableVector(SSP0_IRQn, - CORTEX_PRIORITY_MASK(LPC_SPI_SSP0_IRQ_PRIORITY)); - } -#endif -#if LPC_SPI_USE_SSP1 - if (&SPID2 == spip) { - LPC_SYSCON->SSP1CLKDIV = LPC_SPI_SSP1CLKDIV; - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18); - LPC_SYSCON->PRESETCTRL |= 4; - nvicEnableVector(SSP1_IRQn, - CORTEX_PRIORITY_MASK(LPC_SPI_SSP1_IRQ_PRIORITY)); - } -#endif - } - /* Configuration.*/ - spip->ssp->CR1 = 0; - spip->ssp->ICR = ICR_RT | ICR_ROR; - spip->ssp->CR0 = spip->config->cr0; - spip->ssp->CPSR = spip->config->cpsr; - spip->ssp->CR1 = CR1_SSE; -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_stop(SPIDriver *spip) { - - if (spip->state != SPI_STOP) { - spip->ssp->CR1 = 0; - spip->ssp->CR0 = 0; - spip->ssp->CPSR = 0; -#if LPC_SPI_USE_SSP0 - if (&SPID1 == spip) { - LPC_SYSCON->PRESETCTRL &= ~1; - LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11); - LPC_SYSCON->SSP0CLKDIV = 0; - nvicDisableVector(SSP0_IRQn); - } -#endif -#if LPC_SPI_USE_SSP1 - if (&SPID2 == spip) { - LPC_SYSCON->PRESETCTRL &= ~4; - LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18); - LPC_SYSCON->SSP1CLKDIV = 0; - nvicDisableVector(SSP1_IRQn); - } -#endif - } -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_select(SPIDriver *spip) { - - palClearPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_unselect(SPIDriver *spip) { - - palSetPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This function transmits a series of idle words on the SPI bus and - * ignores the received data. This function can be invoked even - * when a slave select signal has not been yet asserted. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @notapi - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) { - - spip->rxptr = NULL; - spip->txptr = NULL; - spip->rxcnt = spip->txcnt = n; - ssp_fifo_preload(spip); - spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf) { - - spip->rxptr = rxbuf; - spip->txptr = txbuf; - spip->rxcnt = spip->txcnt = n; - ssp_fifo_preload(spip); - spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { - - spip->rxptr = NULL; - spip->txptr = txbuf; - spip->rxcnt = spip->txcnt = n; - ssp_fifo_preload(spip); - spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { - - spip->rxptr = rxbuf; - spip->txptr = NULL; - spip->rxcnt = spip->txcnt = n; - ssp_fifo_preload(spip); - spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { - - spip->ssp->DR = (uint32_t)frame; - while ((spip->ssp->SR & SR_RNE) == 0) - ; - return (uint16_t)spip->ssp->DR; -} - -#endif /* HAL_USE_SPI */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/spi_lld.h b/os/hal/platforms/LPC11Uxx/spi_lld.h deleted file mode 100644 index 46d2e657c..000000000 --- a/os/hal/platforms/LPC11Uxx/spi_lld.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file LPC11Uxx/spi_lld.h - * @brief LPC11Uxx low level SPI driver header. - * - * @addtogroup SPI - * @{ - */ - -#ifndef _SPI_LLD_H_ -#define _SPI_LLD_H_ - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Hardware FIFO depth. - */ -#define LPC_SSP_FIFO_DEPTH 8 - -#define CR0_DSSMASK 0x0F -#define CR0_DSS4BIT 3 -#define CR0_DSS5BIT 4 -#define CR0_DSS6BIT 5 -#define CR0_DSS7BIT 6 -#define CR0_DSS8BIT 7 -#define CR0_DSS9BIT 8 -#define CR0_DSS10BIT 9 -#define CR0_DSS11BIT 0xA -#define CR0_DSS12BIT 0xB -#define CR0_DSS13BIT 0xC -#define CR0_DSS14BIT 0xD -#define CR0_DSS15BIT 0xE -#define CR0_DSS16BIT 0xF -#define CR0_FRFSPI 0 -#define CR0_FRFSSI 0x10 -#define CR0_FRFMW 0x20 -#define CR0_CPOL 0x40 -#define CR0_CPHA 0x80 -#define CR0_CLOCKRATE(n) ((n) << 8) - -#define CR1_LBM 1 -#define CR1_SSE 2 -#define CR1_MS 4 -#define CR1_SOD 8 - -#define SR_TFE 1 -#define SR_TNF 2 -#define SR_RNE 4 -#define SR_RFF 8 -#define SR_BSY 16 - -#define IMSC_ROR 1 -#define IMSC_RT 2 -#define IMSC_RX 4 -#define IMSC_TX 8 - -#define RIS_ROR 1 -#define RIS_RT 2 -#define RIS_RX 4 -#define RIS_TX 8 - -#define MIS_ROR 1 -#define MIS_RT 2 -#define MIS_RX 4 -#define MIS_TX 8 - -#define ICR_ROR 1 -#define ICR_RT 2 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief SPI1 driver enable switch. - * @details If set to @p TRUE the support for device SSP0 is included. - * @note The default is @p TRUE. - */ -#if !defined(LPC_SPI_USE_SSP0) || defined(__DOXYGEN__) -#define LPC_SPI_USE_SSP0 TRUE -#endif - -/** - * @brief SPI2 driver enable switch. - * @details If set to @p TRUE the support for device SSP1 is included. - * @note The default is @p TRUE. - */ -#if !defined(LPC_SPI_USE_SSP1) || defined(__DOXYGEN__) -#define LPC_SPI_USE_SSP1 TRUE -#endif - -/** - * @brief SSP0 PCLK divider. - */ -#if !defined(LPC_SPI_SSP0CLKDIV) || defined(__DOXYGEN__) -#define LPC_SPI_SSP0CLKDIV 1 -#endif - -/** - * @brief SSP1 PCLK divider. - */ -#if !defined(LPC_SPI_SSP1CLKDIV) || defined(__DOXYGEN__) -#define LPC_SPI_SSP1CLKDIV 1 -#endif - -/** - * @brief SPI0 interrupt priority level setting. - */ -#if !defined(LPC_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC_SPI_SSP0_IRQ_PRIORITY 1 -#endif - -/** - * @brief SPI1 interrupt priority level setting. - */ -#if !defined(LPC_SPI_SSP1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define LPC_SPI_SSP1_IRQ_PRIORITY 1 -#endif - -/** - * @brief Overflow error hook. - * @details The default action is to stop the system. - */ -#if !defined(LPC_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__) -#define LPC_SPI_SSP_ERROR_HOOK(spip) chSysHalt() -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (LPC_SPI_SSP0CLKDIV < 1) || (LPC_SPI_SSP0CLKDIV > 255) -#error "invalid LPC_SPI_SSP0CLKDIV setting" -#endif - -#if (LPC_SPI_SSP1CLKDIV < 1) || (LPC_SPI_SSP1CLKDIV > 255) -#error "invalid LPC_SPI_SSP1CLKDIV setting" -#endif - -#if !LPC_SPI_USE_SSP0 && !LPC_SPI_USE_SSP1 -#error "SPI driver activated but no SPI peripheral assigned" -#endif - -/** - * @brief SSP0 clock. - */ -#define LPC_SPI_SSP0_PCLK \ - (LPC_MAINCLK / LPC_SPI_SSP0CLKDIV) - -/** - * @brief SSP1 clock. - */ -#define LPC_SPI_SSP1_PCLK \ - (LPC_MAINCLK / LPC_SPI_SSP1CLKDIV) - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an SPI driver. - */ -typedef struct SPIDriver SPIDriver; - -/** - * @brief SPI notification callback type. - * - * @param[in] spip pointer to the @p SPIDriver object triggering the - * callback - */ -typedef void (*spicallback_t)(SPIDriver *spip); - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief Operation complete callback or @p NULL. - */ - spicallback_t end_cb; - /* End of the mandatory fields.*/ - /** - * @brief The chip select line port. - */ - ioportid_t ssport; - /** - * @brief The chip select line pad number. - */ - uint16_t sspad; - /** - * @brief SSP CR0 initialization data. - */ - uint16_t cr0; - /** - * @brief SSP CPSR initialization data. - */ - uint32_t cpsr; -} SPIConfig; - -/** - * @brief Structure representing a SPI driver. - */ -struct SPIDriver { - /** - * @brief Driver state. - */ - spistate_t state; - /** - * @brief Current configuration data. - */ - const SPIConfig *config; -#if SPI_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - Thread *thread; -#endif /* SPI_USE_WAIT */ -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - Mutex mutex; -#elif CH_CFG_USE_SEMAPHORES - Semaphore semaphore; -#endif -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#if defined(SPI_DRIVER_EXT_FIELDS) - SPI_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the SSP registers block. - */ - LPC_SSPx_Type *ssp; - /** - * @brief Number of bytes yet to be received. - */ - uint32_t rxcnt; - /** - * @brief Receive pointer or @p NULL. - */ - void *rxptr; - /** - * @brief Number of bytes yet to be transmitted. - */ - uint32_t txcnt; - /** - * @brief Transmit pointer or @p NULL. - */ - const void *txptr; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if LPC_SPI_USE_SSP0 && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#if LPC_SPI_USE_SSP1 && !defined(__DOXYGEN__) -extern SPIDriver SPID2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); - uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SPI */ - -#endif /* _SPI_LLD_H_ */ - -/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/system_LPC11Uxx.h b/os/hal/platforms/LPC11Uxx/system_LPC11Uxx.h deleted file mode 100644 index e490d17dc..000000000 --- a/os/hal/platforms/LPC11Uxx/system_LPC11Uxx.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//** - * @file system_LPC11Uxx.h - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File - * for the NXP LPC11Uxx Device Series - * @version V1.10 - * @date 24. November 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC11Uxx_H -#define __SYSTEM_LPC11Uxx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC11Uxx_H */ -- cgit v1.2.3