From 887ff945a901fac1fe18d6be7367b7f405a99e1a Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Thu, 4 Oct 2018 14:36:34 +0000 Subject: Flash infrastructure rework based on WSPI, not complete. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12320 110e8d01-0319-4d1e-a829-52ad28d1bb01 --- .../serial_nor/devices/micron_n25q/flash_device.c | 567 +++++++++++++++++++++ .../serial_nor/devices/micron_n25q/flash_device.h | 148 ++++++ .../serial_nor/devices/micron_n25q/flash_device.mk | 14 + .../serial_nor/devices/micron_n25q/micron_n25q.c | 544 -------------------- .../serial_nor/devices/micron_n25q/micron_n25q.h | 149 ------ .../serial_nor/devices/micron_n25q/micron_n25q.mk | 14 - os/hal/lib/complex/serial_nor/hal_jesd216_flash.c | 402 +++++++++++++++ os/hal/lib/complex/serial_nor/hal_jesd216_flash.h | 223 ++++++++ os/hal/lib/complex/serial_nor/serial_nor.c | 165 +++--- os/hal/lib/complex/serial_nor/serial_nor.h | 64 +-- 10 files changed, 1469 insertions(+), 821 deletions(-) create mode 100644 os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.c create mode 100644 os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.h create mode 100644 os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.mk delete mode 100644 os/hal/lib/complex/serial_nor/devices/micron_n25q/micron_n25q.c delete mode 100644 os/hal/lib/complex/serial_nor/devices/micron_n25q/micron_n25q.h delete mode 100644 os/hal/lib/complex/serial_nor/devices/micron_n25q/micron_n25q.mk create mode 100644 os/hal/lib/complex/serial_nor/hal_jesd216_flash.c create mode 100644 os/hal/lib/complex/serial_nor/hal_jesd216_flash.h (limited to 'os/hal/lib') diff --git a/os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.c b/os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.c new file mode 100644 index 000000000..032e6d0cc --- /dev/null +++ b/os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.c @@ -0,0 +1,567 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file flash_device.c + * @brief Micron N25Q serial flash driver code. + * + * @addtogroup MICRON_N25Q + * @ingroup MICRON_N25Q + * @{ + */ + +#include + +#include "hal.h" +#include "serial_nor.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define PAGE_SIZE 256U +#define PAGE_MASK (PAGE_SIZE - 1U) + +#if SNOR_USE_SUB_SECTORS == TRUE +#define SECTOR_SIZE 0x00001000U +#define CMD_SECTOR_ERASE N25Q_CMD_SUBSECTOR_ERASE +#else +#define SECTOR_SIZE 0x00010000U +#define CMD_SECTOR_ERASE N25Q_CMD_SECTOR_ERASE +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief N25Q128 descriptor. + */ +flash_descriptor_t snor_descriptor = { + .attributes = FLASH_ATTR_ERASED_IS_ONE | FLASH_ATTR_REWRITABLE | + FLASH_ATTR_SUSPEND_ERASE_CAPABLE, + .page_size = 256U, + .sectors_count = 0U, /* It is overwritten.*/ + .sectors = NULL, + .sectors_size = SECTOR_SIZE, + .address = 0U +}; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI +/* Initial N25Q_CMD_READ_ID command.*/ +static const wspi_command_t n25q_cmd_read_id = { + .cmd = N25Q_CMD_READ_ID, + .cfg = 0U | +#if SNOR_SWITCH_WIDTH == TRUE + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE, +#else +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE, +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES, +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES, +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES, +#endif +#endif + .addr = 0, + .alt = 0, + .dummy = 0 +}; + +/* Initial N25Q_CMD_WRITE_ENHANCED_V_CONF_REGISTER command.*/ +static const wspi_command_t n25q_cmd_write_evconf = { + .cmd = N25Q_CMD_WRITE_ENHANCED_V_CONF_REGISTER, + .cfg = 0U | +#if SNOR_SWITCH_WIDTH == TRUE + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE, +#else +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE, +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES, +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES, +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES, +#endif +#endif + .addr = 0, + .alt = 0, + .dummy = 0 +}; + +/* Initial N25Q_CMD_WRITE_ENABLE command.*/ +static const wspi_command_t n25q_cmd_write_enable = { + .cmd = N25Q_CMD_WRITE_ENABLE, + .cfg = 0U | +#if SNOR_SWITCH_WIDTH == TRUE + WSPI_CFG_CMD_MODE_ONE_LINE, +#else +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE, +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES, +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES, +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES, +#endif +#endif + .addr = 0, + .alt = 0, + .dummy = 0 +}; + +/* Bus width initialization.*/ +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L +static const uint8_t n25q_evconf_value[1] = {0xCF}; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L +static const uint8_t n25q_evconf_value[1] = {0x8F}; +#else +static const uint8_t n25q_evconf_value[1] = {0x4F}; +#endif +#endif /* JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static bool n25q_find_id(const uint8_t *set, size_t size, uint8_t element) { + size_t i; + + for (i = 0; i < size; i++) { + if (set[i] == element) { + return true; + } + } + return false; +} + +static flash_error_t n25q_poll_status(SNORDriver *devp) { + uint8_t sts; + + do { +#if SNOR_NICE_WAITING == TRUE + osalThreadSleepMilliseconds(1); +#endif + /* Read status command.*/ + jesd216_cmd_receive(devp->config->busp, N25Q_CMD_READ_FLAG_STATUS_REGISTER, + 1, &sts); + } while ((sts & N25Q_FLAGS_PROGRAM_ERASE) == 0U); + + /* Checking for errors.*/ + if ((sts & N25Q_FLAGS_ALL_ERRORS) != 0U) { + /* Clearing status register.*/ + jesd216_cmd(devp->config->busp, N25Q_CMD_CLEAR_FLAG_STATUS_REGISTER); + + /* Program operation failed.*/ + return FLASH_ERROR_PROGRAM; + } + + return FLASH_NO_ERROR; +} + +#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) || defined(__DOXYGEN__) +static void n25q_reset_memory(SNORDriver *devp) { + + /* 1x N25Q_CMD_RESET_ENABLE command.*/ + static const wspi_command_t cmd_reset_enable_1 = { + .cmd = N25Q_CMD_RESET_ENABLE, + .cfg = WSPI_CFG_CMD_MODE_ONE_LINE, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + /* 1x N25Q_CMD_RESET_MEMORY command.*/ + static const wspi_command_t cmd_reset_memory_1 = { + .cmd = N25Q_CMD_RESET_MEMORY, + .cfg = WSPI_CFG_CMD_MODE_ONE_LINE, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + /* If the device is in one bit mode then the following commands are + rejected because shorter than 8 bits. If the device is in multiple + bits mode then the commands are accepted and the device is reset to + one bit mode.*/ +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI4L + /* 4x N25Q_CMD_RESET_ENABLE command.*/ + static const wspi_command_t cmd_reset_enable_4 = { + .cmd = N25Q_CMD_RESET_ENABLE, + .cfg = WSPI_CFG_CMD_MODE_FOUR_LINES, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + /* 4x N25Q_CMD_RESET_MEMORY command.*/ + static const wspi_command_t cmd_reset_memory_4 = { + .cmd = N25Q_CMD_RESET_MEMORY, + .cfg = WSPI_CFG_CMD_MODE_FOUR_LINES, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + wspiCommand(devp->config->busp, &cmd_reset_enable_4); + wspiCommand(devp->config->busp, &cmd_reset_memory_4); +#else + /* 2x N25Q_CMD_RESET_ENABLE command.*/ + static const wspi_command_t cmd_reset_enable_2 = { + .cfg = WSPI_CFG_CMD(N25Q_CMD_RESET_ENABLE) | + WSPI_CFG_CMD_MODE_TWO_LINES, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + /* 2x N25Q_CMD_RESET_MEMORY command.*/ + static const wspi_command_t cmd_reset_memory_2 = { + .cfg = WSPI_CFG_CMD(N25Q_CMD_RESET_MEMORY) | + WSPI_CFG_CMD_MODE_TWO_LINES, + .addr = 0, + .alt = 0, + .dummy = 0 + }; + + wspiCommand(devp->config->busp, &cmd_reset_enable_2); + wspiCommand(devp->config->busp, &cmd_reset_memory_2); +#endif + + /* Now the device should be in one bit mode for sure and we perform a + device reset.*/ + wspiCommand(devp->config->busp, &cmd_reset_enable_1); + wspiCommand(devp->config->busp, &cmd_reset_memory_1); +} +#endif /* #if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ + +static const uint8_t n25q_manufacturer_ids[] = N25Q_SUPPORTED_MANUFACTURE_IDS; +static const uint8_t n25q_memory_type_ids[] = N25Q_SUPPORTED_MEMORY_TYPE_IDS; + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +void snor_device_init(SNORDriver *devp) { + +#if JESD216_BUS_MODE == JESD216_BUS_MODE_SPI + /* Reading device ID.*/ + jesd216_cmd_receive(devp->config->busp, N25Q_CMD_READ_ID, + sizeof devp->device_id, devp->device_id); + +#else /* JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ + /* Attempting a reset of the XIP mode, it could be in an unexpected state + because a CPU reset does not reset the memory too.*/ + snor_reset_xip(devp); + + /* Attempting a eeset of the device, it could be in an unexpected state + because a CPU reset does not reset the memory too.*/ + n25q_reset_memory(devp); + + /* Reading device ID and unique ID.*/ + wspiReceive(devp->config->busp, &n25q_cmd_read_id, + sizeof devp->device_id, devp->device_id); +#endif /* JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ + + /* Checking if the device is white listed.*/ + osalDbgAssert(n25q_find_id(n25q_manufacturer_ids, + sizeof n25q_manufacturer_ids, + devp->device_id[0]), + "invalid manufacturer id"); + osalDbgAssert(n25q_find_id(n25q_memory_type_ids, + sizeof n25q_memory_type_ids, + devp->device_id[1]), + "invalid memory type id"); + +#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) && (SNOR_SWITCH_WIDTH == TRUE) + /* Setting up final bus width.*/ + wspiCommand(devp->config->busp, &n25q_cmd_write_enable); + wspiSend(devp->config->busp, &n25q_cmd_write_evconf, 1, n25q_evconf_value); + + { + uint8_t id[3]; + + /* Reading ID again for confirmation.*/ + jesd216_cmd_receive(devp->config->busp, N25Q_CMD_MULTIPLE_IO_READ_ID, + 3, id); + + /* Checking if the device is white listed.*/ + osalDbgAssert(memcmp(id, devp->device_id, 3) == 0, + "id confirmation failed"); + } +#endif + + /* Setting up the device size.*/ + snor_descriptor.sectors_count = (1U << (size_t)devp->device_id[2]) / + SECTOR_SIZE; + +#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) + { + static const uint8_t flash_conf[1] = { + (SNOR_READ_DUMMY_CYCLES << 4U) | 0x0FU + }; + + /* Setting up the dummy cycles to be used for fast read operations.*/ + jesd216_cmd(devp->config->busp, N25Q_CMD_WRITE_ENABLE); + jesd216_cmd_send(devp->config->busp, N25Q_CMD_WRITE_V_CONF_REGISTER, + 1, flash_conf); + } +#endif +} + +const flash_descriptor_t *snor_get_descriptor(void *instance) { + SNORDriver *devp = (SNORDriver *)instance; + + osalDbgCheck(instance != NULL); + osalDbgAssert((devp->state != FLASH_UNINIT) && (devp->state != FLASH_STOP), + "invalid state"); + + return &snor_descriptor; +} + +flash_error_t snor_device_read(SNORDriver *devp, flash_offset_t offset, + size_t n, uint8_t *rp) { + +#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI + /* Fast read command in WSPI mode.*/ + jesd216_cmd_addr_dummy_receive(devp->config->busp, N25Q_CMD_FAST_READ, + offset, SNOR_READ_DUMMY_CYCLES, n, rp); +#else + /* Normal read command in SPI mode.*/ + jesd216_cmd_addr_receive(devp->config->busp, N25Q_CMD_READ, + offset, n, rp); +#endif + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_program(SNORDriver *devp, flash_offset_t offset, + size_t n, const uint8_t *pp) { + + /* Data is programmed page by page.*/ + while (n > 0U) { + flash_error_t err; + + /* Data size that can be written in a single program page operation.*/ + size_t chunk = (size_t)(((offset | PAGE_MASK) + 1U) - offset); + if (chunk > n) { + chunk = n; + } + + /* Enabling write operation.*/ + jesd216_cmd(devp->config->busp, N25Q_CMD_WRITE_ENABLE); + + /* Page program command.*/ + jesd216_cmd_addr_send(devp->config->busp, N25Q_CMD_PAGE_PROGRAM, offset, + chunk, pp); + + /* Wait for status and check errors.*/ + err = n25q_poll_status(devp); + if (err != FLASH_NO_ERROR) { + + /* Bus released.*/ + jesd216_bus_release(devp->config->busp); + + return err; + } + + /* Next page.*/ + offset += chunk; + pp += chunk; + n -= chunk; + } + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_start_erase_all(SNORDriver *devp) { + + /* Enabling write operation.*/ + jesd216_cmd(devp->config->busp, N25Q_CMD_WRITE_ENABLE); + + /* Bulk erase command.*/ + jesd216_cmd(devp->config->busp, N25Q_CMD_BULK_ERASE); + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_start_erase_sector(SNORDriver *devp, + flash_sector_t sector) { + flash_offset_t offset = (flash_offset_t)(sector * SECTOR_SIZE); + + /* Enabling write operation.*/ + jesd216_cmd(devp->config->busp, N25Q_CMD_WRITE_ENABLE); + + /* Sector erase command.*/ + jesd216_cmd_addr(devp->config->busp, N25Q_CMD_SECTOR_ERASE, offset); + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_verify_erase(SNORDriver *devp, + flash_sector_t sector) { + uint8_t cmpbuf[SNOR_COMPARE_BUFFER_SIZE]; + flash_offset_t offset; + size_t n; + + /* Read command.*/ + offset = (flash_offset_t)(sector * SECTOR_SIZE); + n = SECTOR_SIZE; + while (n > 0U) { + uint8_t *p; + +#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI + jesd216_cmd_addr_dummy_receive(devp->config->busp, N25Q_CMD_FAST_READ, + offset, SNOR_READ_DUMMY_CYCLES, + sizeof cmpbuf, cmpbuf); +#else + /* Normal read command in SPI mode.*/ + jesd216_cmd_addr_receive(devp->config->busp, N25Q_CMD_READ, + offset, sizeof cmpbuf, cmpbuf); +#endif + + /* Checking for erased state of current buffer.*/ + for (p = cmpbuf; p < &cmpbuf[SNOR_COMPARE_BUFFER_SIZE]; p++) { + if (*p != 0xFFU) { + /* Ready state again.*/ + devp->state = FLASH_READY; + + return FLASH_ERROR_VERIFY; + } + } + + offset += sizeof cmpbuf; + n -= sizeof cmpbuf; + } + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_query_erase(SNORDriver *devp, uint32_t *msec) { + uint8_t sts; + + /* Read status command.*/ + jesd216_cmd_receive(devp->config->busp, N25Q_CMD_READ_FLAG_STATUS_REGISTER, + 1, &sts); + + /* If the P/E bit is zero (busy) or the flash in a suspended state then + report that the operation is still in progress.*/ + if (((sts & N25Q_FLAGS_PROGRAM_ERASE) == 0U) || + ((sts & N25Q_FLAGS_ERASE_SUSPEND) != 0U)) { + + /* Recommended time before polling again, this is a simplified + implementation.*/ + if (msec != NULL) { + *msec = 1U; + } + + return FLASH_BUSY_ERASING; + } + + /* Checking for errors.*/ + if ((sts & N25Q_FLAGS_ALL_ERRORS) != 0U) { + + /* Clearing status register.*/ + jesd216_cmd(devp->config->busp, N25Q_CMD_CLEAR_FLAG_STATUS_REGISTER); + + /* Erase operation failed.*/ + return FLASH_ERROR_ERASE; + } + + return FLASH_NO_ERROR; +} + +flash_error_t snor_device_read_sfdp(SNORDriver *devp, flash_offset_t offset, + size_t n, uint8_t *rp) { + + (void)devp; + (void)rp; + (void)offset; + (void)n; + + return FLASH_NO_ERROR; +} + +#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) || defined(__DOXYGEN__) +void snor_activate_xip(SNORDriver *devp) { + static const uint8_t flash_status_xip[1] = { + (SNOR_READ_DUMMY_CYCLES << 4U) | 0x07U + }; + + /* Activating XIP mode in the device.*/ + jesd216_cmd(devp->config->busp, N25Q_CMD_WRITE_ENABLE); + jesd216_cmd_send(devp->config->busp, N25Q_CMD_WRITE_V_CONF_REGISTER, + 1, flash_status_xip); +} + +void snor_reset_xip(SNORDriver *devp) { + static const uint8_t flash_conf[1] = { + (SNOR_READ_DUMMY_CYCLES << 4U) | 0x0FU + }; + wspi_command_t cmd; + uint8_t buf[1]; + + /* Resetting XIP mode by reading one byte without XIP confirmation bit.*/ + cmd.alt = 0xFF; + cmd.addr = 0; + cmd.dummy = SNOR_READ_DUMMY_CYCLES - 2; + cmd.cfg = WSPI_CFG_CMD_MODE_NONE | + WSPI_CFG_ADDR_SIZE_24 | +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L + WSPI_CFG_ADDR_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE | +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L + WSPI_CFG_ADDR_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES | +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI4L + WSPI_CFG_ADDR_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES | +#else + WSPI_CFG_ADDR_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES | +#endif + WSPI_CFG_ALT_MODE_FOUR_LINES | /* Always 4 lines, note.*/ + WSPI_CFG_ALT_SIZE_8; + wspiReceive(devp->config->busp, &cmd, 1, buf); + + /* Enabling write operation.*/ + jesd216_cmd(devp->config->busp, N25Q_CMD_WRITE_ENABLE); + + /* Rewriting volatile configuration register.*/ + jesd216_cmd_send(devp->config->busp, N25Q_CMD_WRITE_V_CONF_REGISTER, + 1, flash_conf); +} +#endif /* #if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ + +/** @} */ diff --git a/os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.h b/os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.h new file mode 100644 index 000000000..59db2c30d --- /dev/null +++ b/os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.h @@ -0,0 +1,148 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file flash_device.h + * @brief Micron N25Q serial flash driver header. + * + * @addtogroup MICRON_N25Q + * @ingroup MICRON_N25Q + * @{ + */ + +#ifndef FLASH_DEVICE_H +#define FLASH_DEVICE_H + +#include "hal_jesd216_flash.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Device identification + * @{ + */ +#define N25Q_SUPPORTED_MANUFACTURE_IDS {0x20} +#define N25Q_SUPPORTED_MEMORY_TYPE_IDS {0xBA, 0xBB} +/** @} */ + +/** + * @name Command codes + * @{ + */ +#define N25Q_CMD_RESET_ENABLE 0x66 +#define N25Q_CMD_RESET_MEMORY 0x99 +#define N25Q_CMD_READ_ID 0x9F +#define N25Q_CMD_MULTIPLE_IO_READ_ID 0xAF +#define N25Q_CMD_READ_DISCOVERY_PARAMETER 0x5A +#define N25Q_CMD_READ 0x03 +#define N25Q_CMD_FAST_READ 0x0B +#define N25Q_CMD_WRITE_ENABLE 0x06 +#define N25Q_CMD_WRITE_DISABLE 0x04 +#define N25Q_CMD_READ_STATUS_REGISTER 0x05 +#define N25Q_CMD_WRITE_STATUS_REGISTER 0x01 +#define N25Q_CMD_READ_LOCK_REGISTER 0xE8 +#define N25Q_CMD_WRITE_LOCK_REGISTER 0xE5 +#define N25Q_CMD_READ_FLAG_STATUS_REGISTER 0x70 +#define N25Q_CMD_CLEAR_FLAG_STATUS_REGISTER 0x50 +#define N25Q_CMD_READ_NV_CONFIGURATION_REGISTER 0xB5 +#define N25Q_CMD_WRITE_NV_CONFIGURATION_REGISTER 0xB1 +#define N25Q_CMD_READ_V_CONF_REGISTER 0x85 +#define N25Q_CMD_WRITE_V_CONF_REGISTER 0x81 +#define N25Q_CMD_READ_ENHANCED_V_CONF_REGISTER 0x65 +#define N25Q_CMD_WRITE_ENHANCED_V_CONF_REGISTER 0x61 +#define N25Q_CMD_PAGE_PROGRAM 0x02 +#define N25Q_CMD_SUBSECTOR_ERASE 0x20 +#define N25Q_CMD_SECTOR_ERASE 0xD8 +#define N25Q_CMD_BULK_ERASE 0xC7 +#define N25Q_CMD_PROGRAM_ERASE_RESUME 0x7A +#define N25Q_CMD_PROGRAM_ERASE_SUSPEND 0x75 +#define N25Q_CMD_READ_OTP_ARRAY 0x4B +#define N25Q_CMD_PROGRAM_OTP_ARRAY 0x42 +/** @} */ + +/** + * @name Flags status register bits + * @{ + */ +#define N25Q_FLAGS_PROGRAM_ERASE 0x80U +#define N25Q_FLAGS_ERASE_SUSPEND 0x40U +#define N25Q_FLAGS_ERASE_ERROR 0x20U +#define N25Q_FLAGS_PROGRAM_ERROR 0x10U +#define N25Q_FLAGS_VPP_ERROR 0x08U +#define N25Q_FLAGS_PROGRAM_SUSPEND 0x04U +#define N25Q_FLAGS_PROTECTION_ERROR 0x02U +#define N25Q_FLAGS_RESERVED 0x01U +#define N25Q_FLAGS_ALL_ERRORS (N25Q_FLAGS_ERASE_ERROR | \ + N25Q_FLAGS_PROGRAM_ERROR | \ + N25Q_FLAGS_VPP_ERROR | \ + N25Q_FLAGS_PROTECTION_ERROR) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern flash_descriptor_t snor_descriptor; +#endif + +#ifdef __cplusplus +extern "C" { +#endif +void snor_device_init(SNORDriver *devp); +const flash_descriptor_t *snor_get_descriptor(void *instance); +flash_error_t snor_device_read(SNORDriver *devp, flash_offset_t offset, + size_t n, uint8_t *rp); +flash_error_t snor_device_program(SNORDriver *devp, flash_offset_t offset, + size_t n, const uint8_t *pp); +flash_error_t snor_device_start_erase_all(SNORDriver *devp); +flash_error_t snor_device_start_erase_sector(SNORDriver *devp, + flash_sector_t sector); +flash_error_t snor_device_verify_erase(SNORDriver *devp, + flash_sector_t sector); +flash_error_t snor_device_query_erase(SNORDriver *devp, uint32_t *msec); +flash_error_t snor_device_read_sfdp(SNORDriver *devp, flash_offset_t offset, + size_t n, uint8_t *rp); +#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI + void snor_activate_xip(SNORDriver *devp); + void snor_reset_xip(SNORDriver *devp); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* FLASH_DEVICE_H */ + +/** @} */ + diff --git a/os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.mk b/os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.mk new file mode 100644 index 000000000..802a8388d --- /dev/null +++ b/os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.mk @@ -0,0 +1,14 @@ +# List of all the Micron N25Q device files. +N25QSRC := $(CHIBIOS)/os/hal/lib/peripherals/flash/hal_flash.c \ + $(CHIBIOS)/os/hal/lib/complex/serial_nor/hal_jesd216_flash.c \ + $(CHIBIOS)/os/hal/lib/complex/serial_nor/serial_nor.c \ + $(CHIBIOS)/os/hal/lib/complex/serial_nor/devices/micron_n25q/flash_device.c + +# Required include directories +N25QINC := $(CHIBIOS)/os/hal/lib/peripherals/flash \ + $(CHIBIOS)/os/hal/lib/complex/serial_nor \ + $(CHIBIOS)/os/hal/lib/complex/serial_nor/devices/micron_n25q + +# Shared variables +ALLCSRC += $(N25QSRC) +ALLINC += $(N25QINC) diff --git a/os/hal/lib/complex/serial_nor/devices/micron_n25q/micron_n25q.c b/os/hal/lib/complex/serial_nor/devices/micron_n25q/micron_n25q.c deleted file mode 100644 index 4240192fb..000000000 --- a/os/hal/lib/complex/serial_nor/devices/micron_n25q/micron_n25q.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file m25q_flash.c - * @brief Micron N25Q serial flash driver code. - * - * @addtogroup MICRON_N25Q - * @ingroup M25Q - * @{ - */ - -#include - -#include "hal.h" -#include "m25q.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define PAGE_SIZE 256U -#define PAGE_MASK (PAGE_SIZE - 1U) - -#if M25Q_USE_SUB_SECTORS == TRUE -#define SECTOR_SIZE 0x00001000U -#define CMD_SECTOR_ERASE M25Q_CMD_SUBSECTOR_ERASE -#else -#define SECTOR_SIZE 0x00010000U -#define CMD_SECTOR_ERASE M25Q_CMD_SECTOR_ERASE -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief N25Q128 descriptor. - */ -flash_descriptor_t m25q_descriptor = { - .attributes = FLASH_ATTR_ERASED_IS_ONE | FLASH_ATTR_REWRITABLE | - FLASH_ATTR_SUSPEND_ERASE_CAPABLE, - .page_size = 256U, - .sectors_count = 0U, /* It is overwritten.*/ - .sectors = NULL, - .sectors_size = SECTOR_SIZE, - .address = 0U -}; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI -/* Initial M25Q_CMD_READ_ID command.*/ -static const qspi_command_t m25q_cmd_read_id = { - .cfg = QSPI_CFG_CMD(M25Q_CMD_READ_ID) | -#if M25Q_SWITCH_WIDTH == TRUE - QSPI_CFG_CMD_MODE_ONE_LINE | - QSPI_CFG_DATA_MODE_ONE_LINE, -#else -#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L - QSPI_CFG_CMD_MODE_ONE_LINE | - QSPI_CFG_DATA_MODE_ONE_LINE, -#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L - QSPI_CFG_CMD_MODE_TWO_LINES | - QSPI_CFG_DATA_MODE_TWO_LINES, -#else - QSPI_CFG_CMD_MODE_FOUR_LINES | - QSPI_CFG_DATA_MODE_FOUR_LINES, -#endif -#endif - .addr = 0, - .alt = 0 -}; - -/* Initial M25Q_CMD_WRITE_ENHANCED_V_CONF_REGISTER command.*/ -static const qspi_command_t m25q_cmd_write_evconf = { - .cfg = QSPI_CFG_CMD(M25Q_CMD_WRITE_ENHANCED_V_CONF_REGISTER) | -#if M25Q_SWITCH_WIDTH == TRUE - QSPI_CFG_CMD_MODE_ONE_LINE | - QSPI_CFG_DATA_MODE_ONE_LINE, -#else -#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L - QSPI_CFG_CMD_MODE_ONE_LINE | - QSPI_CFG_DATA_MODE_ONE_LINE, -#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L - QSPI_CFG_CMD_MODE_TWO_LINES | - QSPI_CFG_DATA_MODE_TWO_LINES, -#else - QSPI_CFG_CMD_MODE_FOUR_LINES | - QSPI_CFG_DATA_MODE_FOUR_LINES, -#endif -#endif - .addr = 0, - .alt = 0 -}; - -/* Initial M25Q_CMD_WRITE_ENABLE command.*/ -static const qspi_command_t m25q_cmd_write_enable = { - .cfg = QSPI_CFG_CMD(M25Q_CMD_WRITE_ENABLE) | -#if M25Q_SWITCH_WIDTH == TRUE - QSPI_CFG_CMD_MODE_ONE_LINE, -#else -#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L - QSPI_CFG_CMD_MODE_ONE_LINE, -#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L - QSPI_CFG_CMD_MODE_TWO_LINES, -#else - QSPI_CFG_CMD_MODE_FOUR_LINES, -#endif -#endif - .addr = 0, - .alt = 0 -}; - -/* Bus width initialization.*/ -#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L -static const uint8_t m25q_evconf_value[1] = {0xCF}; -#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L -static const uint8_t m25q_evconf_value[1] = {0x8F}; -#else -static const uint8_t m25q_evconf_value[1] = {0x4F}; -#endif -#endif /* JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -static bool m25q_find_id(const uint8_t *set, size_t size, uint8_t element) { - size_t i; - - for (i = 0; i < size; i++) { - if (set[i] == element) { - return true; - } - } - return false; -} - -static flash_error_t m25q_poll_status(M25QDriver *devp) { - uint8_t sts; - - do { -#if M25Q_NICE_WAITING == TRUE - osalThreadSleepMilliseconds(1); -#endif - /* Read status command.*/ - jesd216_cmd_receive(devp->config->busp, M25Q_CMD_READ_FLAG_STATUS_REGISTER, - 1, &sts); - } while ((sts & M25Q_FLAGS_PROGRAM_ERASE) == 0U); - - /* Checking for errors.*/ - if ((sts & M25Q_FLAGS_ALL_ERRORS) != 0U) { - /* Clearing status register.*/ - jesd216_cmd(devp->config->busp, M25Q_CMD_CLEAR_FLAG_STATUS_REGISTER); - - /* Program operation failed.*/ - return FLASH_ERROR_PROGRAM; - } - - return FLASH_NO_ERROR; -} - -#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) || defined(__DOXYGEN__) -static void m25q_reset_memory(M25QDriver *devp) { - - /* 1x M25Q_CMD_RESET_ENABLE command.*/ - static const qspi_command_t cmd_reset_enable_1 = { - .cfg = QSPI_CFG_CMD(M25Q_CMD_RESET_ENABLE) | - QSPI_CFG_CMD_MODE_ONE_LINE, - .addr = 0, - .alt = 0 - }; - - /* 1x M25Q_CMD_RESET_MEMORY command.*/ - static const qspi_command_t cmd_reset_memory_1 = { - .cfg = QSPI_CFG_CMD(M25Q_CMD_RESET_MEMORY) | - QSPI_CFG_CMD_MODE_ONE_LINE, - .addr = 0, - .alt = 0 - }; - - /* If the device is in one bit mode then the following commands are - rejected because shorter than 8 bits. If the device is in multiple - bits mode then the commands are accepted and the device is reset to - one bit mode.*/ -#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI4L - /* 4x M25Q_CMD_RESET_ENABLE command.*/ - static const qspi_command_t cmd_reset_enable_4 = { - .cfg = QSPI_CFG_CMD(M25Q_CMD_RESET_ENABLE) | - QSPI_CFG_CMD_MODE_FOUR_LINES, - .addr = 0, - .alt = 0 - }; - - /* 4x M25Q_CMD_RESET_MEMORY command.*/ - static const qspi_command_t cmd_reset_memory_4 = { - .cfg = QSPI_CFG_CMD(M25Q_CMD_RESET_MEMORY) | - QSPI_CFG_CMD_MODE_FOUR_LINES, - .addr = 0, - .alt = 0 - }; - - qspiCommand(devp->config->busp, &cmd_reset_enable_4); - qspiCommand(devp->config->busp, &cmd_reset_memory_4); -#else - /* 2x M25Q_CMD_RESET_ENABLE command.*/ - static const qspi_command_t cmd_reset_enable_2 = { - .cfg = QSPI_CFG_CMD(M25Q_CMD_RESET_ENABLE) | - QSPI_CFG_CMD_MODE_TWO_LINES, - .addr = 0, - .alt = 0 - }; - - /* 2x M25Q_CMD_RESET_MEMORY command.*/ - static const qspi_command_t cmd_reset_memory_2 = { - .cfg = QSPI_CFG_CMD(M25Q_CMD_RESET_MEMORY) | - QSPI_CFG_CMD_MODE_TWO_LINES, - .addr = 0, - .alt = 0 - }; - - qspiCommand(devp->config->busp, &cmd_reset_enable_2); - qspiCommand(devp->config->busp, &cmd_reset_memory_2); -#endif - - /* Now the device should be in one bit mode for sure and we perform a - device reset.*/ - qspiCommand(devp->config->busp, &cmd_reset_enable_1); - qspiCommand(devp->config->busp, &cmd_reset_memory_1); -} -#endif /* #if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ - -static const uint8_t m25q_manufacturer_ids[] = M25Q_SUPPORTED_MANUFACTURE_IDS; -static const uint8_t m25q_memory_type_ids[] = M25Q_SUPPORTED_MEMORY_TYPE_IDS; - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -void m25q_device_init(M25QDriver *devp) { - -#if JESD216_BUS_MODE == JESD216_BUS_MODE_SPI - /* Reading device ID.*/ - jesd216_cmd_receive(devp->config->busp, M25Q_CMD_READ_ID, - sizeof devp->device_id, devp->device_id); - -#else /* JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ - /* Attempting a reset of the XIP mode, it could be in an unexpected state - because a CPU reset does not reset the memory too.*/ - m25q_reset_xip(devp); - - /* Attempting a eeset of the device, it could be in an unexpected state - because a CPU reset does not reset the memory too.*/ - m25q_reset_memory(devp); - - /* Reading device ID and unique ID.*/ - qspiReceive(devp->config->busp, &m25q_cmd_read_id, - sizeof devp->device_id, devp->device_id); -#endif /* JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ - - /* Checking if the device is white listed.*/ - osalDbgAssert(m25q_find_id(m25q_manufacturer_ids, - sizeof m25q_manufacturer_ids, - devp->device_id[0]), - "invalid manufacturer id"); - osalDbgAssert(m25q_find_id(m25q_memory_type_ids, - sizeof m25q_memory_type_ids, - devp->device_id[1]), - "invalid memory type id"); - -#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) && (M25Q_SWITCH_WIDTH == TRUE) - /* Setting up final bus width.*/ - qspiCommand(devp->config->busp, &m25q_cmd_write_enable); - qspiSend(devp->config->busp, &m25q_cmd_write_evconf, 1, m25q_evconf_value); - - { - uint8_t id[3]; - - /* Reading ID again for confirmation.*/ - jesd216_cmd_receive(devp->config->busp, M25Q_CMD_MULTIPLE_IO_READ_ID, - 3, id); - - /* Checking if the device is white listed.*/ - osalDbgAssert(memcmp(id, devp->device_id, 3) == 0, - "id confirmation failed"); - } -#endif - - /* Setting up the device size.*/ - m25q_descriptor.sectors_count = (1U << (size_t)devp->device_id[2]) / - SECTOR_SIZE; - -#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) - { - static const uint8_t flash_conf[1] = { - (M25Q_READ_DUMMY_CYCLES << 4U) | 0x0FU - }; - - /* Setting up the dummy cycles to be used for fast read operations.*/ - jesd216_cmd(devp->config->busp, M25Q_CMD_WRITE_ENABLE); - jesd216_cmd_send(devp->config->busp, M25Q_CMD_WRITE_V_CONF_REGISTER, - 1, flash_conf); - } -#endif -} - -const flash_descriptor_t *m25q_get_descriptor(void *instance) { - M25QDriver *devp = (M25QDriver *)instance; - - osalDbgCheck(instance != NULL); - osalDbgAssert((devp->state != FLASH_UNINIT) && (devp->state != FLASH_STOP), - "invalid state"); - - return &m25q_descriptor; -} - -flash_error_t m25q_device_read(M25QDriver *devp, flash_offset_t offset, - size_t n, uint8_t *rp) { - -#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI - /* Fast read command in QSPI mode.*/ - jesd216_cmd_addr_dummy_receive(devp->config->busp, M25Q_CMD_FAST_READ, - offset, M25Q_READ_DUMMY_CYCLES, n, rp); -#else - /* Normal read command in SPI mode.*/ - jesd216_cmd_addr_receive(devp->config->busp, M25Q_CMD_READ, - offset, n, rp); -#endif - - return FLASH_NO_ERROR; -} - -flash_error_t m25q_device_program(M25QDriver *devp, flash_offset_t offset, - size_t n, const uint8_t *pp) { - - /* Data is programmed page by page.*/ - while (n > 0U) { - flash_error_t err; - - /* Data size that can be written in a single program page operation.*/ - size_t chunk = (size_t)(((offset | PAGE_MASK) + 1U) - offset); - if (chunk > n) { - chunk = n; - } - - /* Enabling write operation.*/ - jesd216_cmd(devp->config->busp, M25Q_CMD_WRITE_ENABLE); - - /* Page program command.*/ - jesd216_cmd_addr_send(devp->config->busp, M25Q_CMD_PAGE_PROGRAM, offset, - chunk, pp); - - /* Wait for status and check errors.*/ - err = m25q_poll_status(devp); - if (err != FLASH_NO_ERROR) { - - /* Bus released.*/ - jesd216_bus_release(devp->config->busp); - - return err; - } - - /* Next page.*/ - offset += chunk; - pp += chunk; - n -= chunk; - } - - return FLASH_NO_ERROR; -} - -flash_error_t m25q_device_start_erase_all(M25QDriver *devp) { - - /* Enabling write operation.*/ - jesd216_cmd(devp->config->busp, M25Q_CMD_WRITE_ENABLE); - - /* Bulk erase command.*/ - jesd216_cmd(devp->config->busp, M25Q_CMD_BULK_ERASE); - - return FLASH_NO_ERROR; -} - -flash_error_t m25q_device_start_erase_sector(M25QDriver *devp, - flash_sector_t sector) { - flash_offset_t offset = (flash_offset_t)(sector * SECTOR_SIZE); - - /* Enabling write operation.*/ - jesd216_cmd(devp->config->busp, M25Q_CMD_WRITE_ENABLE); - - /* Sector erase command.*/ - jesd216_cmd_addr(devp->config->busp, M25Q_CMD_SECTOR_ERASE, offset); - - return FLASH_NO_ERROR; -} - -flash_error_t m25q_device_verify_erase(M25QDriver *devp, - flash_sector_t sector) { - uint8_t cmpbuf[M25Q_COMPARE_BUFFER_SIZE]; - flash_offset_t offset; - size_t n; - - /* Read command.*/ - offset = (flash_offset_t)(sector * SECTOR_SIZE); - n = SECTOR_SIZE; - while (n > 0U) { - uint8_t *p; - -#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI - jesd216_cmd_addr_dummy_receive(devp->config->busp, M25Q_CMD_FAST_READ, - offset, M25Q_READ_DUMMY_CYCLES, - sizeof cmpbuf, cmpbuf); -#else - /* Normal read command in SPI mode.*/ - jesd216_cmd_addr_receive(devp->config->busp, M25Q_CMD_READ, - offset, sizeof cmpbuf, cmpbuf); -#endif - - /* Checking for erased state of current buffer.*/ - for (p = cmpbuf; p < &cmpbuf[M25Q_COMPARE_BUFFER_SIZE]; p++) { - if (*p != 0xFFU) { - /* Ready state again.*/ - devp->state = FLASH_READY; - - return FLASH_ERROR_VERIFY; - } - } - - offset += sizeof cmpbuf; - n -= sizeof cmpbuf; - } - - return FLASH_NO_ERROR; -} - -flash_error_t m25q_device_query_erase(M25QDriver *devp, uint32_t *msec) { - uint8_t sts; - - /* Read status command.*/ - jesd216_cmd_receive(devp->config->busp, M25Q_CMD_READ_FLAG_STATUS_REGISTER, - 1, &sts); - - /* If the P/E bit is zero (busy) or the flash in a suspended state then - report that the operation is still in progress.*/ - if (((sts & M25Q_FLAGS_PROGRAM_ERASE) == 0U) || - ((sts & M25Q_FLAGS_ERASE_SUSPEND) != 0U)) { - - /* Recommended time before polling again, this is a simplified - implementation.*/ - if (msec != NULL) { - *msec = 1U; - } - - return FLASH_BUSY_ERASING; - } - - /* Checking for errors.*/ - if ((sts & M25Q_FLAGS_ALL_ERRORS) != 0U) { - - /* Clearing status register.*/ - jesd216_cmd(devp->config->busp, M25Q_CMD_CLEAR_FLAG_STATUS_REGISTER); - - /* Erase operation failed.*/ - return FLASH_ERROR_ERASE; - } - - return FLASH_NO_ERROR; -} - -flash_error_t m25q_device_read_sfdp(M25QDriver *devp, flash_offset_t offset, - size_t n, uint8_t *rp) { - - (void)devp; - (void)rp; - (void)offset; - (void)n; - - return FLASH_NO_ERROR; -} - -#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) || defined(__DOXYGEN__) -void m25q_activate_xip(M25QDriver *devp) { - static const uint8_t flash_status_xip[1] = { - (M25Q_READ_DUMMY_CYCLES << 4U) | 0x07U - }; - - /* Activating XIP mode in the device.*/ - jesd216_cmd(devp->config->busp, M25Q_CMD_WRITE_ENABLE); - jesd216_cmd_send(devp->config->busp, M25Q_CMD_WRITE_V_CONF_REGISTER, - 1, flash_status_xip); -} - -void m25q_reset_xip(M25QDriver *devp) { - static const uint8_t flash_conf[1] = { - (M25Q_READ_DUMMY_CYCLES << 4U) | 0x0FU - }; - qspi_command_t cmd; - uint8_t buf[1]; - - /* Resetting XIP mode by reading one byte without XIP confirmation bit.*/ - cmd.alt = 0xFF; - cmd.addr = 0; - cmd.cfg = QSPI_CFG_CMD_MODE_NONE | - QSPI_CFG_ADDR_SIZE_24 | -#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L - QSPI_CFG_ADDR_MODE_ONE_LINE | - QSPI_CFG_DATA_MODE_ONE_LINE | -#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L - QSPI_CFG_ADDR_MODE_TWO_LINES | - QSPI_CFG_DATA_MODE_TWO_LINES | -#else - QSPI_CFG_ADDR_MODE_FOUR_LINES | - QSPI_CFG_DATA_MODE_FOUR_LINES | -#endif - QSPI_CFG_ALT_MODE_FOUR_LINES | /* Always 4 lines, note.*/ - QSPI_CFG_ALT_SIZE_8 | - QSPI_CFG_DUMMY_CYCLES(M25Q_READ_DUMMY_CYCLES - 2); - qspiReceive(devp->config->busp, &cmd, 1, buf); - - /* Enabling write operation.*/ - jesd216_cmd(devp->config->busp, M25Q_CMD_WRITE_ENABLE); - - /* Rewriting volatile configuration register.*/ - jesd216_cmd_send(devp->config->busp, M25Q_CMD_WRITE_V_CONF_REGISTER, - 1, flash_conf); -} -#endif /* #if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ - -/** @} */ diff --git a/os/hal/lib/complex/serial_nor/devices/micron_n25q/micron_n25q.h b/os/hal/lib/complex/serial_nor/devices/micron_n25q/micron_n25q.h deleted file mode 100644 index d29f9439c..000000000 --- a/os/hal/lib/complex/serial_nor/devices/micron_n25q/micron_n25q.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file n25q_flash.h - * @brief Micron N25Q serial flash driver header. - * - * @addtogroup MICRON_N25Q - * @ingroup M25Q - * @{ - */ - -#ifndef MICRON_N25Q_H -#define MICRON_N25Q_H - -#include "hal_jesd216_flash.h" -#include "m25q_flash.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Device identification - * @{ - */ -#define M25Q_SUPPORTED_MANUFACTURE_IDS {0x20} -#define M25Q_SUPPORTED_MEMORY_TYPE_IDS {0xBA, 0xBB} -/** @} */ - -/** - * @name Command codes - * @{ - */ -#define M25Q_CMD_RESET_ENABLE 0x66 -#define M25Q_CMD_RESET_MEMORY 0x99 -#define M25Q_CMD_READ_ID 0x9F -#define M25Q_CMD_MULTIPLE_IO_READ_ID 0xAF -#define M25Q_CMD_READ_DISCOVERY_PARAMETER 0x5A -#define M25Q_CMD_READ 0x03 -#define M25Q_CMD_FAST_READ 0x0B -#define M25Q_CMD_WRITE_ENABLE 0x06 -#define M25Q_CMD_WRITE_DISABLE 0x04 -#define M25Q_CMD_READ_STATUS_REGISTER 0x05 -#define M25Q_CMD_WRITE_STATUS_REGISTER 0x01 -#define M25Q_CMD_READ_LOCK_REGISTER 0xE8 -#define M25Q_CMD_WRITE_LOCK_REGISTER 0xE5 -#define M25Q_CMD_READ_FLAG_STATUS_REGISTER 0x70 -#define M25Q_CMD_CLEAR_FLAG_STATUS_REGISTER 0x50 -#define M25Q_CMD_READ_NV_CONFIGURATION_REGISTER 0xB5 -#define M25Q_CMD_WRITE_NV_CONFIGURATION_REGISTER 0xB1 -#define M25Q_CMD_READ_V_CONF_REGISTER 0x85 -#define M25Q_CMD_WRITE_V_CONF_REGISTER 0x81 -#define M25Q_CMD_READ_ENHANCED_V_CONF_REGISTER 0x65 -#define M25Q_CMD_WRITE_ENHANCED_V_CONF_REGISTER 0x61 -#define M25Q_CMD_PAGE_PROGRAM 0x02 -#define M25Q_CMD_SUBSECTOR_ERASE 0x20 -#define M25Q_CMD_SECTOR_ERASE 0xD8 -#define M25Q_CMD_BULK_ERASE 0xC7 -#define M25Q_CMD_PROGRAM_ERASE_RESUME 0x7A -#define M25Q_CMD_PROGRAM_ERASE_SUSPEND 0x75 -#define M25Q_CMD_READ_OTP_ARRAY 0x4B -#define M25Q_CMD_PROGRAM_OTP_ARRAY 0x42 -/** @} */ - -/** - * @name Flags status register bits - * @{ - */ -#define M25Q_FLAGS_PROGRAM_ERASE 0x80U -#define M25Q_FLAGS_ERASE_SUSPEND 0x40U -#define M25Q_FLAGS_ERASE_ERROR 0x20U -#define M25Q_FLAGS_PROGRAM_ERROR 0x10U -#define M25Q_FLAGS_VPP_ERROR 0x08U -#define M25Q_FLAGS_PROGRAM_SUSPEND 0x04U -#define M25Q_FLAGS_PROTECTION_ERROR 0x02U -#define M25Q_FLAGS_RESERVED 0x01U -#define M25Q_FLAGS_ALL_ERRORS (M25Q_FLAGS_ERASE_ERROR | \ - M25Q_FLAGS_PROGRAM_ERROR | \ - M25Q_FLAGS_VPP_ERROR | \ - M25Q_FLAGS_PROTECTION_ERROR) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern flash_descriptor_t m25q_descriptor; -#endif - -#ifdef __cplusplus -extern "C" { -#endif -void m25q_device_init(M25QDriver *devp); -const flash_descriptor_t *m25q_get_descriptor(void *instance); -flash_error_t m25q_device_read(M25QDriver *devp, flash_offset_t offset, - size_t n, uint8_t *rp); -flash_error_t m25q_device_program(M25QDriver *devp, flash_offset_t offset, - size_t n, const uint8_t *pp); -flash_error_t m25q_device_start_erase_all(M25QDriver *devp); -flash_error_t m25q_device_start_erase_sector(M25QDriver *devp, - flash_sector_t sector); -flash_error_t m25q_device_verify_erase(M25QDriver *devp, - flash_sector_t sector); -flash_error_t m25q_device_query_erase(M25QDriver *devp, uint32_t *msec); -flash_error_t m25q_device_read_sfdp(M25QDriver *devp, flash_offset_t offset, - size_t n, uint8_t *rp); -#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI - void m25q_activate_xip(M25QDriver *devp); - void m25q_reset_xip(M25QDriver *devp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* MICRON_N25Q_H */ - -/** @} */ - diff --git a/os/hal/lib/complex/serial_nor/devices/micron_n25q/micron_n25q.mk b/os/hal/lib/complex/serial_nor/devices/micron_n25q/micron_n25q.mk deleted file mode 100644 index 143fec675..000000000 --- a/os/hal/lib/complex/serial_nor/devices/micron_n25q/micron_n25q.mk +++ /dev/null @@ -1,14 +0,0 @@ -# List of all the Micron N25Q device files. -M25QSRC := $(CHIBIOS)/os/hal/lib/peripherals/flash/hal_flash.c \ - $(CHIBIOS)/os/hal/lib/peripherals/flash/hal_jesd216_flash.c \ - $(CHIBIOS)/os/hal/lib/complex/m25q/serial_nor.c \ - $(CHIBIOS)/os/hal/lib/complex/m25q/devices/micron_n25q/micron_n25q.c - -# Required include directories -M25QINC := $(CHIBIOS)/os/hal/lib/peripherals/flash \ - $(CHIBIOS)/os/hal/lib/complex/m25q \ - $(CHIBIOS)/os/hal/lib/complex/m25q/devices/micron_n25q - -# Shared variables -ALLCSRC += $(M25QSRC) -ALLINC += $(M25QINC) diff --git a/os/hal/lib/complex/serial_nor/hal_jesd216_flash.c b/os/hal/lib/complex/serial_nor/hal_jesd216_flash.c new file mode 100644 index 000000000..6b81d1bec --- /dev/null +++ b/os/hal/lib/complex/serial_nor/hal_jesd216_flash.c @@ -0,0 +1,402 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_jesd216_flash.c + * @brief JESD216 compliant flash driver class code. + * + * @addtogroup HAL_JESD216_FLASH + * @{ + */ + +#include "hal.h" + +#include "hal_jesd216_flash.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +void jesd216_start(BUSDriver *busp, const BUSConfig *config) { + +#if JESD216_BUS_MODE == JESD216_BUS_MODE_SPI + spiStart(busp, config); +#else + wspiStart(busp, config); +#endif +} + +void jesd216_stop(BUSDriver *busp) { + +#if JESD216_BUS_MODE == JESD216_BUS_MODE_SPI + spiStop(busp); +#else + wspiStop(busp); +#endif +} + +void jesd216_cmd(BUSDriver *busp, uint32_t cmd) { +#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI + wspi_command_t mode; + + mode.cmd = cmd; + mode.dummy = 0U; + mode.cfg = 0U | +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES; +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES; +#endif + mode.addr = 0U; + mode.alt = 0U; + wspiCommand(busp, &mode); +#else + uint8_t buf[1]; + + spiSelect(busp); + buf[0] = cmd; + spiSend(busp, 1, buf); + spiUnselect(busp); +#endif +} + +void jesd216_cmd_receive(BUSDriver *busp, + uint32_t cmd, + size_t n, + uint8_t *p) { +#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI + wspi_command_t mode; + + mode.cmd = cmd; + mode.dummy = 0U; + mode.cfg = 0U | +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES; +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES; +#endif + mode.addr = 0U; + mode.alt = 0U; + wspiReceive(busp, &mode, n, p); +#else + uint8_t buf[1]; + + spiSelect(busp); + buf[0] = cmd; + spiSend(busp, 1, buf); + spiReceive(busp, n, p); + spiUnselect(busp); +#endif +} + +void jesd216_cmd_send(BUSDriver *busp, + uint32_t cmd, + size_t n, + const uint8_t *p) { +#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI + wspi_command_t mode; + + mode.cmd = cmd; + mode.dummy = 0U; + mode.cfg = 0U | +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES; +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES; +#endif + mode.addr = 0U; + mode.alt = 0U; + wspiSend(busp, &mode, n, p); +#else + uint8_t buf[1]; + + spiSelect(busp); + buf[0] = cmd; + spiSend(busp, 1, buf); + spiSend(busp, n, p); + spiUnselect(busp); +#endif +} + +void jesd216_cmd_addr(BUSDriver *busp, + uint32_t cmd, + flash_offset_t offset) { +#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI + wspi_command_t mode; + + mode.cmd = cmd; + mode.dummy = 0U; + mode.cfg = 0U | +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_ADDR_MODE_ONE_LINE | + WSPI_CFG_ADDR_SIZE_24; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_ADDR_MODE_TWO_LINES | + WSPI_CFG_ADDR_SIZE_24; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_ADDR_MODE_FOUR_LINES | + WSPI_CFG_ADDR_SIZE_24; +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES | + WSPI_CFG_ADDR_MODE_EIGHT_LINES | + WSPI_CFG_ADDR_SIZE_24; +#endif + mode.addr = offset; + mode.alt = 0U; + wspiCommand(busp, &mode); +#else + uint8_t buf[4]; + + spiSelect(busp); + buf[0] = cmd; + buf[1] = (uint8_t)(offset >> 16); + buf[2] = (uint8_t)(offset >> 8); + buf[3] = (uint8_t)(offset >> 0); + spiSend(busp, 4, buf); + spiUnselect(busp); +#endif +} + +void jesd216_cmd_addr_send(BUSDriver *busp, + uint32_t cmd, + flash_offset_t offset, + size_t n, + const uint8_t *p) { +#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI + wspi_command_t mode; + + mode.cmd = cmd; + mode.dummy = 0U; + mode.cfg = 0U | +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_ADDR_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_ADDR_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_ADDR_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES; +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES | + WSPI_CFG_ADDR_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES; +#endif + + /* Handling 32 bits addressing. + TODO: Address size should come from upper levels.*/ + if ((cmd & JESD216_CMD_EXTENDED_ADDRESSING) == 0) { + mode.cfg |= WSPI_CFG_ADDR_SIZE_24; + } + else { + mode.cfg |= WSPI_CFG_ADDR_SIZE_32; + } + + mode.addr = offset; + mode.alt = 0U; + wspiSend(busp, &mode, n, p); +#else + uint8_t buf[4]; + + spiSelect(busp); + buf[0] = cmd; + buf[1] = (uint8_t)(offset >> 16); + buf[2] = (uint8_t)(offset >> 8); + buf[3] = (uint8_t)(offset >> 0); + spiSend(busp, 4, buf); + spiSend(busp, n, p); + spiUnselect(busp); +#endif +} + +void jesd216_cmd_addr_receive(BUSDriver *busp, + uint32_t cmd, + flash_offset_t offset, + size_t n, + uint8_t *p) { +#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI + wspi_command_t mode; + + mode.cmd = cmd; + mode.dummy = 0U; + mode.cfg = 0U | +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_ADDR_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_ADDR_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_ADDR_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES; +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES | + WSPI_CFG_ADDR_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES; +#endif + + /* Handling 32 bits addressing. + TODO: Address size should come from upper levels.*/ + if ((cmd & JESD216_CMD_EXTENDED_ADDRESSING) == 0) { + mode .cfg |= WSPI_CFG_ADDR_SIZE_24; + } + else { + mode .cfg |= WSPI_CFG_ADDR_SIZE_32; + } + + mode.addr = offset; + mode.alt = 0U; + wspiReceive(busp, &mode, n, p); +#else + uint8_t buf[4]; + + spiSelect(busp); + buf[0] = cmd; + buf[1] = (uint8_t)(offset >> 16); + buf[2] = (uint8_t)(offset >> 8); + buf[3] = (uint8_t)(offset >> 0); + spiSend(busp, 4, buf); + spiReceive(busp, n, p); + spiUnselect(busp); +#endif +} + +#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) || defined(__DOXYGEN__) +void jesd216_cmd_addr_dummy_receive(BUSDriver *busp, + uint32_t cmd, + flash_offset_t offset, + uint32_t dummy, + size_t n, + uint8_t *p) { + wspi_command_t mode; + + mode.cmd = cmd; + mode.dummy = dummy; + mode.cfg = 0U | +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_ADDR_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_ADDR_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES; +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI4L + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_ADDR_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES; +#else + WSPI_CFG_CMD_MODE_EIGHT_LINES | + WSPI_CFG_ADDR_MODE_EIGHT_LINES | + WSPI_CFG_DATA_MODE_EIGHT_LINES; +#endif + + /* Handling 32 bits addressing. + TODO: Address size should come from upper levels.*/ + if ((cmd & JESD216_CMD_EXTENDED_ADDRESSING) == 0) { + mode .cfg |= WSPI_CFG_ADDR_SIZE_24; + } + else { + mode .cfg |= WSPI_CFG_ADDR_SIZE_32; + } + + mode.addr = offset; + mode.alt = 0U; + wspiReceive(busp, &mode, n, p); +} +#endif /* JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ + +#if ((JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) && \ + (JESD216_SHARED_BUS == TRUE)) || defined(__DOXYGEN__) +void jesd216_bus_acquire(BUSDriver *busp, const BUSConfig *config) { + + (void)config; + + wspiAcquireBus(busp); + if (busp->config != config) { + wspiStart(busp, config); + } +} + +void jesd216_bus_release(BUSDriver *busp) { + + wspiReleaseBus(busp); +} +#elif (JESD216_BUS_MODE == JESD216_BUS_MODE_SPI) && \ + (JESD216_SHARED_BUS == TRUE) +void jesd216_bus_acquire(BUSDriver *busp, const BUSConfig *config) { + + spiAcquireBus(busp); + if (busp->config != config) { + spiStart(busp, config); + } +} + +void jesd216_bus_release(BUSDriver *busp) { + + spiReleaseBus(busp); +} +#else +#define jesd216_bus_acquire(busp) +#define jesd216_bus_release(busp) +#endif + +/** @} */ diff --git a/os/hal/lib/complex/serial_nor/hal_jesd216_flash.h b/os/hal/lib/complex/serial_nor/hal_jesd216_flash.h new file mode 100644 index 000000000..63ad44e71 --- /dev/null +++ b/os/hal/lib/complex/serial_nor/hal_jesd216_flash.h @@ -0,0 +1,223 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_jesd216_flash.h + * @brief JESD216 compliant flash driver class header. + * + * @addtogroup HAL_JESD216_FLASH + * @{ + */ + +#ifndef HAL_JESD216_FLASH_H +#define HAL_JESD216_FLASH_H + +#include "hal_flash.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Common command codes + * @{ + */ +#define JESD216_CMD_READ_ID 0x9FU +#define JESD216_CMD_READ 0x03U +#define JESD216_CMD_WRITE_ENABLE 0x06U +#define JESD216_CMD_WRITE_DISABLE 0x04U +#define JESD216_CMD_READ_STATUS_REGISTER 0x05U +#define JESD216_CMD_WRITE_STATUS_REGISTER 0x01U +#define JESD216_CMD_PAGE_PROGRAM 0x02U +#define JESD216_CMD_ERASE_4K 0x20U +#define JESD216_CMD_ERASE_BULK 0xC7U +#define JESD216_CMD_PROGRAM_ERASE_RESUME 0x7AU +#define JESD216_CMD_PROGRAM_ERASE_SUSPEND 0x75U +#define JESD216_CMD_READ_OTP_ARRAY 0x4BU +#define JESD216_CMD_PROGRAM_OTP_ARRAY 0x42U +/** @} */ + +/** + * @name Command options + * @{ + */ +#define JESD216_CMD_EXTENDED_ADDRESSING 0x80000000U +/** @} */ + +/** + * @name Bus interface. + * @{ + */ +#define JESD216_BUS_MODE_SPI 0U +#define JESD216_BUS_MODE_WSPI1L 1U +#define JESD216_BUS_MODE_WSPI2L 2U +#define JESD216_BUS_MODE_WSPI4L 4U +#define JESD216_BUS_MODE_WSPI8L 8U +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Physical transport interface. + */ +#if !defined(JESD216_BUS_MODE) || defined(__DOXYGEN__) +#define JESD216_BUS_MODE JESD216_BUS_MODE_WSPI4L +#endif + +/** + * @brief Shared bus switch. + * @details If set to @p TRUE the device acquires bus ownership + * on each transaction. + * @note Requires @p SPI_USE_MUTUAL_EXCLUSION or + * @p SPI_USE_MUTUAL_EXCLUSION. + */ +#if !defined(JESD216_SHARED_BUS) || defined(__DOXYGEN__) +#define JESD216_SHARED_BUS TRUE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (JESD216_BUS_MODE == JESD216_BUS_MODE_SPI) && (HAL_USE_SPI == FALSE) +#error "JESD216_BUS_MODE_SPI requires HAL_USE_SPI" +#endif + +#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) && (HAL_USE_WSPI == FALSE) +#error "JESD216_BUS_MODE_WSPIxL requires HAL_USE_WSPI" +#endif + +#if (JESD216_BUS_MODE == JESD216_BUS_MODE_SPI) && \ + (JESD216_SHARED_BUS == TRUE) && \ + (SPI_USE_MUTUAL_EXCLUSION == FALSE) +#error "JESD216_SHARED_SPI requires SPI_USE_MUTUAL_EXCLUSION" +#endif + +#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) && \ + (JESD216_BUS_MODE != JESD216_BUS_MODE_WSPI1L) && \ + (JESD216_BUS_MODE != JESD216_BUS_MODE_WSPI2L) && \ + (JESD216_BUS_MODE != JESD216_BUS_MODE_WSPI4L) && \ + (JESD216_BUS_MODE != JESD216_BUS_MODE_WSPI8L) +#error "invalid JESD216_BUS_MODE selected" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +#if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) || defined(__DOXYGEN__) +#define BUSConfig WSPIConfig +#define BUSDriver WSPIDriver +#else +#define BUSConfig SPIConfig +#define BUSDriver SPIDriver +#endif + +#define _jesd216_config \ + BUSDriver *busp; \ + const BUSConfig *buscfg; + +/** + * @brief @p JESD215Flash specific methods. + */ +#define _jesd216_flash_methods_alone \ + /* Read SFDP.*/ \ + flash_error_t (*read_sfdp)(void *instance, \ + flash_offset_t offset, \ + size_t n, \ + uint8_t *rp); + +/** + * @brief @p JESD215Flash specific methods with inherited ones. + */ +#define _jesd216_flash_methods \ + _base_flash_methods \ + _jesd216_flash_methods_alone + +/** + * @brief @p JESD215Flash virtual methods table. + */ +struct JESD215FlashVMT { + _jesd216_flash_methods +}; + +/** + * @brief @p JESD215Flash specific data. + */ +#define _jesd216_flash_data \ + _base_flash_data + +/** + * @brief Base flash class. + */ +typedef struct { + /** @brief Virtual Methods Table.*/ + const struct JESD215FlashVMT *vmt; + _jesd216_flash_data +} JESD215Flash; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Macro Functions (BaseFlash) + * @{ + */ +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void jesd216_start(BUSDriver *busp, const BUSConfig *config); + void jesd216_stop(BUSDriver *busp); + void jesd216_cmd(BUSDriver *busp, uint32_t cmd); + void jesd216_cmd_receive(BUSDriver *busp, uint32_t cmd, + size_t n, uint8_t *p); + void jesd216_cmd_send(BUSDriver *busp, uint32_t cmd, + size_t n, const uint8_t *p); + void jesd216_cmd_addr(BUSDriver *busp, uint32_t cmd, flash_offset_t offset); + void jesd216_cmd_addr_send(BUSDriver *busp, uint32_t cmd, + flash_offset_t offset, size_t n, const uint8_t *p); + void jesd216_cmd_addr_receive(BUSDriver *busp, uint32_t cmd, + flash_offset_t offset, size_t n, uint8_t *p); +#if JESD216_BUS_MODE != JESD216_BUS_MODE_SPI + void jesd216_cmd_addr_dummy_receive(BUSDriver *busp, uint32_t cmd, + flash_offset_t offset, uint32_t dummy, + size_t n, uint8_t *p); +#endif /* JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ +#if JESD216_SHARED_BUS == TRUE + void jesd216_bus_acquire(BUSDriver *busp, const BUSConfig *config); + void jesd216_bus_release(BUSDriver *busp); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* HAL_JESD216_FLASH_H */ + +/** @} */ diff --git a/os/hal/lib/complex/serial_nor/serial_nor.c b/os/hal/lib/complex/serial_nor/serial_nor.c index b4c0970b7..3c0b2cd28 100644 --- a/os/hal/lib/complex/serial_nor/serial_nor.c +++ b/os/hal/lib/complex/serial_nor/serial_nor.c @@ -24,7 +24,7 @@ */ #include "hal.h" -#include "m25q.h" +#include "serial_nor.h" /*===========================================================================*/ /* Driver local definitions. */ @@ -38,42 +38,42 @@ /* Driver local variables and types. */ /*===========================================================================*/ -static flash_error_t m25q_read(void *instance, flash_offset_t offset, +static flash_error_t snor_read(void *instance, flash_offset_t offset, size_t n, uint8_t *rp); -static flash_error_t m25q_program(void *instance, flash_offset_t offset, +static flash_error_t snor_program(void *instance, flash_offset_t offset, size_t n, const uint8_t *pp); -static flash_error_t m25q_start_erase_all(void *instance); -static flash_error_t m25q_start_erase_sector(void *instance, +static flash_error_t snor_start_erase_all(void *instance); +static flash_error_t snor_start_erase_sector(void *instance, flash_sector_t sector); -static flash_error_t m25q_verify_erase(void *instance, +static flash_error_t snor_verify_erase(void *instance, flash_sector_t sector); -static flash_error_t m25q_query_erase(void *instance, uint32_t *msec); -static flash_error_t m25q_read_sfdp(void *instance, flash_offset_t offset, +static flash_error_t snor_query_erase(void *instance, uint32_t *msec); +static flash_error_t snor_read_sfdp(void *instance, flash_offset_t offset, size_t n, uint8_t *rp); /** * @brief Virtual methods table. */ -static const struct M25QDriverVMT m25q_vmt = { +static const struct SNORDriverVMT snor_vmt = { (size_t)0, - m25q_get_descriptor, m25q_read, m25q_program, - m25q_start_erase_all, m25q_start_erase_sector, - m25q_query_erase, m25q_verify_erase, - m25q_read_sfdp + snor_get_descriptor, snor_read, snor_program, + snor_start_erase_all, snor_start_erase_sector, + snor_query_erase, snor_verify_erase, + snor_read_sfdp }; /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ -static flash_error_t m25q_read(void *instance, flash_offset_t offset, +static flash_error_t snor_read(void *instance, flash_offset_t offset, size_t n, uint8_t *rp) { - M25QDriver *devp = (M25QDriver *)instance; + SNORDriver *devp = (SNORDriver *)instance; flash_error_t err; osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U)); - osalDbgCheck((size_t)offset + n <= (size_t)m25q_descriptor.sectors_count * - (size_t)m25q_descriptor.sectors_size); + osalDbgCheck((size_t)offset + n <= (size_t)snor_descriptor.sectors_count * + (size_t)snor_descriptor.sectors_size); osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), "invalid state"); @@ -88,7 +88,7 @@ static flash_error_t m25q_read(void *instance, flash_offset_t offset, devp->state = FLASH_READ; /* Actual read implementation.*/ - err = m25q_device_read(devp, offset, n, rp); + err = snor_device_read(devp, offset, n, rp); /* Ready state again.*/ devp->state = FLASH_READY; @@ -99,14 +99,14 @@ static flash_error_t m25q_read(void *instance, flash_offset_t offset, return err; } -static flash_error_t m25q_program(void *instance, flash_offset_t offset, +static flash_error_t snor_program(void *instance, flash_offset_t offset, size_t n, const uint8_t *pp) { - M25QDriver *devp = (M25QDriver *)instance; + SNORDriver *devp = (SNORDriver *)instance; flash_error_t err; osalDbgCheck((instance != NULL) && (pp != NULL) && (n > 0U)); - osalDbgCheck((size_t)offset + n <= (size_t)m25q_descriptor.sectors_count * - (size_t)m25q_descriptor.sectors_size); + osalDbgCheck((size_t)offset + n <= (size_t)snor_descriptor.sectors_count * + (size_t)snor_descriptor.sectors_size); osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), "invalid state"); @@ -121,7 +121,7 @@ static flash_error_t m25q_program(void *instance, flash_offset_t offset, devp->state = FLASH_PGM; /* Actual program implementation.*/ - err = m25q_device_program(devp, offset, n, pp); + err = snor_device_program(devp, offset, n, pp); /* Ready state again.*/ devp->state = FLASH_READY; @@ -132,8 +132,8 @@ static flash_error_t m25q_program(void *instance, flash_offset_t offset, return err; } -static flash_error_t m25q_start_erase_all(void *instance) { - M25QDriver *devp = (M25QDriver *)instance; +static flash_error_t snor_start_erase_all(void *instance) { + SNORDriver *devp = (SNORDriver *)instance; flash_error_t err; osalDbgCheck(instance != NULL); @@ -151,7 +151,7 @@ static flash_error_t m25q_start_erase_all(void *instance) { devp->state = FLASH_ERASE; /* Actual erase implementation.*/ - err = m25q_device_start_erase_all(devp); + err = snor_device_start_erase_all(devp); /* Ready state again.*/ devp->state = FLASH_READY; @@ -162,13 +162,13 @@ static flash_error_t m25q_start_erase_all(void *instance) { return err; } -static flash_error_t m25q_start_erase_sector(void *instance, +static flash_error_t snor_start_erase_sector(void *instance, flash_sector_t sector) { - M25QDriver *devp = (M25QDriver *)instance; + SNORDriver *devp = (SNORDriver *)instance; flash_error_t err; osalDbgCheck(instance != NULL); - osalDbgCheck(sector < m25q_descriptor.sectors_count); + osalDbgCheck(sector < snor_descriptor.sectors_count); osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), "invalid state"); @@ -183,7 +183,7 @@ static flash_error_t m25q_start_erase_sector(void *instance, devp->state = FLASH_ERASE; /* Actual erase implementation.*/ - err = m25q_device_start_erase_sector(devp, sector); + err = snor_device_start_erase_sector(devp, sector); /* Bus released.*/ jesd216_bus_release(devp->config->busp); @@ -191,13 +191,13 @@ static flash_error_t m25q_start_erase_sector(void *instance, return err; } -static flash_error_t m25q_verify_erase(void *instance, +static flash_error_t snor_verify_erase(void *instance, flash_sector_t sector) { - M25QDriver *devp = (M25QDriver *)instance; + SNORDriver *devp = (SNORDriver *)instance; flash_error_t err; osalDbgCheck(instance != NULL); - osalDbgCheck(sector < m25q_descriptor.sectors_count); + osalDbgCheck(sector < snor_descriptor.sectors_count); osalDbgAssert((devp->state == FLASH_READY) || (devp->state == FLASH_ERASE), "invalid state"); @@ -212,7 +212,7 @@ static flash_error_t m25q_verify_erase(void *instance, devp->state = FLASH_READ; /* Actual verify erase implementation.*/ - err = m25q_device_verify_erase(devp, sector); + err = snor_device_verify_erase(devp, sector); /* Ready state again.*/ devp->state = FLASH_READY; @@ -223,8 +223,8 @@ static flash_error_t m25q_verify_erase(void *instance, return err; } -static flash_error_t m25q_query_erase(void *instance, uint32_t *msec) { - M25QDriver *devp = (M25QDriver *)instance; +static flash_error_t snor_query_erase(void *instance, uint32_t *msec) { + SNORDriver *devp = (SNORDriver *)instance; flash_error_t err; osalDbgCheck(instance != NULL); @@ -238,7 +238,7 @@ static flash_error_t m25q_query_erase(void *instance, uint32_t *msec) { jesd216_bus_acquire(devp->config->busp, devp->config->buscfg); /* Actual query erase implementation.*/ - err = m25q_device_query_erase(devp, msec); + err = snor_device_query_erase(devp, msec); /* The device is ready to accept commands.*/ if (err == FLASH_NO_ERROR) { @@ -255,9 +255,9 @@ static flash_error_t m25q_query_erase(void *instance, uint32_t *msec) { return err; } -static flash_error_t m25q_read_sfdp(void *instance, flash_offset_t offset, +static flash_error_t snor_read_sfdp(void *instance, flash_offset_t offset, size_t n, uint8_t *rp) { - M25QDriver *devp = (M25QDriver *)instance; + SNORDriver *devp = (SNORDriver *)instance; flash_error_t err; osalDbgCheck((instance != NULL) && (rp != NULL) && (n > 0U)); @@ -272,7 +272,7 @@ static flash_error_t m25q_read_sfdp(void *instance, flash_offset_t offset, jesd216_bus_acquire(devp->config->busp, devp->config->buscfg); /* Actual read SFDP implementation.*/ - err = m25q_device_read_sfdp(devp, offset, n, rp); + err = snor_device_read_sfdp(devp, offset, n, rp); /* The device is ready to accept commands.*/ if (err == FLASH_NO_ERROR) { @@ -292,15 +292,15 @@ static flash_error_t m25q_read_sfdp(void *instance, flash_offset_t offset, /** * @brief Initializes an instance. * - * @param[out] devp pointer to the @p M25QDriver object + * @param[out] devp pointer to the @p SNORDriver object * * @init */ -void m25qObjectInit(M25QDriver *devp) { +void m25qObjectInit(SNORDriver *devp) { osalDbgCheck(devp != NULL); - devp->vmt = &m25q_vmt; + devp->vmt = &snor_vmt; devp->state = FLASH_STOP; devp->config = NULL; } @@ -308,12 +308,12 @@ void m25qObjectInit(M25QDriver *devp) { /** * @brief Configures and activates N25Q128 driver. * - * @param[in] devp pointer to the @p M25QDriver object + * @param[in] devp pointer to the @p SNORDriver object * @param[in] config pointer to the configuration * * @api */ -void m25qStart(M25QDriver *devp, const M25QConfig *config) { +void m25qStart(SNORDriver *devp, const SNORConfig *config) { osalDbgCheck((devp != NULL) && (config != NULL)); osalDbgAssert(devp->state != FLASH_UNINIT, "invalid state"); @@ -326,7 +326,7 @@ void m25qStart(M25QDriver *devp, const M25QConfig *config) { jesd216_bus_acquire(devp->config->busp, devp->config->buscfg); /* Device identification and initialization.*/ - m25q_device_init(devp); + snor_device_init(devp); /* Driver in ready state.*/ devp->state = FLASH_READY; @@ -339,11 +339,11 @@ void m25qStart(M25QDriver *devp, const M25QConfig *config) { /** * @brief Deactivates the N25Q128 driver. * - * @param[in] devp pointer to the @p M25QDriver object + * @param[in] devp pointer to the @p SNORDriver object * * @api */ -void m25qStop(M25QDriver *devp) { +void m25qStop(SNORDriver *devp) { osalDbgCheck(devp != NULL); osalDbgAssert(devp->state != FLASH_UNINIT, "invalid state"); @@ -368,51 +368,52 @@ void m25qStop(M25QDriver *devp) { } #if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) || defined(__DOXYGEN__) -#if (QSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__) +#if (WSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__) /** * @brief Enters the memory Mapping mode. - * @details The memory mapping mode is only available when the QSPI mode - * is selected and the underlying QSPI controller supports the + * @details The memory mapping mode is only available when the WSPI mode + * is selected and the underlying WSPI controller supports the * feature. * - * @param[in] devp pointer to the @p M25QDriver object + * @param[in] devp pointer to the @p SNORDriver object * @param[out] addrp pointer to the memory start address of the mapped * flash or @p NULL * * @api */ -void m25qMemoryMap(M25QDriver *devp, uint8_t **addrp) { - qspi_command_t cmd; +void m25qMemoryMap(SNORDriver *devp, uint8_t **addrp) { + wspi_command_t cmd; /* Bus acquisition.*/ jesd216_bus_acquire(devp->config->busp, devp->config->buscfg); /* Activating XIP mode in the device.*/ - m25q_activate_xip(devp); - - /* Putting the QSPI driver in memory mapped mode.*/ - cmd.cfg = QSPI_CFG_CMD(M25Q_CMD_FAST_READ) | - QSPI_CFG_ADDR_SIZE_24 | -#if JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI1L - QSPI_CFG_CMD_MODE_ONE_LINE | - QSPI_CFG_ADDR_MODE_ONE_LINE | - QSPI_CFG_DATA_MODE_ONE_LINE | -#elif JESD216_BUS_MODE == JESD216_BUS_MODE_QSPI2L - QSPI_CFG_CMD_MODE_TWO_LINES | - QSPI_CFG_ADDR_MODE_TWO_LINES | - QSPI_CFG_DATA_MODE_TWO_LINES | + snor_activate_xip(devp); + + /* Putting the WSPI driver in memory mapped mode. + TODO: Put this in the device code.*/ + cmd.cmd = N25Q_CMD_FAST_READ; + cmd.dummy = SNOR_READ_DUMMY_CYCLES - 2; + cmd.cfg = WSPI_CFG_ADDR_SIZE_24 | +#if JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI1L + WSPI_CFG_CMD_MODE_ONE_LINE | + WSPI_CFG_ADDR_MODE_ONE_LINE | + WSPI_CFG_DATA_MODE_ONE_LINE | +#elif JESD216_BUS_MODE == JESD216_BUS_MODE_WSPI2L + WSPI_CFG_CMD_MODE_TWO_LINES | + WSPI_CFG_ADDR_MODE_TWO_LINES | + WSPI_CFG_DATA_MODE_TWO_LINES | #else - QSPI_CFG_CMD_MODE_FOUR_LINES | - QSPI_CFG_ADDR_MODE_FOUR_LINES | - QSPI_CFG_DATA_MODE_FOUR_LINES | + WSPI_CFG_CMD_MODE_FOUR_LINES | + WSPI_CFG_ADDR_MODE_FOUR_LINES | + WSPI_CFG_DATA_MODE_FOUR_LINES | #endif - QSPI_CFG_ALT_MODE_FOUR_LINES | /* Always 4 lines, note.*/ - QSPI_CFG_ALT_SIZE_8 | - QSPI_CFG_SIOO | - QSPI_CFG_DUMMY_CYCLES(M25Q_READ_DUMMY_CYCLES - 2); + WSPI_CFG_ALT_MODE_FOUR_LINES | /* Always 4 lines, note.*/ + WSPI_CFG_ALT_SIZE_8 | + WSPI_CFG_SIOO; - /* Starting QSPI memory mapped mode.*/ - qspiMapFlash(devp->config->busp, &cmd, addrp); + /* Starting WSPI memory mapped mode.*/ + wspiMapFlash(devp->config->busp, &cmd, addrp); /* Bus release.*/ jesd216_bus_release(devp->config->busp); @@ -421,24 +422,24 @@ void m25qMemoryMap(M25QDriver *devp, uint8_t **addrp) { /** * @brief Leaves the memory Mapping mode. * - * @param[in] devp pointer to the @p M25QDriver object + * @param[in] devp pointer to the @p SNORDriver object * * @api */ -void m25qMemoryUnmap(M25QDriver *devp) { +void m25qMemoryUnmap(SNORDriver *devp) { /* Bus acquisition.*/ jesd216_bus_acquire(devp->config->busp, devp->config->buscfg); - /* Stopping QSPI memory mapped mode.*/ - qspiUnmapFlash(devp->config->busp); + /* Stopping WSPI memory mapped mode.*/ + wspiUnmapFlash(devp->config->busp); - m25q_reset_xip(devp); + snor_reset_xip(devp); /* Bus release.*/ jesd216_bus_release(devp->config->busp); } -#endif /* QSPI_SUPPORTS_MEMMAP == TRUE */ +#endif /* WSPI_SUPPORTS_MEMMAP == TRUE */ #endif /* JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ /** @} */ diff --git a/os/hal/lib/complex/serial_nor/serial_nor.h b/os/hal/lib/complex/serial_nor/serial_nor.h index d33dd9f48..9882c9d54 100644 --- a/os/hal/lib/complex/serial_nor/serial_nor.h +++ b/os/hal/lib/complex/serial_nor/serial_nor.h @@ -45,8 +45,8 @@ * @details This is the number of dummy cycles to be used for fast read * operations. */ -#if !defined(M25Q_READ_DUMMY_CYCLES) || defined(__DOXYGEN__) -#define M25Q_READ_DUMMY_CYCLES 8 +#if !defined(SNOR_READ_DUMMY_CYCLES) || defined(__DOXYGEN__) +#define SNOR_READ_DUMMY_CYCLES 8 #endif /** @@ -57,8 +57,8 @@ * Register then this option is not required. * @note This option is only valid in QSPI bus modes. */ -#if !defined(M25Q_SWITCH_WIDTH) || defined(__DOXYGEN__) -#define M25Q_SWITCH_WIDTH TRUE +#if !defined(SNOR_SWITCH_WIDTH) || defined(__DOXYGEN__) +#define SNOR_SWITCH_WIDTH TRUE #endif /** @@ -67,15 +67,15 @@ * routines releasing some extra CPU time for threads with lower * priority, this may slow down the driver a bit however. */ -#if !defined(M25Q_NICE_WAITING) || defined(__DOXYGEN__) -#define M25Q_NICE_WAITING TRUE +#if !defined(SNOR_NICE_WAITING) || defined(__DOXYGEN__) +#define SNOR_NICE_WAITING TRUE #endif /** * @brief Uses 4kB sub-sectors rather than 64kB sectors. */ -#if !defined(M25Q_USE_SUB_SECTORS) || defined(__DOXYGEN__) -#define M25Q_USE_SUB_SECTORS FALSE +#if !defined(SNOR_USE_SUB_SECTORS) || defined(__DOXYGEN__) +#define SNOR_USE_SUB_SECTORS FALSE #endif /** @@ -85,8 +85,8 @@ * Larger buffers lead to better verify performance but increase * stack usage for that function. */ -#if !defined(M25Q_COMPARE_BUFFER_SIZE) || defined(__DOXYGEN__) -#define M25Q_COMPARE_BUFFER_SIZE 32 +#if !defined(SNOR_COMPARE_BUFFER_SIZE) || defined(__DOXYGEN__) +#define SNOR_COMPARE_BUFFER_SIZE 32 #endif /** @} */ @@ -94,12 +94,12 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if (M25Q_READ_DUMMY_CYCLES < 1) || (M25Q_READ_DUMMY_CYCLES > 15) -#error "invalid M25Q_READ_DUMMY_CYCLES value (1..15)" +#if (SNOR_READ_DUMMY_CYCLES < 1) || (SNOR_READ_DUMMY_CYCLES > 15) +#error "invalid SNOR_READ_DUMMY_CYCLES value (1..15)" #endif -#if (M25Q_COMPARE_BUFFER_SIZE & (M25Q_COMPARE_BUFFER_SIZE - 1)) != 0 -#error "invalid M25Q_COMPARE_BUFFER_SIZE value" +#if (SNOR_COMPARE_BUFFER_SIZE & (SNOR_COMPARE_BUFFER_SIZE - 1)) != 0 +#error "invalid SNOR_COMPARE_BUFFER_SIZE value" #endif /*===========================================================================*/ @@ -111,43 +111,43 @@ */ typedef struct { _jesd216_config -} M25QConfig; +} SNORConfig; /** - * @brief @p M25Q specific methods. + * @brief @p SNOR specific methods. */ -#define _m25q_methods \ +#define _snor_methods \ _jesd216_flash_methods /** * @extends JESD216FlashVMT * - * @brief @p M25Q virtual methods table. + * @brief @p SNOR virtual methods table. */ -struct M25QDriverVMT { - _m25q_methods +struct SNORDriverVMT { + _snor_methods }; /** * @extends JESD216Flash * - * @brief Type of M25Q flash class. + * @brief Type of SNOR flash class. */ typedef struct { /** - * @brief M25QDriver Virtual Methods Table. + * @brief SNORDriver Virtual Methods Table. */ - const struct M25QDriverVMT *vmt; + const struct SNORDriverVMT *vmt; _jesd216_flash_data /** * @brief Current configuration data. */ - const M25QConfig *config; + const SNORConfig *config; /** * @brief Device ID and unique ID. */ uint8_t device_id[20]; -} M25QDriver; +} SNORDriver; /*===========================================================================*/ /* Driver macros. */ @@ -160,13 +160,13 @@ typedef struct { #ifdef __cplusplus extern "C" { #endif - void m25qObjectInit(M25QDriver *devp); - void m25qStart(M25QDriver *devp, const M25QConfig *config); - void m25qStop(M25QDriver *devp); + void m25qObjectInit(SNORDriver *devp); + void m25qStart(SNORDriver *devp, const SNORConfig *config); + void m25qStop(SNORDriver *devp); #if (JESD216_BUS_MODE != JESD216_BUS_MODE_SPI) || defined(__DOXYGEN__) -#if (QSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__) - void m25qMemoryMap(M25QDriver *devp, uint8_t ** addrp); - void m25qMemoryUnmap(M25QDriver *devp); +#if (WSPI_SUPPORTS_MEMMAP == TRUE) || defined(__DOXYGEN__) + void m25qMemoryMap(SNORDriver *devp, uint8_t ** addrp); + void m25qMemoryUnmap(SNORDriver *devp); #endif /* QSPI_SUPPORTS_MEMMAP == TRUE */ #endif /* JESD216_BUS_MODE != JESD216_BUS_MODE_SPI */ #ifdef __cplusplus @@ -174,7 +174,7 @@ extern "C" { #endif /* Device-specific implementations.*/ -#include "m25q_flash.h" +#include "flash_device.h" #endif /* M25Q_H */ -- cgit v1.2.3