From 5995950eb617d50beb043576eccf6f112bce188e Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sun, 5 Feb 2017 15:08:12 +0000 Subject: MISRA-related fixes. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10085 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/hal_qspi.h | 73 ++++++++++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 36 deletions(-) (limited to 'os/hal/include') diff --git a/os/hal/include/hal_qspi.h b/os/hal/include/hal_qspi.h index 0b67923b3..c5f0f1c22 100644 --- a/os/hal/include/hal_qspi.h +++ b/os/hal/include/hal_qspi.h @@ -35,42 +35,43 @@ * @name Transfer options * @{ */ -#define QSPI_CFG_CMD_MASK (0xFFU << 0U) -#define QSPI_CFG_CMD(n) ((n) << 0U) -#define QSPI_CFG_CMD_MODE_MASK (3U << 8U) -#define QSPI_CFG_CMD_MODE_NONE (0U << 8U) -#define QSPI_CFG_CMD_MODE_ONE_LINE (1U << 8U) -#define QSPI_CFG_CMD_MODE_TWO_LINES (2U << 8U) -#define QSPI_CFG_CMD_MODE_FOUR_LINES (3U << 8U) -#define QSPI_CFG_ADDR_MODE_MASK (3U << 10U) -#define QSPI_CFG_ADDR_MODE_NONE (0U << 10U) -#define QSPI_CFG_ADDR_MODE_ONE_LINE (1U << 10U) -#define QSPI_CFG_ADDR_MODE_TWO_LINES (2U << 10U) -#define QSPI_CFG_ADDR_MODE_FOUR_LINES (3U << 10U) -#define QSPI_CFG_ADDR_SIZE_MASK (3U << 12U) -#define QSPI_CFG_ADDR_SIZE_8 (0U << 12U) -#define QSPI_CFG_ADDR_SIZE_16 (1U << 12U) -#define QSPI_CFG_ADDR_SIZE_24 (2U << 12U) -#define QSPI_CFG_ADDR_SIZE_32 (3U << 12U) -#define QSPI_CFG_ALT_MODE_MASK (3U << 14U) -#define QSPI_CFG_ALT_MODE_NONE (0U << 14U) -#define QSPI_CFG_ALT_MODE_ONE_LINE (1U << 14U) -#define QSPI_CFG_ALT_MODE_TWO_LINES (2U << 14U) -#define QSPI_CFG_ALT_MODE_FOUR_LINES (3U << 14U) -#define QSPI_CFG_ALT_SIZE_MASK (3U << 16U) -#define QSPI_CFG_ALT_SIZE_8 (0U << 16U) -#define QSPI_CFG_ALT_SIZE_16 (1U << 16U) -#define QSPI_CFG_ALT_SIZE_24 (2U << 16U) -#define QSPI_CFG_ALT_SIZE_32 (3U << 16U) -#define QSPI_CFG_DUMMY_CYCLES_MASK (0x1FU << 18U) -#define QSPI_CFG_DUMMY_CYCLES(n) ((n) << 18U) -#define QSPI_CFG_DATA_MODE_MASK (3U << 24U) -#define QSPI_CFG_DATA_MODE_NONE (0U << 24U) -#define QSPI_CFG_DATA_MODE_ONE_LINE (1U << 24U) -#define QSPI_CFG_DATA_MODE_TWO_LINES (2U << 24U) -#define QSPI_CFG_DATA_MODE_FOUR_LINES (3U << 24U) -#define QSPI_CFG_SIOO (1U << 28U) -#define QSPI_CFG_DDRM (1U << 31U) +#define QSPI_CFG_CMD_MASK (0xFFLU << 0LU) +#define QSPI_CFG_CMD(n) ((n) << 0LU) +#define QSPI_CFG_CMD_MODE_MASK (3LU << 8LU) +#define QSPI_CFG_CMD_MODE_NONE (0LU << 8LU) +#define QSPI_CFG_CMD_MODE_ONE_LINE (1LU << 8LU) +#define QSPI_CFG_CMD_MODE_TWO_LINES (2LU << 8LU) +#define QSPI_CFG_CMD_MODE_FOUR_LINES (3LU << 8LU) +#define QSPI_CFG_ADDR_MODE_MASK (3LU << 10LU) +#define QSPI_CFG_ADDR_MODE_NONE (0LU << 10LU) +#define QSPI_CFG_ADDR_MODE_ONE_LINE (1LU << 10LU) +#define QSPI_CFG_ADDR_MODE_TWO_LINES (2LU << 10LU) +#define QSPI_CFG_ADDR_MODE_FOUR_LINES (3LU << 10LU) +#define QSPI_CFG_ADDR_SIZE_MASK (3LU << 12LU) +#define QSPI_CFG_ADDR_SIZE_8 (0LU << 12LU) +#define QSPI_CFG_ADDR_SIZE_16 (1LU << 12LU) +#define QSPI_CFG_ADDR_SIZE_24 (2LU << 12LU) +#define QSPI_CFG_ADDR_SIZE_32 (3LU << 12LU) +#define QSPI_CFG_ALT_MODE_MASK (3LU << 14LU) +#define QSPI_CFG_ALT_MODE_NONE (0LU << 14LU) +#define QSPI_CFG_ALT_MODE_ONE_LINE (1LU << 14LU) +#define QSPI_CFG_ALT_MODE_TWO_LINES (2LU << 14LU) +#define QSPI_CFG_ALT_MODE_FOUR_LINES (3LU << 14LU) +#define QSPI_CFG_ALT_SIZE_MASK (3LU << 16LU) +#define QSPI_CFG_ALT_SIZE_8 (0LU << 16LU) + +#define QSPI_CFG_ALT_SIZE_16 (1LU << 16LU) +#define QSPI_CFG_ALT_SIZE_24 (2LU << 16LU) +#define QSPI_CFG_ALT_SIZE_32 (3LU << 16LU) +#define QSPI_CFG_DUMMY_CYCLES_MASK (0x1FLU << 18LU) +#define QSPI_CFG_DUMMY_CYCLES(n) ((n) << 18LU) +#define QSPI_CFG_DATA_MODE_MASK (3LU << 24LU) +#define QSPI_CFG_DATA_MODE_NONE (0LU << 24LU) +#define QSPI_CFG_DATA_MODE_ONE_LINE (1LU << 24LU) +#define QSPI_CFG_DATA_MODE_TWO_LINES (2LU << 24LU) +#define QSPI_CFG_DATA_MODE_FOUR_LINES (3LU << 24LU) +#define QSPI_CFG_SIOO (1LU << 28LU) +#define QSPI_CFG_DDRM (1LU << 31LU) /** @} */ /*===========================================================================*/ -- cgit v1.2.3