From 29309f101a4828842c377ff11a3a59908aab05f2 Mon Sep 17 00:00:00 2001 From: edolomb Date: Thu, 17 Jan 2019 15:19:20 +0000 Subject: Updated SAMA drivers (still incomplete) git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12543 110e8d01-0319-4d1e-a829-52ad28d1bb01 --- os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S | 42 ++++++++++++++++++++++ .../ARMCAx-TZ/compilers/GCC/ld/SAMA5D2ddr.ld | 37 +++++++++++++++++-- os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c | 25 ++++++++++--- os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.h | 2 +- .../startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h | 2 ++ 5 files changed, 100 insertions(+), 8 deletions(-) (limited to 'os/common/startup/ARMCAx-TZ') diff --git a/os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S b/os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S index 4810ea0f6..016e23c58 100644 --- a/os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S +++ b/os/common/startup/ARMCAx-TZ/compilers/GCC/crt0.S @@ -22,6 +22,20 @@ * @{ */ +/** + * @brief Constructors invocation switch. + */ +#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__) +#define CRT0_CALL_CONSTRUCTORS TRUE +#endif + +/** + * @brief Destructors invocation switch. + */ +#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__) +#define CRT0_CALL_DESTRUCTORS TRUE +#endif + #if !defined(__DOXYGEN__) .set MODE_USR, 0x10 @@ -117,10 +131,38 @@ bssloop: */ bl __core_init bl __late_init +#if 0 /* Constructors initialized after halInit() */ +#if CRT0_CALL_CONSTRUCTORS == TRUE + /* Constructors invocation.*/ + ldr r4, =__init_array_start + ldr r5, =__init_array_end +initloop: + cmp r4, r5 + bge endinitloop + ldr r1, [r4], #4 + blx r1 + b initloop +endinitloop: +#endif /* CRT0_CALL_CONSTRUCTORS */ +#endif /* if 0 */ /* * Main program invocation. */ bl main + +#if CRT0_CALL_DESTRUCTORS == TRUE + /* Destructors invocation.*/ + ldr r4, =__fini_array_start + ldr r5, =__fini_array_end +finiloop: + cmp r4, r5 + bge endfiniloop + ldr r1, [r4], #4 + blx r1 + b finiloop +endfiniloop: +#endif + b __default_exit #endif /* !defined(__DOXYGEN__) */ diff --git a/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/SAMA5D2ddr.ld b/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/SAMA5D2ddr.ld index 225f64d74..cb016edc0 100644 --- a/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/SAMA5D2ddr.ld +++ b/os/common/startup/ARMCAx-TZ/compilers/GCC/ld/SAMA5D2ddr.ld @@ -20,9 +20,9 @@ MEMORY { flash : org = 0x27000000, len = 1M - ram0 : org = 0x27100000, len = 15M - ram1 : org = 0x00000000, len = 0 - ram2 : org = 0x00000000, len = 0 + ram0 : org = 0x27100000, len = 13M + ram1 : org = 0x27E00000, len = 1M + ram2 : org = 0x27F00000, len = 1M ram3 : org = 0x00000000, len = 0 ram4 : org = 0x00000000, len = 0 ram5 : org = 0x00000000, len = 0 @@ -40,6 +40,37 @@ REGION_ALIAS("DATA_RAM", ram0); /* RAM region to be used for BSS segment.*/ REGION_ALIAS("BSS_RAM", ram0); +/* RAM region to be used for lcd frame buffer. */ +REGION_ALIAS("FB_RAM", ram1); + +/* RAM region to be used for no cache area. */ +REGION_ALIAS("NO_CACHE", ram2); + +SECTIONS +{ + /* Special section for frame buffer area.*/ + .fbram (NOLOAD) : ALIGN(4) + { + __fbram_base__ = .; + *(.fbram) + *(.fbram.*) + *(.bss.__fbram_*) + . = ALIGN(4); + __fbram_end__ = .; + } > FB_RAM + + /* Special section for no cache area.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NO_CACHE +} + INCLUDE rules.ld ENTRY(Boot_Handler); diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c index ab063dcfc..b4af836c0 100644 --- a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c +++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.c @@ -48,9 +48,17 @@ #define SAMA_L2CC_ENABLE 0 #endif +#if (SAMA_L2CC_ASSUME_ENABLED && SAMA_L2CC_ENABLE) +#error "These macros are mutually exclusive" +#endif + /*===========================================================================*/ /* Module local definitions. */ /*===========================================================================*/ +/* + * @brief No cacheable memory start address. + */ +#define NO_CACHE_MEMORY_START_ADDR ((uint8_t *) 0x27F00000) /*===========================================================================*/ /* Module exported variables. */ @@ -77,7 +85,7 @@ * +---------+--+-+--+-+-----+--------+-------+-+------+--+-+-+-+---+ * | section |NS|0|nG|S|AP[2]|TEX[2:0]|AP[1:0]| |domain|XN|C|B|1|PXN| * +---------+--+-+--+-+-----+--------+-------+-+------+--+-+-+-+---+ - * | |0 |0|0 |1|0 |111 |11 |0|0000 |0 |1|1|1|0 | == normal, cacheable + * | |0 |0|0 |0|0 |111 |11 |0|0000 |0 |1|1|1|0 | == normal, cacheable, write back, no write allocate * | |0 |0|0 |1|0 |100 |11 |0|0000 |0 |0|0|1|0 | == normal, no-cacheable * | |0 |0|0 |1|0 |000 |11 |0|0000 |0 |0|1|1|0 | == device * | |0 |0|0 |1|0 |000 |11 |0|0000 |0 |0|0|1|0 | == strongly-ordered @@ -164,7 +172,7 @@ void __core_init(void) { TTE_SECT_MEM_CACHEABLE | TTE_SECT_RW_ACCESS | TTE_SECT_DOM(0x00) | - TTE_SECT_S | TTE_TYPE_SECT; + TTE_TYPE_SECT; /* * UDPHS RAM region * @@ -264,7 +272,7 @@ void __core_init(void) { TTE_SECT_MEM_CACHEABLE | TTE_SECT_RW_ACCESS | TTE_SECT_DOM(0x00) | - TTE_SECT_S | TTE_TYPE_SECT; + TTE_TYPE_SECT; /* * DDR AESB regions * @@ -275,7 +283,7 @@ void __core_init(void) { TTE_SECT_MEM_CACHEABLE | TTE_SECT_RW_ACCESS | TTE_SECT_DOM(0x00) | - TTE_SECT_S | TTE_TYPE_SECT; + TTE_TYPE_SECT; /* * EBI 1, 2 and 3 regions * @@ -360,6 +368,9 @@ void __core_init(void) { TTE_SECT_EXE_NEVER | TTE_SECT_S | TTE_TYPE_SECT; + /* Make a NO CACHE AREA */ + MMU_MemorySection((mmuTable + ((uint32_t)NO_CACHE_MEMORY_START_ADDR >> 20)), NORMAL, NON_CACHEABLE, NON_CACHEABLE); + /* Invalidate TLB and L1 I cache Enable caches and MMU.*/ MMU_InvalidateTLB(); @@ -395,11 +406,17 @@ void __core_init(void) { /* Invalidate and enable L2 cache.*/ L2C_InvAllByWay(); + L2C_310->AUX_CNT = L2CC_ACR_DPEN | L2CC_ACR_IPEN; + + /* Prefetch control register. Double linefeed, instr and data enabled.*/ + *((uint32_t *)((char *)L2C_310+0x0F60)) = 0x75800001; L2C_Enable(); __DSB(); __ISB(); } #endif + + #endif } diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.h index 95ef15854..4392fe222 100644 --- a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.h +++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/mmu.h @@ -31,7 +31,6 @@ /*===========================================================================*/ /* Module constants. */ /*===========================================================================*/ - #define DCISW_INVALIDATE 0 #define DCISW_CLEAN 1 #define DCISW_CLEAN_AND_INV 2 @@ -44,6 +43,7 @@ /* Derived constants and error checks. */ /*===========================================================================*/ + /*===========================================================================*/ /* Module data structures and types. */ /*===========================================================================*/ diff --git a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h index 6aad3e035..1d711bf0b 100644 --- a/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h +++ b/os/common/startup/ARMCAx-TZ/devices/SAMA5D2/sama5d2x.h @@ -64,8 +64,10 @@ /**@} */ +#ifndef GBC_DISABLE_AES_REFERENCE /* TODO: to delete */ #define Aes wc_Aes +#endif /** * @brief SAMA5D2 Family -- cgit v1.2.3