From ffdbef26d6bc06b135c43d683403c9d56e53da07 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 26 May 2014 14:43:02 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6964 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/common/ports/ARM/compilers/GCC/crt0.s | 254 +++++++++++++------------ os/common/ports/ARM/compilers/GCC/vectors.s | 101 ++++++++++ os/common/ports/ARMCMx/compilers/GCC/vectors.c | 2 +- 3 files changed, 230 insertions(+), 127 deletions(-) create mode 100644 os/common/ports/ARM/compilers/GCC/vectors.s (limited to 'os/common/ports') diff --git a/os/common/ports/ARM/compilers/GCC/crt0.s b/os/common/ports/ARM/compilers/GCC/crt0.s index 4e7106fb5..8eae3452d 100644 --- a/os/common/ports/ARM/compilers/GCC/crt0.s +++ b/os/common/ports/ARM/compilers/GCC/crt0.s @@ -1,6 +1,6 @@ /* ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. + 2011,2012,2013 Giovanni Di Sirio. This file is part of ChibiOS/RT. @@ -28,133 +28,135 @@ #if !defined(__DOXYGEN__) - .set MODE_USR, 0x10 - .set MODE_FIQ, 0x11 - .set MODE_IRQ, 0x12 - .set MODE_SVC, 0x13 - .set MODE_ABT, 0x17 - .set MODE_UND, 0x1B - .set MODE_SYS, 0x1F + .set MODE_USR, 0x10 + .set MODE_FIQ, 0x11 + .set MODE_IRQ, 0x12 + .set MODE_SVC, 0x13 + .set MODE_ABT, 0x17 + .set MODE_UND, 0x1B + .set MODE_SYS, 0x1F - .set I_BIT, 0x80 - .set F_BIT, 0x40 + .set I_BIT, 0x80 + .set F_BIT, 0x40 - .text - .code 32 - .balign 4 + .text + .code 32 + .balign 4 /* * Reset handler. */ - .global Reset_Handler + .global Reset_Handler Reset_Handler: - /* - * Stack pointers initialization. - */ - ldr r0, =___stacks_end__ - /* Undefined */ - msr CPSR_c, #MODE_UND | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__und_stack_size__ - sub r0, r0, r1 - /* Abort */ - msr CPSR_c, #MODE_ABT | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__abt_stack_size__ - sub r0, r0, r1 - /* FIQ */ - msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__fiq_stack_size__ - sub r0, r0, r1 - /* IRQ */ - msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__irq_stack_size__ - sub r0, r0, r1 - /* Supervisor */ - msr CPSR_c, #MODE_SVC | I_BIT | F_BIT - mov sp, r0 - ldr r1, =__svc_stack_size__ - sub r0, r0, r1 - /* System */ - msr CPSR_c, #MODE_SYS | I_BIT | F_BIT - mov sp, r0 -// ldr r1, =__sys_stack_size__ -// sub r0, r0, r1 - /* - * Early initialization. - */ -#ifndef THUMB_NO_INTERWORKING - bl __early_init -#else - add r0, pc, #1 - bx r0 - .code 16 - bl __early_init - mov r0, pc - bx r0 - .code 32 -#endif - /* - * Data initialization. - * NOTE: It assumes that the DATA size is a multiple of 4. - */ - ldr r1, =_textdata - ldr r2, =_data - ldr r3, =_edata + /* + * Stack pointers initialization. + */ + ldr r0, =___stacks_end__ + /* Undefined */ + msr CPSR_c, #MODE_UND | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__und_stack_size__ + sub r0, r0, r1 + /* Abort */ + msr CPSR_c, #MODE_ABT | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__abt_stack_size__ + sub r0, r0, r1 + /* FIQ */ + msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__fiq_stack_size__ + sub r0, r0, r1 + /* IRQ */ + msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__irq_stack_size__ + sub r0, r0, r1 + /* Supervisor */ + msr CPSR_c, #MODE_SVC | I_BIT | F_BIT + mov sp, r0 + ldr r1, =__svc_stack_size__ + sub r0, r0, r1 + /* System */ + msr CPSR_c, #MODE_SYS | I_BIT | F_BIT + mov sp, r0 +// ldr r1, =__sys_stack_size__ +// sub r0, r0, r1 + /* + * Early initialization. + */ +#if !defined(THUMB_NO_INTERWORKING) + bl __early_init +#else /* defined(THUMB_NO_INTERWORKING) */ + add r0, pc, #1 + bx r0 + .code 16 + bl __early_init + mov r0, pc + bx r0 + .code 32 +#endif /* defined(THUMB_NO_INTERWORKING) */ + + /* + * Data initialization. + * NOTE: It assumes that the DATA size is a multiple of 4. + */ + ldr r1, =_textdata + ldr r2, =_data + ldr r3, =_edata dataloop: - cmp r2, r3 - ldrlo r0, [r1], #4 - strlo r0, [r2], #4 - blo dataloop - /* - * BSS initialization. - * NOTE: It assumes that the BSS size is a multiple of 4. - */ - mov r0, #0 - ldr r1, =_bss_start - ldr r2, =_bss_end + cmp r2, r3 + ldrlo r0, [r1], #4 + strlo r0, [r2], #4 + blo dataloop + /* + * BSS initialization. + * NOTE: It assumes that the BSS size is a multiple of 4. + */ + mov r0, #0 + ldr r1, =_bss_start + ldr r2, =_bss_end bssloop: - cmp r1, r2 - strlo r0, [r1], #4 - blo bssloop - /* - * Late initialization. - */ -#ifndef THUMB_NO_INTERWORKING - bl __late_init -#else - add r0, pc, #1 - bx r0 - .code 16 - bl __late_init - mov r0, pc - bx r0 - .code 32 -#endif - /* - * Main program invocation. - */ -#ifdef THUMB_NO_INTERWORKING - add r0, pc, #1 - bx r0 - .code 16 - bl main - ldr r1, =_main_exit_handler - bx r1 - .code 32 -#else - bl main - b _main_exit_handler -#endif + cmp r1, r2 + strlo r0, [r1], #4 + blo bssloop + /* + * Late initialization. + */ +#if !defined(THUMB_NO_INTERWORKING) + bl __late_init +#else /* defined(THUMB_NO_INTERWORKING) */ + add r0, pc, #1 + bx r0 + .code 16 + bl __late_init + mov r0, pc + bx r0 + .code 32 +#endif /* defined(THUMB_NO_INTERWORKING) */ + + /* + * Main program invocation. + */ +#if defined(THUMB_NO_INTERWORKING) + add r0, pc, #1 + bx r0 + .code 16 + bl main + ldr r1, =_main_exit_handler + bx r1 + .code 32 +#else /* !defined(THUMB_NO_INTERWORKING) + bl main + b _main_exit_handler +#endif /* !defined(THUMB_NO_INTERWORKING) */ /* * Default main function exit handler. */ - .weak _main_exit_handler + .weak _main_exit_handler _main_exit_handler: -.loop: b .loop +.loop: b .loop /* * Default early initialization code. It is declared weak in order to be @@ -162,14 +164,14 @@ _main_exit_handler: * Early initialization is performed just before reset before BSS and DATA * segments initialization. */ -#ifdef THUMB_NO_INTERWORKING - .thumb_func - .code 16 +#if defined(THUMB_NO_INTERWORKING) + .thumb_func + .code 16 #endif - .weak __early_init + .weak __early_init __early_init: - bx lr - .code 32 + bx lr + .code 32 #endif /* @@ -178,14 +180,14 @@ __early_init: * Early initialization is performed just after reset before BSS and DATA * segments initialization. */ -#ifdef THUMB_NO_INTERWORKING - .thumb_func - .code 16 +#if defined(THUMB_NO_INTERWORKING) + .thumb_func + .code 16 #endif - .weak __late_init + .weak __late_init __late_init: - bx lr - .code 32 + bx lr + .code 32 #endif /** @} */ diff --git a/os/common/ports/ARM/compilers/GCC/vectors.s b/os/common/ports/ARM/compilers/GCC/vectors.s new file mode 100644 index 000000000..4ed076eb6 --- /dev/null +++ b/os/common/ports/ARM/compilers/GCC/vectors.s @@ -0,0 +1,101 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file ARM/compilers/GCC/vectors.s + * @brief Interrupt vectors for ARM devices. + * + * @defgroup ARM_VECTORS ARM Exception Vectors + * @{ + */ + +#if defined(__DOXYGEN__) +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * @note The default implementation is a weak symbol, the application + * can override the default implementation. + * + * @notapi + */ +void _unhandled_exception(void) {} +#endif + +#if !defined(__DOXYGEN__) + + .section vectors + .code 32 + .balign 4 + +/* + * System entry points. + */ +_start: + ldr pc, _reset + ldr pc, _undefined + ldr pc, _swi + ldr pc, _prefetch + ldr pc, _abort + nop + ldr pc, _irq + ldr pc, _fiq + +_reset: + .word ResetHandler +_undefined: + .word UndHandler +_swi: + .word SwiHandler +_prefetch: + .word PrefetchHandler +_abort: + .word AbortHandler +_fiq: + .word FiqHandler +_irq: + .word IrqHandler + +/* + * Default exceptions handlers. The handlers are declared weak in order to be + * replaced by the real handling code. Everything is defaulted to an infinite + * loop. + */ + .weak ResetHandler +ResetHandler: + .weak UndHandler +UndHandler: + .weak SwiHandler +SwiHandler: + .weak PrefetchHandler +PrefetchHandler: + .weak AbortHandler +AbortHandler: + .weak FiqHandler +FiqHandler: + .weak IrqHandler +IrqHandler: + .weak _unhandled_exception +_unhandled_exception: + b _unhandled_exception + +#endif + +/** @} */ diff --git a/os/common/ports/ARMCMx/compilers/GCC/vectors.c b/os/common/ports/ARMCMx/compilers/GCC/vectors.c index 252071854..b42591da2 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/vectors.c +++ b/os/common/ports/ARMCMx/compilers/GCC/vectors.c @@ -19,7 +19,7 @@ */ /** - * @file ARMCMx/GCC/vectors.c + * @file ARMCMx/compilers/GCC/vectors.c * @brief Interrupt vectors for Cortex-Mx devices. * * @defgroup ARMCMx_VECTORS Cortex-Mx Interrupt Vectors -- cgit v1.2.3