From 6274f1e25f189cf3e9792c96750261b7cdee8594 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 4 Sep 2015 12:15:41 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8278
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 .../ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld   | 11 +++-
 .../ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld     | 12 +++-
 .../ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld     | 68 ++++++++++++++++++++++
 3 files changed, 85 insertions(+), 6 deletions(-)
 create mode 100644 os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld

(limited to 'os/common/ports')

diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld
index 94668b13e..b7c90bd0e 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld
@@ -18,8 +18,13 @@
 */
 
 /*
- * ST32F746xG memory setup.
- * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ * ST32F746xG generic setup.
+ * 
+ * RAM0 - Data, Heap.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
  */
 MEMORY
 {
@@ -47,7 +52,7 @@ REGION_ALIAS("PROCESS_STACK_RAM", ram3);
 REGION_ALIAS("DATA_RAM", ram0);
 
 /* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram0);
+REGION_ALIAS("BSS_RAM", ram3);
 
 /* RAM region to be used for the default heap.*/
 REGION_ALIAS("HEAP_RAM", ram0);
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld
index 03d2e1478..d4fa6ca8a 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_ETH.ld
@@ -18,8 +18,14 @@
 */
 
 /*
- * ST32F746xG memory setup.
- * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0.
+ * ST32F746xG Ethernet setup.
+ * 
+ * RAM1 - Data, Heap.
+ * RAM2 - ETH.
+ * RAM3 - Main Stack, Process Stack, BSS, NOCACHE.
+ *
+ * Notes:
+ * BSS is placed in DTCM RAM in order to simplify DMA buffers management.
  */
 MEMORY
 {
@@ -46,7 +52,7 @@ REGION_ALIAS("PROCESS_STACK_RAM", ram3);
 REGION_ALIAS("DATA_RAM", ram1);
 
 /* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram1);
+REGION_ALIAS("BSS_RAM", ram3);
 
 /* RAM region to be used for the default heap.*/
 REGION_ALIAS("HEAP_RAM", ram1);
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld
new file mode 100644
index 000000000..21ba81fed
--- /dev/null
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_MAX.ld
@@ -0,0 +1,68 @@
+/*
+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
+
+    This file is part of ChibiOS.
+
+    ChibiOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * ST32F746xG maximum RAM setup.
+ * 
+ * RAM0 - Data, BSS, Heap.
+ * RAM3 - Main Stack, Process Stack, NOCACHE, ETH.
+ *
+ * Notes:
+ * BSS is placed in cached RAM, DMA buffers management is delegated to the
+ * application code. This setup maximizes the linear RAM available to BSS and
+ * Heap.
+ */
+MEMORY
+{
+    flash       : org = 0x08000000, len = 1M
+    flash_itcm  : org = 0x00200000, len = 1M
+    ram0        : org = 0x20010000, len = 256k    /* SRAM1 + SRAM2 */
+    ram1        : org = 0x20010000, len = 240k    /* SRAM1 */
+    ram2        : org = 0x2004C000, len = 16k     /* SRAM2 */
+    ram3        : org = 0x20000000, len = 64k     /* DTCM-RAM */
+    ram4        : org = 0x00000000, len = 16k     /* ITCM-RAM */
+    ram5        : org = 0x40024000, len = 4k      /* BCKP SRAM */
+    ram6        : org = 0x00000000, len = 0
+    ram7        : org = 0x00000000, len = 0
+}
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+   of all exceptions and interrupts*/
+REGION_ALIAS("MAIN_STACK_RAM", ram3);
+
+/* RAM region to be used for the process stack. This is the stack used by
+   the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram3);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* RAM region to be used for nocache segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for eth segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
+
+INCLUDE ld/rules_STM32F7xx.ld
-- 
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