From a3ce241a45b474eb0b5fffb86040ea6fa554bf1f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 26 Feb 2014 13:44:13 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6730 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld | 31 ++ os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld | 31 ++ os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld | 31 ++ os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld | 30 ++ os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld | 30 ++ os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld | 30 ++ os/common/ports/e200/compilers/GCC/rules_z3.ld | 160 ++++++++++ os/common/ports/e200/devices/SPC560BCxx/boot.h | 118 +++++++ os/common/ports/e200/devices/SPC560BCxx/boot.s | 214 +++++++++++++ .../ports/e200/devices/SPC560BCxx/ppcparams.h | 77 +++++ os/common/ports/e200/devices/SPC560Bxx/boot.h | 118 +++++++ os/common/ports/e200/devices/SPC560Bxx/boot.s | 214 +++++++++++++ os/common/ports/e200/devices/SPC560Bxx/ppcparams.h | 77 +++++ os/common/ports/e200/devices/SPC560Dxx/boot.h | 118 +++++++ os/common/ports/e200/devices/SPC560Dxx/boot.s | 214 +++++++++++++ os/common/ports/e200/devices/SPC560Dxx/ppcparams.h | 77 +++++ os/common/ports/e200/devices/SPC563Mxx/boot.h | 119 +++++++ os/common/ports/e200/devices/SPC563Mxx/boot.s | 188 +++++++++++ os/common/ports/e200/devices/SPC563Mxx/ppcparams.h | 77 +++++ os/common/ports/e200/devices/SPC564Axx/boot.h | 242 ++++++++++++++ os/common/ports/e200/devices/SPC564Axx/boot.s | 353 +++++++++++++++++++++ os/common/ports/e200/devices/SPC564Axx/ppcparams.h | 77 +++++ 22 files changed, 2626 insertions(+) create mode 100644 os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld create mode 100644 os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld create mode 100644 os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld create mode 100644 os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld create mode 100644 os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld create mode 100644 os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld create mode 100644 os/common/ports/e200/compilers/GCC/rules_z3.ld create mode 100644 os/common/ports/e200/devices/SPC560BCxx/boot.h create mode 100644 os/common/ports/e200/devices/SPC560BCxx/boot.s create mode 100644 os/common/ports/e200/devices/SPC560BCxx/ppcparams.h create mode 100644 os/common/ports/e200/devices/SPC560Bxx/boot.h create mode 100644 os/common/ports/e200/devices/SPC560Bxx/boot.s create mode 100644 os/common/ports/e200/devices/SPC560Bxx/ppcparams.h create mode 100644 os/common/ports/e200/devices/SPC560Dxx/boot.h create mode 100644 os/common/ports/e200/devices/SPC560Dxx/boot.s create mode 100644 os/common/ports/e200/devices/SPC560Dxx/ppcparams.h create mode 100644 os/common/ports/e200/devices/SPC563Mxx/boot.h create mode 100644 os/common/ports/e200/devices/SPC563Mxx/boot.s create mode 100644 os/common/ports/e200/devices/SPC563Mxx/ppcparams.h create mode 100644 os/common/ports/e200/devices/SPC564Axx/boot.h create mode 100644 os/common/ports/e200/devices/SPC564Axx/boot.s create mode 100644 os/common/ports/e200/devices/SPC564Axx/ppcparams.h (limited to 'os/common/ports/e200') diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld new file mode 100644 index 000000000..7f6bcc4aa --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC560B50.ld @@ -0,0 +1,31 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC560B50 memory setup. + */ +MEMORY +{ + flash : org = 0x00000000, len = 512k + dataflash : org = 0x00800000, len = 64k + ram : org = 0x40000000, len = 32k +} + +INCLUDE rules_z0.ld diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld new file mode 100644 index 000000000..37f5321f7 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC560B64.ld @@ -0,0 +1,31 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC560B64 memory setup. + */ +MEMORY +{ + flash : org = 0x00000000, len = 1536k + dataflash : org = 0x00800000, len = 64k + ram : org = 0x40000000, len = 96k +} + +INCLUDE rules_z0.ld diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld b/os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld new file mode 100644 index 000000000..b7895ad28 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC560D40.ld @@ -0,0 +1,31 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC560D40 memory setup. + */ +MEMORY +{ + flash : org = 0x00000000, len = 256k + dataflash : org = 0x00800000, len = 64k + ram : org = 0x40000000, len = 16k +} + +INCLUDE rules_z0.ld diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld b/os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld new file mode 100644 index 000000000..f662a2993 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC563M64.ld @@ -0,0 +1,30 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC563M64 memory setup. + */ +MEMORY +{ + flash : org = 0x00000000, len = 1536k + ram : org = 0x40000000, len = 94k +} + +INCLUDE rules_z3.ld diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld b/os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld new file mode 100644 index 000000000..3f8604c84 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC564A70.ld @@ -0,0 +1,30 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC563A70 memory setup. + */ +MEMORY +{ + flash : org = 0x00000000, len = 2M + ram : org = 0x40000000, len = 128k +} + +INCLUDE rules_z4.ld diff --git a/os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld b/os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld new file mode 100644 index 000000000..7923156c4 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/ld/SPC564A80.ld @@ -0,0 +1,30 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * SPC563A80 memory setup. + */ +MEMORY +{ + flash : org = 0x00000000, len = 4M + ram : org = 0x40000000, len = 192k +} + +INCLUDE rules_z4.ld diff --git a/os/common/ports/e200/compilers/GCC/rules_z3.ld b/os/common/ports/e200/compilers/GCC/rules_z3.ld new file mode 100644 index 000000000..68a1ad724 --- /dev/null +++ b/os/common/ports/e200/compilers/GCC/rules_z3.ld @@ -0,0 +1,160 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +__ram_size__ = LENGTH(ram); +__ram_start__ = ORIGIN(ram); +__ram_end__ = ORIGIN(ram) + LENGTH(ram); + +ENTRY(_reset_address) + +SECTIONS +{ + . = ORIGIN(flash); + .boot0 : ALIGN(16) SUBALIGN(16) + { + __ivpr_base__ = .; + KEEP(*(.boot)) + } > flash + + .boot1 : ALIGN(16) SUBALIGN(16) + { + KEEP(*(.handlers)) + KEEP(*(.crt0)) + /* The vectors table requires a 2kB alignment.*/ + . = ALIGN(0x800); + KEEP(*(.vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text_vle : ALIGN(16) SUBALIGN(16) + { + *(.text_vle) + *(.text_vle.*) + *(.gnu.linkonce.t_vle.*) + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } > flash + + .rodata : ALIGN(16) SUBALIGN(16) + { + *(.glue_7t) + *(.glue_7) + *(.gcc*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + } > flash + + .sdata2 : ALIGN(16) SUBALIGN(16) + { + __sdata2_start__ = . + 0x8000; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .romdata : ALIGN(16) SUBALIGN(16) + { + __romdata_start__ = .; + } > flash + + .stacks : ALIGN(16) SUBALIGN(16) + { + . = ALIGN(8); + __irq_stack_base__ = .; + . += __irq_stack_size__; + . = ALIGN(8); + __irq_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : AT(__romdata_start__) + { + . = ALIGN(4); + __data_start__ = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + __sdata_start__ = . + 0x8000; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __data_end__ = .; + } > ram + + .sbss : + { + __bss_start__ = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } > ram + + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end__ = .; + } > ram + + __heap_base__ = __bss_end__; + __heap_end__ = __ram_end__; +} diff --git a/os/common/ports/e200/devices/SPC560BCxx/boot.h b/os/common/ports/e200/devices/SPC560BCxx/boot.h new file mode 100644 index 000000000..51b2607ae --- /dev/null +++ b/os/common/ports/e200/devices/SPC560BCxx/boot.h @@ -0,0 +1,118 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file boot.h + * @brief Boot parameters for the SPC560BCxx. + * @{ + */ + +#ifndef _BOOT_H_ +#define _BOOT_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_ME 0x00001000 +#define MSR_DE 0x00000200 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/* + * BUCSR default settings. + */ +#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) +#endif + +/* + * MSR default settings. + */ +#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) +#endif + +/* + * Boot default settings. + */ +#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) +#define BOOT_PERFORM_CORE_INIT 1 +#endif + +/* + * VLE mode default settings. + */ +#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) +#define BOOT_USE_VLE 1 +#endif + +/* + * RAM relocation flag. + */ +#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) +#define BOOT_RELOCATE_IN_RAM 0 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* _BOOT_H_ */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC560BCxx/boot.s b/os/common/ports/e200/devices/SPC560BCxx/boot.s new file mode 100644 index 000000000..7c8457161 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560BCxx/boot.s @@ -0,0 +1,214 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560BCxx/boot.s + * @brief SPC560BCxx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + + .long 0x015A0000 + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_coreinit: + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + blr + + .section .ivors, "ax" + + .globl IVORS +IVORS: +IVOR0: b IVOR0 + .align 4 +IVOR1: b _IVOR1 + .align 4 +IVOR2: b _IVOR2 + .align 4 +IVOR3: b _IVOR3 + .align 4 +IVOR4: b _IVOR4 + .align 4 +IVOR5: b _IVOR5 + .align 4 +IVOR6: b _IVOR6 + .align 4 +IVOR7: b _IVOR7 + .align 4 +IVOR8: b _IVOR8 + .align 4 +IVOR9: b _IVOR9 + .align 4 +IVOR10: b _IVOR10 + .align 4 +IVOR11: b _IVOR11 + .align 4 +IVOR12: b _IVOR12 + .align 4 +IVOR13: b _IVOR13 + .align 4 +IVOR14: b _IVOR14 + .align 4 +IVOR15: b _IVOR15 + + .section .handlers, "ax" + + /* + * Default IVOR handlers. + */ + .align 2 + .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 + .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 + .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 + .weak _unhandled_exception +_IVOR0: +_IVOR1: +_IVOR2: +_IVOR3: +_IVOR5: +_IVOR6: +_IVOR7: +_IVOR8: +_IVOR9: +_IVOR11: +_IVOR12: +_IVOR13: +_IVOR14: +_IVOR15: +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC560BCxx/ppcparams.h b/os/common/ports/e200/devices/SPC560BCxx/ppcparams.h new file mode 100644 index 000000000..5b29a80c8 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560BCxx/ppcparams.h @@ -0,0 +1,77 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560BCxx/ppcparams.h + * @brief PowerPC parameters for the SPC560BCxx. + * + * @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC560BCxx platform. + * @{ + */ + +#ifndef _PPCPARAMS_H_ +#define _PPCPARAMS_H_ + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z0 + +/** + * @brief Number of writable bits in IVPR register. + */ +#define PPC_IVPR_BITS 20 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS FALSE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE FALSE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER FALSE + +/** + * @brief Number of interrupt sources. + */ +#define PPC_NUM_VECTORS 217 + +#endif /* _PPCPARAMS_H_ */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC560Bxx/boot.h b/os/common/ports/e200/devices/SPC560Bxx/boot.h new file mode 100644 index 000000000..7e60b8f78 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Bxx/boot.h @@ -0,0 +1,118 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file boot.h + * @brief Boot parameters for the SPC560Bxx. + * @{ + */ + +#ifndef _BOOT_H_ +#define _BOOT_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_ME 0x00001000 +#define MSR_DE 0x00000200 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/* + * BUCSR default settings. + */ +#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) +#endif + +/* + * MSR default settings. + */ +#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) +#endif + +/* + * Boot default settings. + */ +#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) +#define BOOT_PERFORM_CORE_INIT 1 +#endif + +/* + * VLE mode default settings. + */ +#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) +#define BOOT_USE_VLE 1 +#endif + +/* + * RAM relocation flag. + */ +#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) +#define BOOT_RELOCATE_IN_RAM 0 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* _BOOT_H_ */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC560Bxx/boot.s b/os/common/ports/e200/devices/SPC560Bxx/boot.s new file mode 100644 index 000000000..86600aac2 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Bxx/boot.s @@ -0,0 +1,214 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Bxx/boot.s + * @brief SPC560Bxx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + + .long 0x015A0000 + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_coreinit: + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + blr + + .section .ivors, "ax" + + .globl IVORS +IVORS: +IVOR0: b IVOR0 + .align 4 +IVOR1: b _IVOR1 + .align 4 +IVOR2: b _IVOR2 + .align 4 +IVOR3: b _IVOR3 + .align 4 +IVOR4: b _IVOR4 + .align 4 +IVOR5: b _IVOR5 + .align 4 +IVOR6: b _IVOR6 + .align 4 +IVOR7: b _IVOR7 + .align 4 +IVOR8: b _IVOR8 + .align 4 +IVOR9: b _IVOR9 + .align 4 +IVOR10: b _IVOR10 + .align 4 +IVOR11: b _IVOR11 + .align 4 +IVOR12: b _IVOR12 + .align 4 +IVOR13: b _IVOR13 + .align 4 +IVOR14: b _IVOR14 + .align 4 +IVOR15: b _IVOR15 + + .section .handlers, "ax" + + /* + * Default IVOR handlers. + */ + .align 2 + .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 + .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 + .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 + .weak _unhandled_exception +_IVOR0: +_IVOR1: +_IVOR2: +_IVOR3: +_IVOR5: +_IVOR6: +_IVOR7: +_IVOR8: +_IVOR9: +_IVOR11: +_IVOR12: +_IVOR13: +_IVOR14: +_IVOR15: +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC560Bxx/ppcparams.h b/os/common/ports/e200/devices/SPC560Bxx/ppcparams.h new file mode 100644 index 000000000..451971b61 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Bxx/ppcparams.h @@ -0,0 +1,77 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560Bxx/ppcparams.h + * @brief PowerPC parameters for the SPC560Bxx. + * + * @defgroup PPC_SPC560Bxx SPC560Bxx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC560Bxx platform. + * @{ + */ + +#ifndef _PPCPARAMS_H_ +#define _PPCPARAMS_H_ + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z0 + +/** + * @brief Number of writable bits in IVPR register. + */ +#define PPC_IVPR_BITS 20 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS FALSE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE FALSE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER FALSE + +/** + * @brief Number of interrupt sources. + */ +#define PPC_NUM_VECTORS 234 + +#endif /* _PPCPARAMS_H_ */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC560Dxx/boot.h b/os/common/ports/e200/devices/SPC560Dxx/boot.h new file mode 100644 index 000000000..bb51eebda --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Dxx/boot.h @@ -0,0 +1,118 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file boot.h + * @brief Boot parameters for the SPC560Dxx. + * @{ + */ + +#ifndef _BOOT_H_ +#define _BOOT_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_ME 0x00001000 +#define MSR_DE 0x00000200 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/* + * BUCSR default settings. + */ +#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) +#endif + +/* + * MSR default settings. + */ +#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) +#endif + +/* + * Boot default settings. + */ +#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) +#define BOOT_PERFORM_CORE_INIT 1 +#endif + +/* + * VLE mode default settings. + */ +#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) +#define BOOT_USE_VLE 1 +#endif + +/* + * RAM relocation flag. + */ +#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) +#define BOOT_RELOCATE_IN_RAM 0 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* _BOOT_H_ */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC560Dxx/boot.s b/os/common/ports/e200/devices/SPC560Dxx/boot.s new file mode 100644 index 000000000..520cdf41a --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Dxx/boot.s @@ -0,0 +1,214 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC560Dxx/boot.s + * @brief SPC560Dxx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + + .long 0x015A0000 + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_coreinit: + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + blr + + .section .ivors, "ax" + + .globl IVORS +IVORS: +IVOR0: b IVOR0 + .align 4 +IVOR1: b _IVOR1 + .align 4 +IVOR2: b _IVOR2 + .align 4 +IVOR3: b _IVOR3 + .align 4 +IVOR4: b _IVOR4 + .align 4 +IVOR5: b _IVOR5 + .align 4 +IVOR6: b _IVOR6 + .align 4 +IVOR7: b _IVOR7 + .align 4 +IVOR8: b _IVOR8 + .align 4 +IVOR9: b _IVOR9 + .align 4 +IVOR10: b _IVOR10 + .align 4 +IVOR11: b _IVOR11 + .align 4 +IVOR12: b _IVOR12 + .align 4 +IVOR13: b _IVOR13 + .align 4 +IVOR14: b _IVOR14 + .align 4 +IVOR15: b _IVOR15 + + .section .handlers, "ax" + + /* + * Default IVOR handlers. + */ + .align 2 + .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 + .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 + .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 + .weak _unhandled_exception +_IVOR0: +_IVOR1: +_IVOR2: +_IVOR3: +_IVOR5: +_IVOR6: +_IVOR7: +_IVOR8: +_IVOR9: +_IVOR11: +_IVOR12: +_IVOR13: +_IVOR14: +_IVOR15: +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC560Dxx/ppcparams.h b/os/common/ports/e200/devices/SPC560Dxx/ppcparams.h new file mode 100644 index 000000000..51f6824b7 --- /dev/null +++ b/os/common/ports/e200/devices/SPC560Dxx/ppcparams.h @@ -0,0 +1,77 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC560Dxx/ppcparams.h + * @brief PowerPC parameters for the SPC560Dxx. + * + * @defgroup PPC_SPC560Dxx SPC560Dxx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC560Dxx platform. + * @{ + */ + +#ifndef _PPCPARAMS_H_ +#define _PPCPARAMS_H_ + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z0 + +/** + * @brief Number of writable bits in IVPR register. + */ +#define PPC_IVPR_BITS 20 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS FALSE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE FALSE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER FALSE + +/** + * @brief Number of interrupt sources. + */ +#define PPC_NUM_VECTORS 155 + +#endif /* _PPCPARAMS_H_ */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC563Mxx/boot.h b/os/common/ports/e200/devices/SPC563Mxx/boot.h new file mode 100644 index 000000000..52bee9f45 --- /dev/null +++ b/os/common/ports/e200/devices/SPC563Mxx/boot.h @@ -0,0 +1,119 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file boot.h + * @brief Boot parameters for the SPC563Mxx. + * @{ + */ + +#ifndef _BOOT_H_ +#define _BOOT_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_UCLE 0x04000000 +#define MSR_SPE 0x02000000 +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_FP 0x00002000 +#define MSR_ME 0x00001000 +#define MSR_FE0 0x00000800 +#define MSR_DE 0x00000200 +#define MSR_FE1 0x00000100 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/* + * BUCSR default settings. + */ +#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) +#endif + +/* + * MSR default settings. + */ +#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) +#endif + +/* + * Boot default settings. + */ +#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) +#define BOOT_PERFORM_CORE_INIT 1 +#endif + +/* + * VLE mode default settings. + */ +#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) +#define BOOT_USE_VLE 1 +#endif + +/* + * RAM relocation flag. + */ +#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) +#define BOOT_RELOCATE_IN_RAM 0 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* _BOOT_H_ */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC563Mxx/boot.s b/os/common/ports/e200/devices/SPC563Mxx/boot.s new file mode 100644 index 000000000..7b9dc0e10 --- /dev/null +++ b/os/common/ports/e200/devices/SPC563Mxx/boot.s @@ -0,0 +1,188 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC563Mxx/boot.s + * @brief SPC563Mxx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + +#if BOOT_USE_VLE + .long 0x015A0000 +#else + .long 0x005A0000 +#endif + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_coreinit: + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + /* IVORs initialization.*/ + lis %r3, _unhandled_exception@h + ori %r3, %r3, _unhandled_exception@l + + mtspr 400, %r3 /* IVOR0-15 */ + mtspr 401, %r3 + mtspr 402, %r3 + mtspr 403, %r3 + mtspr 404, %r3 + mtspr 405, %r3 + mtspr 406, %r3 + mtspr 407, %r3 + mtspr 408, %r3 + mtspr 409, %r3 + mtspr 410, %r3 + mtspr 411, %r3 + mtspr 412, %r3 + mtspr 413, %r3 + mtspr 414, %r3 + mtspr 415, %r3 + mtspr 528, %r3 /* IVOR32-34 */ + mtspr 529, %r3 + mtspr 530, %r3 + + blr + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _unhandled_exception + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC563Mxx/ppcparams.h b/os/common/ports/e200/devices/SPC563Mxx/ppcparams.h new file mode 100644 index 000000000..29bc22eb7 --- /dev/null +++ b/os/common/ports/e200/devices/SPC563Mxx/ppcparams.h @@ -0,0 +1,77 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC563Mxx/ppcparams.h + * @brief PowerPC parameters for the SPC563Mxx. + * + * @defgroup PPC_SPC563Mxx SPC563Mxx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC563Mxx platform. + * @{ + */ + +#ifndef _PPCPARAMS_H_ +#define _PPCPARAMS_H_ + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z3 + +/** + * @brief Number of writable bits in IVPR register. + */ +#define PPC_IVPR_BITS 16 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS TRUE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE TRUE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER TRUE + +/** + * @brief Number of interrupt sources. + */ +#define PPC_NUM_VECTORS 360 + +#endif /* _PPCPARAMS_H_ */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC564Axx/boot.h b/os/common/ports/e200/devices/SPC564Axx/boot.h new file mode 100644 index 000000000..7b105153a --- /dev/null +++ b/os/common/ports/e200/devices/SPC564Axx/boot.h @@ -0,0 +1,242 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file boot.h + * @brief Boot parameters for the SPC564Axx. + * @{ + */ + +#ifndef _BOOT_H_ +#define _BOOT_H_ + +/*===========================================================================*/ +/* Module constants. */ +/*===========================================================================*/ + +/** + * @name MASx registers definitions + * @{ + */ +#define MAS0_TBLMAS_TBL 0x10000000 +#define MAS0_ESEL_MASK 0x000F0000 +#define MAS0_ESEL(n) ((n) << 16) + +#define MAS1_VALID 0x80000000 +#define MAS1_IPROT 0x40000000 +#define MAS1_TID_MASK 0x00FF0000 +#define MAS1_TS 0x00001000 +#define MAS1_TSISE_MASK 0x00000F80 +#define MAS1_TSISE_1K 0x00000000 +#define MAS1_TSISE_2K 0x00000080 +#define MAS1_TSISE_4K 0x00000100 +#define MAS1_TSISE_8K 0x00000180 +#define MAS1_TSISE_16K 0x00000200 +#define MAS1_TSISE_32K 0x00000280 +#define MAS1_TSISE_64K 0x00000300 +#define MAS1_TSISE_128K 0x00000380 +#define MAS1_TSISE_256K 0x00000400 +#define MAS1_TSISE_512K 0x00000480 +#define MAS1_TSISE_1M 0x00000500 +#define MAS1_TSISE_2M 0x00000580 +#define MAS1_TSISE_4M 0x00000600 +#define MAS1_TSISE_8M 0x00000680 +#define MAS1_TSISE_16M 0x00000700 +#define MAS1_TSISE_32M 0x00000780 +#define MAS1_TSISE_64M 0x00000800 +#define MAS1_TSISE_128M 0x00000880 +#define MAS1_TSISE_256M 0x00000900 +#define MAS1_TSISE_512M 0x00000980 +#define MAS1_TSISE_1G 0x00000A00 +#define MAS1_TSISE_2G 0x00000A80 +#define MAS1_TSISE_4G 0x00000B00 + +#define MAS2_EPN_MASK 0xFFFFFC00 +#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK) +#define MAS2_EBOOK 0x00000000 +#define MAS2_VLE 0x00000020 +#define MAS2_W 0x00000010 +#define MAS2_I 0x00000008 +#define MAS2_M 0x00000004 +#define MAS2_G 0x00000002 +#define MAS2_E 0x00000001 + +#define MAS3_RPN_MASK 0xFFFFFC00 +#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK) +#define MAS3_U0 0x00000200 +#define MAS3_U1 0x00000100 +#define MAS3_U2 0x00000080 +#define MAS3_U3 0x00000040 +#define MAS3_UX 0x00000020 +#define MAS3_SX 0x00000010 +#define MAS3_UW 0x00000008 +#define MAS3_SW 0x00000004 +#define MAS3_UR 0x00000002 +#define MAS3_SR 0x00000001 +/** @} */ + +/** + * @name BUCSR registers definitions + * @{ + */ +#define BUCSR_BPEN 0x00000001 +#define BUCSR_BPRED_MASK 0x00000006 +#define BUCSR_BPRED_0 0x00000000 +#define BUCSR_BPRED_1 0x00000002 +#define BUCSR_BPRED_2 0x00000004 +#define BUCSR_BPRED_3 0x00000006 +#define BUCSR_BALLOC_MASK 0x00000030 +#define BUCSR_BALLOC_0 0x00000000 +#define BUCSR_BALLOC_1 0x00000010 +#define BUCSR_BALLOC_2 0x00000020 +#define BUCSR_BALLOC_3 0x00000030 +#define BUCSR_BALLOC_BFI 0x00000200 +/** @} */ + +/** + * @name LICSR1 registers definitions + * @{ + */ +#define LICSR1_ICE 0x00000001 +#define LICSR1_ICINV 0x00000002 +#define LICSR1_ICORG 0x00000010 +/** @} */ + +/** + * @name MSR register definitions + * @{ + */ +#define MSR_UCLE 0x04000000 +#define MSR_SPE 0x02000000 +#define MSR_WE 0x00040000 +#define MSR_CE 0x00020000 +#define MSR_EE 0x00008000 +#define MSR_PR 0x00004000 +#define MSR_FP 0x00002000 +#define MSR_ME 0x00001000 +#define MSR_FE0 0x00000800 +#define MSR_DE 0x00000200 +#define MSR_FE1 0x00000100 +#define MSR_IS 0x00000020 +#define MSR_DS 0x00000010 +#define MSR_RI 0x00000002 +/** @} */ + +/*===========================================================================*/ +/* Module pre-compile time settings. */ +/*===========================================================================*/ + +/* + * TLB default settings. + */ +#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0)) +#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K) +#define TLB0_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE) +#define TLB0_MAS3 (MAS3_RPN(0x40000000) | \ + MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ + MAS3_UR | MAS3_SR) + +#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1)) +#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M) +#define TLB1_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE) +#define TLB1_MAS3 (MAS3_RPN(0x00000000) | \ + MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \ + MAS3_UR | MAS3_SR) + +#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2)) +#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I) +#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3)) +#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I) +#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4)) +#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M) +#define TLB4_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I) +#define TLB4_MAS3 (MAS3_RPN(0xFFF00000) | \ + MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR) + +/* + * BUCSR default settings. + */ +#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \ + BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI) +#endif + +/* + * LICSR1 default settings. + */ +#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG) +#endif + +/* + * MSR default settings. + */ +#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) +#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME) +#endif + +/* + * Boot default settings. + */ +#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) +#define BOOT_PERFORM_CORE_INIT 1 +#endif + +/* + * VLE mode default settings. + */ +#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) +#define BOOT_USE_VLE 1 +#endif + +/* + * RAM relocation flag. + */ +#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) +#define BOOT_RELOCATE_IN_RAM 0 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Module inline functions. */ +/*===========================================================================*/ + +#endif /* _BOOT_H_ */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC564Axx/boot.s b/os/common/ports/e200/devices/SPC564Axx/boot.s new file mode 100644 index 000000000..ef7e4df91 --- /dev/null +++ b/os/common/ports/e200/devices/SPC564Axx/boot.s @@ -0,0 +1,353 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPC564Axx/boot.s + * @brief SPC564Axx boot-related code. + * + * @addtogroup PPC_BOOT + * @{ + */ + +#include "boot.h" + +#if !defined(__DOXYGEN__) + + /* BAM record.*/ + .section .boot, "ax" + +#if BOOT_USE_VLE + .long 0x015A0000 +#else + .long 0x005A0000 +#endif + .long _reset_address + + .align 2 + .globl _reset_address + .type _reset_address, @function +_reset_address: +#if BOOT_PERFORM_CORE_INIT + bl _coreinit +#endif + bl _ivinit + +#if BOOT_RELOCATE_IN_RAM + /* + * Image relocation in RAM. + */ + lis %r4, __ram_reloc_start__@h + ori %r4, %r4, __ram_reloc_start__@l + lis %r5, __ram_reloc_dest__@h + ori %r5, %r5, __ram_reloc_dest__@l + lis %r6, __ram_reloc_end__@h + ori %r6, %r6, __ram_reloc_end__@l +.relloop: + cmpl cr0, %r4, %r6 + bge cr0, .relend + lwz %r7, 0(%r4) + addi %r4, %r4, 4 + stw %r7, 0(%r5) + addi %r5, %r5, 4 + b .relloop +.relend: + lis %r3, _boot_address@h + ori %r3, %r3, _boot_address@l + mtctr %r3 + bctrl +#else + b _boot_address +#endif + +#if BOOT_PERFORM_CORE_INIT + .align 2 +_ramcode: + tlbwe + isync + blr + + .align 2 +_coreinit: + /* + * Invalidating all TLBs except TLB1. + */ + lis %r3, 0 + mtspr 625, %r3 /* MAS1 */ + mtspr 626, %r3 /* MAS2 */ + mtspr 627, %r3 /* MAS3 */ + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h + mtspr 624, %r3 /* MAS0 */ + tlbwe + + /* + * TLB0 allocated to internal RAM. + */ + lis %r3, TLB0_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB0_MAS1@h + ori %r3, %r3, TLB0_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB0_MAS2@h + ori %r3, %r3, TLB0_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB0_MAS3@h + ori %r3, %r3, TLB0_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB2 allocated to internal Peripherals Bridge A. + */ + lis %r3, TLB2_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB2_MAS1@h + ori %r3, %r3, TLB2_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB2_MAS2@h + ori %r3, %r3, TLB2_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB2_MAS3@h + ori %r3, %r3, TLB2_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB3 allocated to internal Peripherals Bridge B. + */ + lis %r3, TLB3_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB3_MAS1@h + ori %r3, %r3, TLB3_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB3_MAS2@h + ori %r3, %r3, TLB3_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB3_MAS3@h + ori %r3, %r3, TLB3_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * TLB4 allocated to on-platform peripherals. + */ + lis %r3, TLB4_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB4_MAS1@h + ori %r3, %r3, TLB4_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB4_MAS2@h + ori %r3, %r3, TLB4_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB4_MAS3@h + ori %r3, %r3, TLB4_MAS3@l + mtspr 627, %r3 /* MAS3 */ + tlbwe + + /* + * RAM clearing, this device requires a write to all RAM location in + * order to initialize the ECC detection hardware, this is going to + * slow down the startup but there is no way around. + */ + xor %r0, %r0, %r0 + xor %r1, %r1, %r1 + xor %r2, %r2, %r2 + xor %r3, %r3, %r3 + xor %r4, %r4, %r4 + xor %r5, %r5, %r5 + xor %r6, %r6, %r6 + xor %r7, %r7, %r7 + xor %r8, %r8, %r8 + xor %r9, %r9, %r9 + xor %r10, %r10, %r10 + xor %r11, %r11, %r11 + xor %r12, %r12, %r12 + xor %r13, %r13, %r13 + xor %r14, %r14, %r14 + xor %r15, %r15, %r15 + xor %r16, %r16, %r16 + xor %r17, %r17, %r17 + xor %r18, %r18, %r18 + xor %r19, %r19, %r19 + xor %r20, %r20, %r20 + xor %r21, %r21, %r21 + xor %r22, %r22, %r22 + xor %r23, %r23, %r23 + xor %r24, %r24, %r24 + xor %r25, %r25, %r25 + xor %r26, %r26, %r26 + xor %r27, %r27, %r27 + xor %r28, %r28, %r28 + xor %r29, %r29, %r29 + xor %r30, %r30, %r30 + xor %r31, %r31, %r31 + lis %r4, __ram_start__@h + ori %r4, %r4, __ram_start__@l + lis %r5, __ram_end__@h + ori %r5, %r5, __ram_end__@l +.cleareccloop: + cmpl %cr0, %r4, %r5 + bge %cr0, .cleareccend + stmw %r16, 0(%r4) + addi %r4, %r4, 64 + b .cleareccloop +.cleareccend: + + /* + * *Finally* the TLB1 is re-allocated to flash, note, the final phase + * is executed from RAM. + */ + lis %r3, TLB1_MAS0@h + mtspr 624, %r3 /* MAS0 */ + lis %r3, TLB1_MAS1@h + ori %r3, %r3, TLB1_MAS1@l + mtspr 625, %r3 /* MAS1 */ + lis %r3, TLB1_MAS2@h + ori %r3, %r3, TLB1_MAS2@l + mtspr 626, %r3 /* MAS2 */ + lis %r3, TLB1_MAS3@h + ori %r3, %r3, TLB1_MAS3@l + mtspr 627, %r3 /* MAS3 */ + mflr %r4 + lis %r6, _ramcode@h + ori %r6, %r6, _ramcode@l + lis %r7, 0x40010000@h + mtctr %r7 + lwz %r3, 0(%r6) + stw %r3, 0(%r7) + lwz %r3, 4(%r6) + stw %r3, 4(%r7) + lwz %r3, 8(%r6) + stw %r3, 8(%r7) + bctrl + mtlr %r4 + + /* + * Branch prediction enabled. + */ + li %r3, BOOT_BUCSR_DEFAULT + mtspr 1013, %r3 /* BUCSR */ + + /* + * Cache invalidated and then enabled. + */ + li %r3, LICSR1_ICINV + mtspr 1011, %r3 /* LICSR1 */ +.inv: mfspr %r3, 1011 /* LICSR1 */ + andi. %r3, %r3, LICSR1_ICINV + bne .inv + lis %r3, BOOT_LICSR1_DEFAULT@h + ori %r3, %r3, BOOT_LICSR1_DEFAULT@l + mtspr 1011, %r3 /* LICSR1 */ + + blr +#endif /* BOOT_PERFORM_CORE_INIT */ + + /* + * Exception vectors initialization. + */ + .align 2 +_ivinit: + /* MSR initialization.*/ + lis %r3, BOOT_MSR_DEFAULT@h + ori %r3, %r3, BOOT_MSR_DEFAULT@l + mtMSR %r3 + + /* IVPR initialization.*/ + lis %r3, __ivpr_base__@h + ori %r3, %r3, __ivpr_base__@l + mtIVPR %r3 + + /* IVORs initialization.*/ + lis %r3, _unhandled_exception@h + ori %r3, %r3, _unhandled_exception@l + + mtspr 400, %r3 /* IVOR0-15 */ + mtspr 401, %r3 + mtspr 402, %r3 + mtspr 403, %r3 + mtspr 404, %r3 + mtspr 405, %r3 + mtspr 406, %r3 + mtspr 407, %r3 + mtspr 408, %r3 + mtspr 409, %r3 + mtspr 410, %r3 + mtspr 411, %r3 + mtspr 412, %r3 + mtspr 413, %r3 + mtspr 414, %r3 + mtspr 415, %r3 + mtspr 528, %r3 /* IVOR32-34 */ + mtspr 529, %r3 + mtspr 530, %r3 + + blr + + .section .handlers, "ax" + + /* + * Unhandled exceptions handler. + */ + .weak _unhandled_exception + .type _unhandled_exception, @function +_unhandled_exception: + b _unhandled_exception + +#endif /* !defined(__DOXYGEN__) */ + +/** @} */ diff --git a/os/common/ports/e200/devices/SPC564Axx/ppcparams.h b/os/common/ports/e200/devices/SPC564Axx/ppcparams.h new file mode 100644 index 000000000..badc1a83b --- /dev/null +++ b/os/common/ports/e200/devices/SPC564Axx/ppcparams.h @@ -0,0 +1,77 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file SPC564Axx/ppcparams.h + * @brief PowerPC parameters for the SPC564Axx. + * + * @defgroup PPC_SPC564Axx SPC564Axx Specific Parameters + * @ingroup PPC_SPECIFIC + * @details This file contains the PowerPC specific parameters for the + * SPC564Axx platform. + * @{ + */ + +#ifndef _PPCPARAMS_H_ +#define _PPCPARAMS_H_ + +/** + * @brief PPC core model. + */ +#define PPC_VARIANT PPC_VARIANT_e200z4 + +/** + * @brief Number of writable bits in IVPR register. + */ +#define PPC_IVPR_BITS 16 + +/** + * @brief IVORx registers support. + */ +#define PPC_SUPPORTS_IVORS TRUE + +/** + * @brief Book E instruction set support. + */ +#define PPC_SUPPORTS_BOOKE TRUE + +/** + * @brief VLE instruction set support. + */ +#define PPC_SUPPORTS_VLE TRUE + +/** + * @brief Supports VLS Load/Store Multiple Volatile instructions. + */ +#define PPC_SUPPORTS_VLE_MULTI TRUE + +/** + * @brief Supports the decrementer timer. + */ +#define PPC_SUPPORTS_DECREMENTER TRUE + +/** + * @brief Number of interrupt sources. + */ +#define PPC_NUM_VECTORS 486 + +#endif /* _PPCPARAMS_H_ */ + +/** @} */ -- cgit v1.2.3