From 33a3c8f7324f05af4d83c8bb22f24bdb606bfa91 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sun, 15 Oct 2017 09:41:49 +0000 Subject: CMSIS update and cleanup. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10824 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/common/ext/CMSIS/ST/STM32L0xx/stm32l011xx.h | 5957 --------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l021xx.h | 6097 --------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l031xx.h | 6096 --------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l041xx.h | 6236 --------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l051xx.h | 6272 --------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l052xx.h | 7348 ------------------ os/common/ext/CMSIS/ST/STM32L0xx/stm32l053xx.h | 7508 ------------------ os/common/ext/CMSIS/ST/STM32L0xx/stm32l061xx.h | 6412 ---------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l062xx.h | 7488 ------------------ os/common/ext/CMSIS/ST/STM32L0xx/stm32l063xx.h | 7648 ------------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l071xx.h | 6505 ---------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l072xx.h | 7683 ------------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l073xx.h | 7845 ------------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l081xx.h | 6645 ---------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l082xx.h | 7823 ------------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l083xx.h | 7985 -------------------- os/common/ext/CMSIS/ST/STM32L0xx/stm32l0xx.h | 243 - .../ext/CMSIS/ST/STM32L0xx/system_stm32l0xx.h | 127 - 18 files changed, 111918 deletions(-) delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l011xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l021xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l031xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l041xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l051xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l052xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l053xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l061xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l062xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l063xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l071xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l072xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l073xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l081xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l082xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l083xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/stm32l0xx.h delete mode 100644 os/common/ext/CMSIS/ST/STM32L0xx/system_stm32l0xx.h (limited to 'os/common/ext/CMSIS/ST/STM32L0xx') diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l011xx.h b/os/common/ext/CMSIS/ST/STM32L0xx/stm32l011xx.h deleted file mode 100644 index dee9ae0c3..000000000 --- a/os/common/ext/CMSIS/ST/STM32L0xx/stm32l011xx.h +++ /dev/null @@ -1,5957 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l011xx.h - * @author MCD Application Team - * @version V1.7.1 - * @date 25-November-2016 - * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for stm32l011xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral's registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l011xx - * @{ - */ - -#ifndef __STM32L011xx_H -#define __STM32L011xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 0 /*!< STM32L0xx provides no MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l011xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l021xx - * @{ - */ - -#ifndef __STM32L021xx_H -#define __STM32L021xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 0 /*!< STM32L0xx provides no MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l021xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - AES_LPUART1_IRQn = 29, /*!< AES and LPUART1 Interrupts */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - -/** - * @brief AES hardware accelerator - */ - -typedef struct -{ - __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ - __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ - __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ - __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ - __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ - __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ - __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ - __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ - __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ - __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ - __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ -} AES_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l031xx - * @{ - */ - -#ifndef __STM32L031xx_H -#define __STM32L031xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 0 /*!< STM32L0xx provides no MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l031xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l041xx - * @{ - */ - -#ifndef __STM32L041xx_H -#define __STM32L041xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 0 /*!< STM32L0xx provides no MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l041xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - AES_LPUART1_IRQn = 29, /*!< AES and LPUART1 Interrupts */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - -/** - * @brief AES hardware accelerator - */ - -typedef struct -{ - __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ - __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ - __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ - __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ - __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ - __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ - __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ - __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ - __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ - __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ - __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ -} AES_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l051xx - * @{ - */ - -#ifndef __STM32L051xx_H -#define __STM32L051xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l051xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM6_IRQn = 17, /*!< TIM6 Interrupt */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l052xx - * @{ - */ - -#ifndef __STM32L052xx_H -#define __STM32L052xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l052xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ - USB_IRQn = 31, /*!< USB global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ - -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - uint32_t RESERVED0[6]; /*!< 0x14-0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - uint32_t RESERVED1; /*!< 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l053xx - * @{ - */ - -#ifndef __STM32L053xx_H -#define __STM32L053xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l053xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ - LCD_IRQn = 30, /*!< LCD Interrupt */ - USB_IRQn = 31, /*!< USB global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ - -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - uint32_t RESERVED0[6]; /*!< 0x14-0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - uint32_t RESERVED1; /*!< 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l061xx - * @{ - */ - -#ifndef __STM32L061xx_H -#define __STM32L061xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l061xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM6_IRQn = 17, /*!< TIM6 Interrupt */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - AES_LPUART1_IRQn = 29, /*!< AES and LPUART1 Interrupts */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - -/** - * @brief AES hardware accelerator - */ - -typedef struct -{ - __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ - __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ - __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ - __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ - __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ - __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ - __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ - __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ - __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ - __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ - __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ -} AES_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l062xx - * @{ - */ - -#ifndef __STM32L062xx_H -#define __STM32L062xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l062xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - AES_RNG_LPUART1_IRQn = 29, /*!< AES and RNG and LPUART1 Interrupts */ - USB_IRQn = 31, /*!< USB global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - -/** - * @brief AES hardware accelerator - */ - -typedef struct -{ - __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ - __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ - __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ - __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ - __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ - __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ - __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ - __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ - __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ - __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ - __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ -} AES_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ - -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - uint32_t RESERVED0[6]; /*!< 0x14-0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - uint32_t RESERVED1; /*!< 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l063xx - * @{ - */ - -#ifndef __STM32L063xx_H -#define __STM32L063xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l063xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - AES_RNG_LPUART1_IRQn = 29, /*!< AES and RNG and LPUART1 Interrupts */ - LCD_IRQn = 30, /*!< LCD Interrupt */ - USB_IRQn = 31, /*!< USB global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - -/** - * @brief AES hardware accelerator - */ - -typedef struct -{ - __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ - __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ - __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ - __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ - __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ - __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ - __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ - __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ - __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ - __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ - __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ -} AES_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ - -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - uint32_t RESERVED0[6]; /*!< 0x14-0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - uint32_t RESERVED1; /*!< 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l071xx - * @{ - */ - -#ifndef __STM32L071xx_H -#define __STM32L071xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l071xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM6_IRQn = 17, /*!< TIM6 Interrupt */ - TIM7_IRQn = 18, /*!< TIM7 Interrupt */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - I2C3_IRQn = 21, /*!< I2C3 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l072xx - * @{ - */ - -#ifndef __STM32L072xx_H -#define __STM32L072xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l072xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM7_IRQn = 18, /*!< TIM7 Interrupt */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - I2C3_IRQn = 21, /*!< I2C3 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ - USB_IRQn = 31, /*!< USB global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ - -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l073xx - * @{ - */ - -#ifndef __STM32L073xx_H -#define __STM32L073xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l073xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM7_IRQn = 18, /*!< TIM7 Interrupt */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - I2C3_IRQn = 21, /*!< I2C3 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ - LCD_IRQn = 30, /*!< LCD Interrupt */ - USB_IRQn = 31, /*!< USB global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ - -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l081xx - * @{ - */ - -#ifndef __STM32L081xx_H -#define __STM32L081xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l081xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_IRQn = 4, /*!< RCC Interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM6_IRQn = 17, /*!< TIM6 Interrupt */ - TIM7_IRQn = 18, /*!< TIM7 Interrupt */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - I2C3_IRQn = 21, /*!< I2C3 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - AES_LPUART1_IRQn = 29, /*!< AES and LPUART1 Interrupts */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - -/** - * @brief AES hardware accelerator - */ - -typedef struct -{ - __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ - __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ - __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ - __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ - __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ - __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ - __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ - __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ - __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ - __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ - __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ -} AES_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l082xx - * @{ - */ - -#ifndef __STM32L082xx_H -#define __STM32L082xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l082xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM7_IRQn = 18, /*!< TIM7 Interrupt */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - I2C3_IRQn = 21, /*!< I2C3 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - AES_RNG_LPUART1_IRQn = 29, /*!< AES and RNG and LPUART1 Interrupts */ - USB_IRQn = 31, /*!< USB global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - -/** - * @brief AES hardware accelerator - */ - -typedef struct -{ - __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ - __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ - __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ - __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ - __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ - __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ - __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ - __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ - __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ - __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ - __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ -} AES_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ - -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l083xx - * @{ - */ - -#ifndef __STM32L083xx_H -#define __STM32L083xx_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ -#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ -#define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ -#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ -#define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief stm32l083xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - -/*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ - -/****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ - DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM3_IRQn = 16, /*!< TIM3 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM7_IRQn = 18, /*!< TIM7 Interrupt */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - I2C3_IRQn = 21, /*!< I2C3 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - AES_RNG_LPUART1_IRQn = 29, /*!< AES and RNG and LPUART1 Interrupts */ - LCD_IRQn = 30, /*!< LCD Interrupt */ - USB_IRQn = 31, /*!< USB global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm0plus.h" -#include "system_stm32l0xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ - __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ - __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ - uint32_t RESERVED1; /*!< Reserved, 0x18 */ - uint32_t RESERVED2; /*!< Reserved, 0x1C */ - __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ - uint32_t RESERVED3; /*!< Reserved, 0x24 */ - __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ - uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ - __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ - __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; -} ADC_Common_TypeDef; - -/** - * @brief AES hardware accelerator - */ - -typedef struct -{ - __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ - __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ - __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ - __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ - __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ - __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ - __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ - __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ - __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ - __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ - __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ -} AES_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - - -/** -* @brief CRC calculation unit -*/ - -typedef struct -{ -__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ -__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ -uint8_t RESERVED0; /*!< Reserved, 0x05 */ -uint16_t RESERVED1; /*!< Reserved, 0x06 */ -__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -uint32_t RESERVED2; /*!< Reserved, 0x0C */ -__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ -__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Clock Recovery System - */ - -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
© COPYRIGHT(c) 2016 STMicroelectronics
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l0xx - * @{ - */ - -#ifndef __STM32L0xx_H -#define __STM32L0xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L0) -#define STM32L0 -#endif /* STM32L0 */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32L011xx) && !defined (STM32L021xx) && \ - !defined (STM32L031xx) && !defined (STM32L041xx) && \ - !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && \ - !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) && \ - !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && \ - !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) \ - /* #define STM32L011xx */ - /* #define STM32L021xx */ - /* #define STM32L031xx */ /*!< STM32L031C6, STM32L031E6, STM32L031F6, STM32L031G6, STM32L031K6 Devices */ - /* #define STM32L041xx */ /*!< STM32L041C6, STM32L041E6, STM32L041F6, STM32L041G6, STM32L041K6 Devices */ - /* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */ - /* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */ - /* #define STM32L053xx */ /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */ - /* #define STM32L061xx */ /*!< */ - /* #define STM32L062xx */ /*!< STM32L062K8 */ - /* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */ - /* #define STM32L071xx */ /*!< */ - /* #define STM32L072xx */ /*!< */ - /* #define STM32L073xx */ /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */ - /* #define STM32L081xx */ /*!< */ - /* #define STM32L082xx */ /*!< */ - /* #define STM32L083xx */ /*!< */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_HAL_DRIVER */ -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number V1.7.1 - */ -#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ -#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ -#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L0xx_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ -#if defined(STM32L011xx) - #include "stm32l011xx.h" -#elif defined(STM32L021xx) - #include "stm32l021xx.h" -#elif defined(STM32L031xx) - #include "stm32l031xx.h" -#elif defined(STM32L041xx) - #include "stm32l041xx.h" -#elif defined(STM32L051xx) - #include "stm32l051xx.h" -#elif defined(STM32L052xx) - #include "stm32l052xx.h" -#elif defined(STM32L053xx) - #include "stm32l053xx.h" -#elif defined(STM32L062xx) - #include "stm32l062xx.h" -#elif defined(STM32L063xx) - #include "stm32l063xx.h" -#elif defined(STM32L061xx) - #include "stm32l061xx.h" -#elif defined(STM32L071xx) - #include "stm32l071xx.h" -#elif defined(STM32L072xx) - #include "stm32l072xx.h" -#elif defined(STM32L073xx) - #include "stm32l073xx.h" -#elif defined(STM32L082xx) - #include "stm32l082xx.h" -#elif defined(STM32L083xx) - #include "stm32l083xx.h" -#elif defined(STM32L081xx) - #include "stm32l081xx.h" -#else - #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - ERROR = 0, - SUCCESS = !ERROR -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macro - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l0xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L0xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/os/common/ext/CMSIS/ST/STM32L0xx/system_stm32l0xx.h b/os/common/ext/CMSIS/ST/STM32L0xx/system_stm32l0xx.h deleted file mode 100644 index 64b85cbf1..000000000 --- a/os/common/ext/CMSIS/ST/STM32L0xx/system_stm32l0xx.h +++ /dev/null @@ -1,127 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l0xx.h - * @author MCD Application Team - * @version V1.7.1 - * @date 25-November-2016 - * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l0xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L0XX_H -#define __SYSTEM_STM32L0XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L0xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L0xx_System_Exported_types - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -/* -*/ -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ - - -/** - * @} - */ - -/** @addtogroup STM32L0xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L0xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L0xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L0XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -- cgit v1.2.3