From ef8caca39a1963d75376b4ae004b0426cc801792 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Fri, 28 Dec 2018 14:59:47 +0000 Subject: Dynamic DMA allocation for STM32H7xx. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12489 110e8d01-0319-4d1e-a829-52ad28d1bb01 --- demos/STM32/RT-STM32H743I-NUCLEO144/cfg/halconf.h | 2 +- demos/STM32/RT-STM32H743I-NUCLEO144/cfg/mcuconf.h | 84 +++++++++++------------ 2 files changed, 43 insertions(+), 43 deletions(-) (limited to 'demos') diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/cfg/halconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/cfg/halconf.h index 3974e6114..89be0946a 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/cfg/halconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/cfg/halconf.h @@ -44,7 +44,7 @@ * @brief Enables the ADC subsystem. */ #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) -#define HAL_USE_ADC TRUE +#define HAL_USE_ADC FALSE #endif /** diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/cfg/mcuconf.h index 18633380d..510f9a325 100644 --- a/demos/STM32/RT-STM32H743I-NUCLEO144/cfg/mcuconf.h +++ b/demos/STM32/RT-STM32H743I-NUCLEO144/cfg/mcuconf.h @@ -183,10 +183,10 @@ */ #define STM32_ADC_DUAL_MODE FALSE #define STM32_ADC_COMPACT_SAMPLES FALSE -#define STM32_ADC_USE_ADC12 TRUE +#define STM32_ADC_USE_ADC12 FALSE #define STM32_ADC_USE_ADC3 FALSE -#define STM32_ADC_ADC12_DMA_CHANNEL 0 -#define STM32_ADC_ADC3_DMA_CHANNEL 1 +#define STM32_ADC_ADC12_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_ADC_ADC3_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY #define STM32_ADC_ADC12_DMA_PRIORITY 2 #define STM32_ADC_ADC3_DMA_PRIORITY 2 #define STM32_ADC_ADC12_IRQ_PRIORITY 5 @@ -214,8 +214,8 @@ #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 -#define STM32_DAC_DAC1_CH1_DMA_CHANNEL 3 -#define STM32_DAC_DAC1_CH2_DMA_CHANNEL 4 +#define STM32_DAC_DAC1_CH1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_DAC_DAC1_CH2_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY /* * GPT driver system settings. @@ -253,14 +253,14 @@ #define STM32_I2C_USE_I2C3 FALSE #define STM32_I2C_USE_I2C4 FALSE #define STM32_I2C_BUSY_TIMEOUT 50 -#define STM32_I2C_I2C1_RX_DMA_CHANNEL 6 -#define STM32_I2C_I2C1_TX_DMA_CHANNEL 7 -#define STM32_I2C_I2C2_RX_DMA_CHANNEL 8 -#define STM32_I2C_I2C2_TX_DMA_CHANNEL 9 -#define STM32_I2C_I2C3_RX_DMA_CHANNEL 8 -#define STM32_I2C_I2C3_TX_DMA_CHANNEL 9 -#define STM32_I2C_I2C4_RX_BDMA_CHANNEL 0 -#define STM32_I2C_I2C4_TX_BDMA_CHANNEL 1 +#define STM32_I2C_I2C1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_I2C_I2C4_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY +#define STM32_I2C_I2C4_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY #define STM32_I2C_I2C1_IRQ_PRIORITY 5 #define STM32_I2C_I2C2_IRQ_PRIORITY 5 #define STM32_I2C_I2C3_IRQ_PRIORITY 5 @@ -335,7 +335,7 @@ #define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 #define STM32_SDC_SDMMC_READ_TIMEOUT 1000 #define STM32_SDC_SDMMC_CLOCK_DELAY 10 -#define STM32_SDC_SDMMC1_DMA_CHANNEL 5 +#define STM32_SDC_SDMMC1_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY #define STM32_SDC_SDMMC1_DMA_PRIORITY 3 #define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 @@ -368,18 +368,18 @@ #define STM32_SPI_USE_SPI4 FALSE #define STM32_SPI_USE_SPI5 FALSE #define STM32_SPI_USE_SPI6 FALSE -#define STM32_SPI_SPI1_RX_DMA_CHANNEL 10 -#define STM32_SPI_SPI1_TX_DMA_CHANNEL 11 -#define STM32_SPI_SPI2_RX_DMA_CHANNEL 12 -#define STM32_SPI_SPI2_TX_DMA_CHANNEL 13 -#define STM32_SPI_SPI3_RX_DMA_CHANNEL 10 -#define STM32_SPI_SPI3_TX_DMA_CHANNEL 11 -#define STM32_SPI_SPI4_RX_DMA_CHANNEL 12 -#define STM32_SPI_SPI4_TX_DMA_CHANNEL 13 -#define STM32_SPI_SPI5_RX_DMA_CHANNEL 12 -#define STM32_SPI_SPI5_TX_DMA_CHANNEL 13 -#define STM32_SPI_SPI6_RX_BDMA_CHANNEL 2 -#define STM32_SPI_SPI6_TX_BDMA_CHANNEL 3 +#define STM32_SPI_SPI1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_SPI_SPI6_RX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY +#define STM32_SPI_SPI6_TX_BDMA_CHANNEL STM32_BDMA_STREAM_ID_ANY #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 @@ -411,22 +411,22 @@ #define STM32_UART_USE_USART6 FALSE #define STM32_UART_USE_UART7 FALSE #define STM32_UART_USE_UART8 FALSE -#define STM32_UART_USART1_RX_DMA_CHANNEL 14 -#define STM32_UART_USART1_TX_DMA_CHANNEL 15 -#define STM32_UART_USART2_RX_DMA_CHANNEL 8 -#define STM32_UART_USART2_TX_DMA_CHANNEL 9 -#define STM32_UART_USART3_RX_DMA_CHANNEL 12 -#define STM32_UART_USART3_TX_DMA_CHANNEL 13 -#define STM32_UART_UART4_RX_DMA_CHANNEL 14 -#define STM32_UART_UART4_TX_DMA_CHANNEL 15 -#define STM32_UART_UART5_RX_DMA_CHANNEL 8 -#define STM32_UART_UART5_TX_DMA_CHANNEL 9 -#define STM32_UART_USART6_RX_DMA_CHANNEL 12 -#define STM32_UART_USART6_TX_DMA_CHANNEL 13 -#define STM32_UART_UART7_RX_DMA_CHANNEL 8 -#define STM32_UART_UART7_TX_DMA_CHANNEL 9 -#define STM32_UART_UART8_RX_DMA_CHANNEL 12 -#define STM32_UART_UART8_TX_DMA_CHANNEL 13 +#define STM32_UART_USART1_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART1_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART2_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART2_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART3_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART3_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART4_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART4_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART5_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART5_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART6_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_USART6_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART7_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART7_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART8_RX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY +#define STM32_UART_UART8_TX_DMA_CHANNEL STM32_DMA_STREAM_ID_ANY #define STM32_UART_USART1_IRQ_PRIORITY 12 #define STM32_UART_USART2_IRQ_PRIORITY 12 #define STM32_UART_USART3_IRQ_PRIORITY 12 -- cgit v1.2.3