From 4c76bcedf53a76c634f7729d882195845f938c12 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Wed, 16 Dec 2015 14:59:57 +0000 Subject: SDMMC1 now compilable on STM32L4. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8611 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM32/RT-STM32L476RG-NUCLEO/mcuconf.h | 43 +++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 5 deletions(-) (limited to 'demos/STM32') diff --git a/demos/STM32/RT-STM32L476RG-NUCLEO/mcuconf.h b/demos/STM32/RT-STM32L476RG-NUCLEO/mcuconf.h index 30097f65c..8cacd9a2a 100644 --- a/demos/STM32/RT-STM32L476RG-NUCLEO/mcuconf.h +++ b/demos/STM32/RT-STM32L476RG-NUCLEO/mcuconf.h @@ -65,13 +65,13 @@ #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK #define STM32_MCOPRE STM32_MCOPRE_DIV1 #define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK -#define STM32_PLLSAI1N_VALUE 80 +#define STM32_PLLSAI1N_VALUE 72 #define STM32_PLLSAI1P_VALUE 7 #define STM32_PLLSAI1Q_VALUE 6 -#define STM32_PLLSAI1R_VALUE 4 -#define STM32_PLLSAI2N_VALUE 80 +#define STM32_PLLSAI1R_VALUE 6 +#define STM32_PLLSAI2N_VALUE 72 #define STM32_PLLSAI2P_VALUE 7 -#define STM32_PLLSAI2R_VALUE 4 +#define STM32_PLLSAI2R_VALUE 6 #define STM32_USART1SEL STM32_USART1SEL_SYSCLK #define STM32_USART2SEL STM32_USART2SEL_SYSCLK #define STM32_USART3SEL STM32_USART3SEL_SYSCLK @@ -85,12 +85,45 @@ #define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1 #define STM32_SAI1SEL STM32_SAI1SEL_OFF #define STM32_SAI2SEL STM32_SAI2SEL_OFF -#define STM32_CLK48SEL STM32_CLK48SEL_PLL +#define STM32_CLK48SEL STM32_CLK48SEL_PLLSAI1 #define STM32_ADCSEL STM32_ADCSEL_SYSCLK #define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1 #define STM32_DFSDMSEL STM32_DFSDMSEL_PCLK1 #define STM32_RTCSEL STM32_RTCSEL_LSI +/* + * ADC driver system settings. + */ +#define STM32_ADC_DUAL_MODE FALSE +#define STM32_ADC_COMPACT_SAMPLES FALSE +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_ADC12_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_IRQ_PRIORITY 5 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5 +#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250 +#define STM32_SDC_SDMMC_READ_TIMEOUT 25 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) + /* * SERIAL driver system settings. */ -- cgit v1.2.3