From de3354237212038456fadffcc252b4365815634a Mon Sep 17 00:00:00 2001 From: gdisirio Date: Wed, 27 Jul 2011 12:22:07 +0000 Subject: Provisional STM32L1xx and STM32F2xx support. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3180 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/ST_STM3220G_EVAL/board.c | 58 +++++++++ boards/ST_STM3220G_EVAL/board.h | 245 +++++++++++++++++++++++++++++++++++++ boards/ST_STM3220G_EVAL/board.mk | 5 + boards/ST_STM32L_DISCOVERY/board.c | 12 +- boards/ST_STM32L_DISCOVERY/board.h | 28 +++++ 5 files changed, 342 insertions(+), 6 deletions(-) create mode 100644 boards/ST_STM3220G_EVAL/board.c create mode 100644 boards/ST_STM3220G_EVAL/board.h create mode 100644 boards/ST_STM3220G_EVAL/board.mk (limited to 'boards') diff --git a/boards/ST_STM3220G_EVAL/board.c b/boards/ST_STM3220G_EVAL/board.c new file mode 100644 index 000000000..efb8ef566 --- /dev/null +++ b/boards/ST_STM3220G_EVAL/board.c @@ -0,0 +1,58 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { +} diff --git a/boards/ST_STM3220G_EVAL/board.h b/boards/ST_STM3220G_EVAL/board.h new file mode 100644 index 000000000..e10a5203c --- /dev/null +++ b/boards/ST_STM3220G_EVAL/board.h @@ -0,0 +1,245 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM3220G-EVAL board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM3220G_EVAL +#define BOARD_NAME "ST STM3220G-EVAL" + +/* + * Board frequencies. + * NOTE: The HSE crystal is not fitted by default on the board. + */ +#define STM32_LSECLK 32768 +#define STM32_HSECLK 25000000 + +/* + * MCU type as defined in the ST header file stm32f2xx.h. + */ +#define STM32F2XX + +/* + * IO pins assignments. + */ + +#define GPIOA_WAKEUP_BUTTON 0 + +#define GPIOB_ETHER_INT 14 +#define GPIOB_NAND_INT 15 + +#define GPIOC_TAMPER_BUTTON 0 +#define GPIOC_LED4 7 + +#define GPIOF_POT 9 + +#define GPIOG_LED1 6 +#define GPIOG_LED2 8 +#define GPIOG_USER_BUTTON 15 + +#define GPIOH_EXPANDER_INT 12 +#define GPIOH_SD_DETECT 13 + +#define GPIOI_LED3 9 + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0 << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1 << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2 << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3 << ((n) * 2)) +#define PIN_OTYPE_PUSHPULL(n) (0 << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1 << (n)) +#define PIN_OSPEED_2M(n) (0 << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1 << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2 << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3 << ((n) * 2)) +#define PIN_PUDR_FLOATING(n) (0 << ((n) * 2)) +#define PIN_PUDR_PULLUP(n) (1 << ((n) * 2)) +#define PIN_PUDR_PULLDOWN(n) (2 << ((n) * 2)) +#define PIN_AFIO_AF0(n) (0 << ((n % 8) * 4)) +#define PIN_AFIO_AF1(n) (1 << ((n % 8) * 4)) +#define PIN_AFIO_AF2(n) (2 << ((n % 8) * 4)) +#define PIN_AFIO_AF3(n) (3 << ((n % 8) * 4)) +#define PIN_AFIO_AF4(n) (4 << ((n % 8) * 4)) +#define PIN_AFIO_AF5(n) (5 << ((n % 8) * 4)) +#define PIN_AFIO_AF6(n) (6 << ((n % 8) * 4)) +#define PIN_AFIO_AF7(n) (7 << ((n % 8) * 4)) +#define PIN_AFIO_AF8(n) (8 << ((n % 8) * 4)) +#define PIN_AFIO_AF9(n) (9 << ((n % 8) * 4)) +#define PIN_AFIO_AF10(n) (10 << ((n % 8) * 4)) +#define PIN_AFIO_AF11(n) (11 << ((n % 8) * 4)) +#define PIN_AFIO_AF12(n) (12 << ((n % 8) * 4)) +#define PIN_AFIO_AF13(n) (13 << ((n % 8) * 4)) +#define PIN_AFIO_AF14(n) (14 << ((n % 8) * 4)) +#define PIN_AFIO_AF15(n) (15 << ((n % 8) * 4)) + +/* + * Port A setup. + * All input with pull-up except: + * PA8 - MCO 1 (alternate 0). + * PA13 - JTMS/SWDAT (alternate 0). + * PA14 - JTCK/SWCLK (alternate 0). + * PA15 - JTDI (alternate 0). + */ +#define VAL_GPIOA_MODER (PIN_MODE_ALTERNATE(8) | \ + PIN_MODE_ALTERNATE(13) | \ + PIN_MODE_ALTERNATE(14) | \ + PIN_MODE_ALTERNATE(15)) +#define VAL_GPIOA_OTYPER 0x00000000 +#define VAL_GPIOA_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOA_PUPDR (PIN_PUDR_FLOATING(13) | \ + PIN_PUDR_FLOATING(14) | \ + PIN_PUDR_FLOATING(15)) +#define VAL_GPIOA_ODR 0xFFFFFFFF +#define VAL_GPIOA_AFRL 0x00000000 +#define VAL_GPIOA_AFRH 0x00000000 + +/* + * Port B setup. + * All input with pull-up except: + * PB3 - JTDO (alternate 0). + * PB4 - JNTRST (alternate 0). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(3) | \ + PIN_MODE_ALTERNATE(4)) +#define VAL_GPIOB_OTYPER 0x00000000 +#define VAL_GPIOB_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOB_PUPDR (~(PIN_PUDR_FLOATING(3) | \ + PIN_PUDR_FLOATING(4))) +#define VAL_GPIOB_ODR 0xFFFFFFFF +#define VAL_GPIOB_AFRL 0x00000000 +#define VAL_GPIOB_AFRH 0x00000000 + +/* + * Port C setup. + * All input with pull-up except: + * PC9 - MCO2 (alternate 0). + * PC10 - USART3_TX (alternate 7). + * PC11 - USART3_RX (alternate 7). + * PC14 - OSC32_INT (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ALTERNATE(9) | \ + PIN_MODE_ALTERNATE(10) | \ + PIN_MODE_ALTERNATE(11)) +#define VAL_GPIOC_OTYPER 0x00000000 +#define VAL_GPIOC_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOC_PUPDR (~(PIN_PUDR_PULLUP(11) | \ + PIN_PUDR_FLOATING(14) | \ + PIN_PUDR_FLOATING(15))) +#define VAL_GPIOC_ODR 0xFFFFFFFF +#define VAL_GPIOC_AFRL 0x00000000 +#define VAL_GPIOC_AFRH (PIN_AFIO_AF7(10) | \ + PIN_AFIO_AF7(11)) + +/* + * Port D setup. + * All input with pull-up. + */ +#define VAL_GPIOD_MODER 0x00000000 +#define VAL_GPIOD_OTYPER 0x00000000 +#define VAL_GPIOD_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOD_PUPDR 0xFFFFFFFF +#define VAL_GPIOD_ODR 0xFFFFFFFF +#define VAL_GPIOD_AFRL 0x00000000 +#define VAL_GPIOD_AFRH 0x00000000 + +/* + * Port E setup. + * All input with pull-up. + */ +#define VAL_GPIOE_MODER 0x00000000 +#define VAL_GPIOE_OTYPER 0x00000000 +#define VAL_GPIOE_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOE_PUPDR 0xFFFFFFFF +#define VAL_GPIOE_ODR 0xFFFFFFFF +#define VAL_GPIOE_AFRL 0x00000000 +#define VAL_GPIOE_AFRH 0x00000000 + +/* + * Port F setup. + * All input with pull-up. + */ +#define VAL_GPIOF_MODER 0x00000000 +#define VAL_GPIOF_OTYPER 0x00000000 +#define VAL_GPIOF_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOF_PUPDR 0xFFFFFFFF +#define VAL_GPIOF_ODR 0xFFFFFFFF +#define VAL_GPIOF_AFRL 0x00000000 +#define VAL_GPIOF_AFRH 0x00000000 + +/* + * Port G setup. + * All input with pull-up. + */ +#define VAL_GPIOG_MODER (PIN_MODE_OUTPUT(GPIOG_LED1)) +#define VAL_GPIOG_OTYPER 0x00000000 +#define VAL_GPIOG_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOG_PUPDR (~(PIN_PUDR_FLOATING(GPIOG_LED1))) +#define VAL_GPIOG_ODR 0xFFFFFFBF +#define VAL_GPIOG_AFRL 0x00000000 +#define VAL_GPIOG_AFRH 0x00000000 + +/* + * Port H setup. + * All input with pull-up. + */ +#define VAL_GPIOH_MODER 0x00000000 +#define VAL_GPIOH_OTYPER 0x00000000 +#define VAL_GPIOH_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOH_PUPDR 0xFFFFFFFF +#define VAL_GPIOH_ODR 0xFFFFFFFF +#define VAL_GPIOH_AFRL 0x00000000 +#define VAL_GPIOH_AFRH 0x00000000 + +/* + * Port I setup. + * All input with pull-up. + */ +#define VAL_GPIOI_MODER 0x00000000 +#define VAL_GPIOI_OTYPER 0x00000000 +#define VAL_GPIOI_OSPEEDR 0xFFFFFFFF +#define VAL_GPIOI_PUPDR 0xFFFFFFFF +#define VAL_GPIOI_ODR 0xFFFFFFFF +#define VAL_GPIOI_AFRL 0x00000000 +#define VAL_GPIOI_AFRH 0x00000000 + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/boards/ST_STM3220G_EVAL/board.mk b/boards/ST_STM3220G_EVAL/board.mk new file mode 100644 index 000000000..3121594a6 --- /dev/null +++ b/boards/ST_STM3220G_EVAL/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/ST_STM3220G_EVAL/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/ST_STM3220G_EVAL diff --git a/boards/ST_STM32L_DISCOVERY/board.c b/boards/ST_STM32L_DISCOVERY/board.c index 37015943a..4a93dada2 100644 --- a/boards/ST_STM32L_DISCOVERY/board.c +++ b/boards/ST_STM32L_DISCOVERY/board.c @@ -29,12 +29,12 @@ #if HAL_USE_PAL || defined(__DOXYGEN__) const PALConfig pal_default_config = { - {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR}, - {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR}, - {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR}, - {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR}, - {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR}, - {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR} + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH} }; #endif diff --git a/boards/ST_STM32L_DISCOVERY/board.h b/boards/ST_STM32L_DISCOVERY/board.h index ddad89b5e..d95480c15 100644 --- a/boards/ST_STM32L_DISCOVERY/board.h +++ b/boards/ST_STM32L_DISCOVERY/board.h @@ -69,6 +69,22 @@ #define PIN_PUDR_FLOATING(n) (0 << ((n) * 2)) #define PIN_PUDR_PULLUP(n) (1 << ((n) * 2)) #define PIN_PUDR_PULLDOWN(n) (2 << ((n) * 2)) +#define PIN_AFIO_AF0(n) (0 << ((n % 8) * 4)) +#define PIN_AFIO_AF1(n) (1 << ((n % 8) * 4)) +#define PIN_AFIO_AF2(n) (2 << ((n % 8) * 4)) +#define PIN_AFIO_AF3(n) (3 << ((n % 8) * 4)) +#define PIN_AFIO_AF4(n) (4 << ((n % 8) * 4)) +#define PIN_AFIO_AF5(n) (5 << ((n % 8) * 4)) +#define PIN_AFIO_AF6(n) (6 << ((n % 8) * 4)) +#define PIN_AFIO_AF7(n) (7 << ((n % 8) * 4)) +#define PIN_AFIO_AF8(n) (8 << ((n % 8) * 4)) +#define PIN_AFIO_AF9(n) (9 << ((n % 8) * 4)) +#define PIN_AFIO_AF10(n) (10 << ((n % 8) * 4)) +#define PIN_AFIO_AF11(n) (11 << ((n % 8) * 4)) +#define PIN_AFIO_AF12(n) (12 << ((n % 8) * 4)) +#define PIN_AFIO_AF13(n) (13 << ((n % 8) * 4)) +#define PIN_AFIO_AF14(n) (14 << ((n % 8) * 4)) +#define PIN_AFIO_AF15(n) (15 << ((n % 8) * 4)) /* * Port A setup. @@ -89,6 +105,8 @@ PIN_PUDR_FLOATING(14) | \ PIN_PUDR_FLOATING(15))) #define VAL_GPIOA_ODR 0xFFFFFFFF +#define VAL_GPIOA_AFRL 0x00000000 +#define VAL_GPIOA_AFRH 0x00000000 /* * Port B setup. @@ -109,6 +127,8 @@ PIN_PUDR_FLOATING(GPIOB_LED4) | \ PIN_PUDR_FLOATING(GPIOB_LED3))) #define VAL_GPIOB_ODR 0xFFFFFF3F +#define VAL_GPIOB_AFRL 0x00000000 +#define VAL_GPIOB_AFRH 0x00000000 /* * Port C setup. @@ -122,6 +142,8 @@ #define VAL_GPIOC_PUPDR (~(PIN_PUDR_FLOATING(15) | \ PIN_PUDR_FLOATING(14))) #define VAL_GPIOC_ODR 0xFFFFFFFF +#define VAL_GPIOC_AFRL 0x00000000 +#define VAL_GPIOC_AFRH 0x00000000 /* * Port D setup. @@ -132,6 +154,8 @@ #define VAL_GPIOD_OSPEEDR 0xFFFFFFFF #define VAL_GPIOD_PUPDR 0xFFFFFFFF #define VAL_GPIOD_ODR 0xFFFFFFFF +#define VAL_GPIOD_AFRL 0x00000000 +#define VAL_GPIOD_AFRH 0x00000000 /* * Port E setup. @@ -142,6 +166,8 @@ #define VAL_GPIOE_OSPEEDR 0xFFFFFFFF #define VAL_GPIOE_PUPDR 0xFFFFFFFF #define VAL_GPIOE_ODR 0xFFFFFFFF +#define VAL_GPIOE_AFRL 0x00000000 +#define VAL_GPIOE_AFRH 0x00000000 /* * Port H setup. @@ -152,6 +178,8 @@ #define VAL_GPIOH_OSPEEDR 0xFFFFFFFF #define VAL_GPIOH_PUPDR 0xFFFFFFFF #define VAL_GPIOH_ODR 0xFFFFFFFF +#define VAL_GPIOH_AFRL 0x00000000 +#define VAL_GPIOH_AFRH 0x00000000 #if !defined(_FROM_ASM_) #ifdef __cplusplus -- cgit v1.2.3