From fee14cb4ce565ed6c47c675a14cfb9480cb52886 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 6 Jan 2009 09:18:24 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@586 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- ports/ARMCM3/chcore.c | 354 ++++++++++++++++++++++----------------------- ports/ARMCM3/chcore.h | 386 ++++++++++++++++++++++++++++--------------------- src/templates/chcore.h | 11 +- 3 files changed, 399 insertions(+), 352 deletions(-) diff --git a/ports/ARMCM3/chcore.c b/ports/ARMCM3/chcore.c index ee868b1e3..68087b1b4 100644 --- a/ports/ARMCM3/chcore.c +++ b/ports/ARMCM3/chcore.c @@ -1,180 +1,174 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#include -#include - -/* - * System idle thread loop. - */ -__attribute__((weak)) -void _idle(void *p) { - - while (TRUE) { -#if ENABLE_WFI_IDLE != 0 - asm volatile ("wfi"); -#endif - } -} - -/* - * System console message (not implemented). - */ -__attribute__((weak)) -void chSysPuts(char *msg) { -} - -/* - * System halt. - */ -__attribute__((naked, weak)) -void chSysHalt(void) { - - asm volatile ("cpsid i"); - while (TRUE) { - } -} - -/* - * Start a thread by invoking its work function. - * - * Start a thread by calling its work function. If the work function returns, - * call chThdExit and chSysHalt. - */ -__attribute__((naked, weak)) -void threadstart(void) { - - asm volatile ("blx r1 \n\t" \ - "bl chThdExit \n\t" \ - "bl chSysHalt "); -} - -/* - * System Timer vector. - */ -void SysTickVector(void) { - - chSysIRQEnterI(); - chSysLock(); - - chSysTimerHandlerI(); - - chSysUnlock(); - chSysIRQExitI(); -} - -/* - * System invoked context switch. - */ -__attribute__((naked)) -void SVCallVector(Thread *otp, Thread *ntp) { - /* { r0 = otp, r1 = ntp } */ - /* get the BASEPRI in r3 */ - /* get the PSP in r12 */ - /* push the registers on the PSP stack */ - /* stores the modified PSP into the thread context */ - /* fetches the PSP position from the new thread context */ - /* pop the registers from the PSP stack */ - /* set the PSP from r12 */ - /* set the BASEPRI from R3 */ -#ifdef CH_CURRP_REGISTER_CACHE - asm volatile ("mrs r3, BASEPRI \n\t" \ - "mrs r12, PSP \n\t" \ - "stmdb r12!, {r3-r6,r8-r11, lr} \n\t" \ - "str r12, [r0, #16] \n\t" \ - "ldr r12, [r1, #16] \n\t" \ - "ldmia r12!, {r3-r6,r8-r11, lr} \n\t" \ - "msr PSP, r12 \n\t" \ - "msr BASEPRI, r3 \n\t" \ - "bx lr "); -#else - asm volatile ("mrs r3, BASEPRI \n\t" \ - "mrs r12, PSP \n\t" \ - "stmdb r12!, {r3-r11, lr} \n\t" \ - "str r12, [r0, #16] \n\t" \ - "ldr r12, [r1, #16] \n\t" \ - "ldmia r12!, {r3-r11, lr} \n\t" \ - "msr PSP, r12 \n\t" \ - "msr BASEPRI, r3 \n\t" \ - "bx lr "); -#endif -} - -#ifdef CH_CURRP_REGISTER_CACHE -#define PUSH_CONTEXT(sp) { \ - register uint32_t tmp asm ("r3") = BASEPRI_USER; \ - asm volatile ("mrs %0, PSP \n\t" \ - "stmdb %0!, {r3-r6,r8-r11, lr}" : \ - "=r" (sp) : "r" (sp), "r" (tmp)); \ -} - -#define POP_CONTEXT(sp) { \ - asm volatile ("ldmia %0!, {r3-r6,r8-r11, lr} \n\t" \ - "msr PSP, %0 \n\t" \ - "msr BASEPRI, r3 \n\t" \ - "bx lr" : "=r" (sp) : "r" (sp)); \ -} -#else -#define PUSH_CONTEXT(sp) { \ - register uint32_t tmp asm ("r3") = BASEPRI_USER; \ - asm volatile ("mrs %0, PSP \n\t" \ - "stmdb %0!, {r3-r11,lr}" : \ - "=r" (sp) : "r" (sp), "r" (tmp)); \ -} - -#define POP_CONTEXT(sp) { \ - asm volatile ("ldmia %0!, {r3-r11, lr} \n\t" \ - "msr PSP, %0 \n\t" \ - "msr BASEPRI, r3 \n\t" \ - "bx lr" : "=r" (sp) : "r" (sp)); \ -} -#endif - -/* - * Preemption invoked context switch. - */ -__attribute__((naked)) -void PendSVVector(void) { - Thread *otp; - register struct intctx *sp_thd asm("r12"); - - chSysLock(); - asm volatile ("push {lr}"); - if (!chSchRescRequiredI()) { - chSysUnlock(); - asm volatile ("pop {pc}"); - } - asm volatile ("pop {lr}"); - - PUSH_CONTEXT(sp_thd); - - (otp = currp)->p_ctx.r13 = sp_thd; - (currp = fifo_remove((void *)&rlist))->p_state = PRCURR; - chSchReadyI(otp); -#ifdef CH_USE_ROUNDROBIN - /* set the round-robin time quantum */ - rlist.r_preempt = CH_TIME_QUANTUM; -#endif -#ifdef CH_USE_TRACE - chDbgTrace(otp, currp); -#endif - sp_thd = currp->p_ctx.r13; - - POP_CONTEXT(sp_thd); -} +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @addtogroup ARMCM3_CORE + * @{ + */ + +#include +#include + +/** + * The default implementation of this function is void so no messages are + * actually printed. + * @note The function is declared as a weak symbol, it is possible to redefine + * it in your application code. + * @param msg pointer to the message string + */ +__attribute__((weak)) +void sys_puts(char *msg) { +} + +void sys_halt(void) { + + asm volatile ("cpsid i"); + while(TRUE) { + } +} + +/** + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. A call + * to @p chSysHalt() is added as failure check in the "impossible" case + * @p chThdExit() returns. + */ +__attribute__((naked, weak)) +void threadstart(void) { + + asm volatile ("blx r1 \n\t" \ + "bl chThdExit \n\t" \ + "bl chSysHalt "); +} + +/** + * System Timer vector. + * This interrupt is used as system tick. + * @note The timer is initialized in the board setup code. + */ +void SysTickVector(void) { + + chSysIRQEnterI(); + chSysLockI(); + chSysTimerHandlerI(); + chSysUnlockI(); + chSysIRQExitI(); +} + +/** + * The SVC vector is used for commanded context switch. + */ +__attribute__((naked)) +void SVCallVector(Thread *otp, Thread *ntp) { + /* { r0 = otp, r1 = ntp } */ + /* get the BASEPRI in r3 */ + /* get the PSP in r12 */ + /* push the registers on the PSP stack */ + /* stores the modified PSP into the thread context */ + /* fetches the PSP position from the new thread context */ + /* pop the registers from the PSP stack */ + /* set the PSP from r12 */ + /* set the BASEPRI from R3 */ +#ifdef CH_CURRP_REGISTER_CACHE + asm volatile ("mrs r3, BASEPRI \n\t" \ + "mrs r12, PSP \n\t" \ + "stmdb r12!, {r3-r6,r8-r11, lr} \n\t" \ + "str r12, [r0, #16] \n\t" \ + "ldr r12, [r1, #16] \n\t" \ + "ldmia r12!, {r3-r6,r8-r11, lr} \n\t" \ + "msr PSP, r12 \n\t" \ + "msr BASEPRI, r3 \n\t" \ + "bx lr "); +#else + asm volatile ("mrs r3, BASEPRI \n\t" \ + "mrs r12, PSP \n\t" \ + "stmdb r12!, {r3-r11, lr} \n\t" \ + "str r12, [r0, #16] \n\t" \ + "ldr r12, [r1, #16] \n\t" \ + "ldmia r12!, {r3-r11, lr} \n\t" \ + "msr PSP, r12 \n\t" \ + "msr BASEPRI, r3 \n\t" \ + "bx lr "); +#endif +} + +#ifdef CH_CURRP_REGISTER_CACHE +#define PUSH_CONTEXT(sp) { \ + register uint32_t tmp asm ("r3") = BASEPRI_USER; \ + asm volatile ("mrs %0, PSP \n\t" \ + "stmdb %0!, {r3-r6,r8-r11, lr}" : \ + "=r" (sp) : "r" (sp), "r" (tmp)); \ +} + +#define POP_CONTEXT(sp) { \ + asm volatile ("ldmia %0!, {r3-r6,r8-r11, lr} \n\t" \ + "msr PSP, %0 \n\t" \ + "msr BASEPRI, r3 \n\t" \ + "bx lr" : "=r" (sp) : "r" (sp)); \ +} +#else +#define PUSH_CONTEXT(sp) { \ + register uint32_t tmp asm ("r3") = BASEPRI_USER; \ + asm volatile ("mrs %0, PSP \n\t" \ + "stmdb %0!, {r3-r11,lr}" : \ + "=r" (sp) : "r" (sp), "r" (tmp)); \ +} + +#define POP_CONTEXT(sp) { \ + asm volatile ("ldmia %0!, {r3-r11, lr} \n\t" \ + "msr PSP, %0 \n\t" \ + "msr BASEPRI, r3 \n\t" \ + "bx lr" : "=r" (sp) : "r" (sp)); \ +} +#endif + +/** + * Preemption invoked context switch. + */ +__attribute__((naked)) +void PendSVVector(void) { + Thread *otp; + register struct intctx *sp_thd asm("r12"); + + chSysLockI(); + asm volatile ("push {lr}"); + if (!chSchRescRequiredI()) { + chSysUnlockI(); + asm volatile ("pop {pc}"); + } + asm volatile ("pop {lr}"); + + PUSH_CONTEXT(sp_thd); + + (otp = currp)->p_ctx.r13 = sp_thd; + (currp = fifo_remove((void *)&rlist))->p_state = PRCURR; + chSchReadyI(otp); +#ifdef CH_USE_ROUNDROBIN + /* set the round-robin time quantum */ + rlist.r_preempt = CH_TIME_QUANTUM; +#endif +#ifdef CH_USE_TRACE + chDbgTrace(otp, currp); +#endif + sp_thd = currp->p_ctx.r13; + + POP_CONTEXT(sp_thd); +} + +/** @} */ diff --git a/ports/ARMCM3/chcore.h b/ports/ARMCM3/chcore.h index d3ee658ba..cdd4a0625 100644 --- a/ports/ARMCM3/chcore.h +++ b/ports/ARMCM3/chcore.h @@ -1,168 +1,218 @@ -/* - ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . -*/ - -#ifndef _CHCORE_H_ -#define _CHCORE_H_ - -/* - * Port-related configuration parameters. - */ -#ifndef BASEPRI_USER -#define BASEPRI_USER 0 /* User level BASEPRI, 0 = disabled. */ -#endif - -#ifndef BASEPRI_KERNEL -#define BASEPRI_KERNEL 0x10 /* BASEPRI level within kernel lock. */ -#endif - -#ifndef ENABLE_WFI_IDLE -#define ENABLE_WFI_IDLE 0 /* Enables the use of the WFI ins. */ -#endif - -/* - * Macro defining the ARM Cortex-M3 architecture. - */ -#define CH_ARCHITECTURE_ARMCM3 - -/* - * 32 bit stack alignment. - */ -typedef uint32_t stkalign_t; - -/* - * Generic ARM register. - */ -typedef void *regarm_t; - -/* - * Interrupt saved context, empty in this architecture. - */ -struct extctx { -}; - -/* - * System saved context. - */ -struct intctx { - regarm_t basepri; - regarm_t r4; - regarm_t r5; - regarm_t r6; -#ifndef CH_CURRP_REGISTER_CACHE - regarm_t r7; -#endif - regarm_t r8; - regarm_t r9; - regarm_t r10; - regarm_t r11; - regarm_t lr_exc; - regarm_t r0; - regarm_t r1; - regarm_t r2; - regarm_t r3; - regarm_t r12; - regarm_t lr_thd; - regarm_t pc; - regarm_t xpsr; -}; - -/* - * Port dependent part of the Thread structure, you may add fields in - * this structure. - */ -typedef struct { - struct intctx *r13; -} Context; - -/* - * Platform dependent part of the \p chThdCreate() API. - * - * The top of the workspace is used for the intctx datastructure. - * - */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ - tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ - wsize - \ - sizeof(struct intctx)); \ - tp->p_ctx.r13->basepri = BASEPRI_USER; \ - tp->p_ctx.r13->lr_exc = (regarm_t)0xFFFFFFFD; \ - tp->p_ctx.r13->r0 = arg; \ - tp->p_ctx.r13->r1 = pf; \ - tp->p_ctx.r13->pc = threadstart; \ - tp->p_ctx.r13->xpsr = (regarm_t)0x01000000; \ -} - -#define chSysLock() { \ - register uint32_t tmp asm ("r3") = BASEPRI_KERNEL; \ - asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \ -} -#define chSysUnlock() { \ - register uint32_t tmp asm ("r3") = BASEPRI_USER; \ - asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \ -} -#define chSysEnable() { \ - register uint32_t tmp asm ("r3") = BASEPRI_USER; \ - asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \ -} -#define chSysSwitchI(otp, ntp) { \ - register Thread *_otp asm ("r0") = (otp); \ - register Thread *_ntp asm ("r1") = (ntp); \ - asm volatile ("svc #0" : : "r" (_otp), "r" (_ntp)); \ -} - -#ifndef INT_REQUIRED_STACK -#define INT_REQUIRED_STACK 0 /* NOTE: Always safe for this port. */ -#endif - -/* - * Enforces a 32 bit alignment for a stack area size value. - */ -#define STACK_ALIGN(n) ((((n) - 1) | sizeof(stkalign_t)) + 1) - -#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \ - sizeof(struct intctx) + \ - sizeof(struct extctx) + \ - (n) + \ - INT_REQUIRED_STACK) - -#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; - -/* called on each interrupt entry, currently nothing is done */ -#define chSysIRQEnterI() - -/* called on each interrupt exit, pends a supervisor handler for - * execution after all higher priority interrupts; PendSVVector() */ -#define chSysIRQExitI() { \ - SCB_ICSR = ICSR_PENDSVSET; \ -} - -#define IDLE_THREAD_STACK_SIZE 0 - -#ifdef __cplusplus -extern "C" { -#endif - void _idle(void *p) __attribute__((weak, noreturn)); - void chSysHalt(void); - void chSysPuts(char *msg); - void threadstart(void); -#ifdef __cplusplus -} -#endif - -#endif /* _CHCORE_H_ */ +/* + ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @addtogroup ARMCM3_CORE + * @{ + */ + +#ifndef _CHCORE_H_ +#define _CHCORE_H_ + +/* + * Port-related configuration parameters. + */ +#ifndef BASEPRI_USER +#define BASEPRI_USER 0 /* User level BASEPRI, 0 = disabled. */ +#endif + +#ifndef BASEPRI_KERNEL +#define BASEPRI_KERNEL 0x10 /* BASEPRI level within kernel lock. */ +#endif + +#ifndef ENABLE_WFI_IDLE +#define ENABLE_WFI_IDLE 0 /* Enables the use of the WFI ins. */ +#endif + +/** + * Macro defining the ARM Cortex-M3 architecture. + */ +#define CH_ARCHITECTURE_ARMCM3 + +/** + * 32 bit stack alignment. + */ +typedef uint32_t stkalign_t; + +/** + * Generic ARM register. + */ +typedef void *regarm_t; + +/** + * Interrupt saved context, empty in this architecture. + */ +struct extctx { +}; + +/** + * System saved context. + * This structure represents the inner stack frame during a context switching. + */ +struct intctx { + regarm_t basepri; + regarm_t r4; + regarm_t r5; + regarm_t r6; +#ifndef CH_CURRP_REGISTER_CACHE + regarm_t r7; +#endif + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t lr_exc; + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +}; + +/** + * Cortex-M3 context structure. + */ +typedef struct { + struct intctx *r13; +} Context; + +/** + * Platform dependent part of the @p chThdInit() API. + * This code usually setup the context switching frame represented by a + * @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->basepri = BASEPRI_USER; \ + tp->p_ctx.r13->lr_exc = (regarm_t)0xFFFFFFFD; \ + tp->p_ctx.r13->r0 = arg; \ + tp->p_ctx.r13->r1 = pf; \ + tp->p_ctx.r13->pc = threadstart; \ + tp->p_ctx.r13->xpsr = (regarm_t)0x01000000; \ +} + +/** + * The default idle thread implementation requires no extra stack space in + * this port. + */ +#ifndef IDLE_THREAD_STACK_SIZE +#define IDLE_THREAD_STACK_SIZE 0 +#endif + +/** + * This port requires no extra stack space for interrupt handling. + */ +#ifndef INT_REQUIRED_STACK +#define INT_REQUIRED_STACK 0 +#endif + +/** + * Enforces a correct alignment for a stack area size value. + */ +#define STACK_ALIGN(n) ((((n) - 1) | sizeof(stkalign_t)) + 1) + + /** + * Computes the thread working area global size. + */ +#define THD_WA_SIZE(n) StackAlign(sizeof(Thread) + \ + sizeof(struct intctx) + \ + sizeof(struct extctx) + \ + (n) + (INT_REQUIRED_STACK)) + +/** + * Macro used to allocate a thread working area aligned as both position and + * size. + */ +#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]; + +/** + * IRQ prologue code, inserted at the start of all IRQ handlers enabled to + * invoke system APIs. + */ +#define SYS_IRQ_PROLOGUE() + +/** + * IRQ epilogue code, inserted at the end of all IRQ handlers enabled to + * invoke system APIs. + */ +#define SYS_IRQ_EPILOGUE() { \ + SCB_ICSR = ICSR_PENDSVSET; \ +} + +/** + * This port function is implemented as inlined code for performance reasons. + */ +#define sys_disable() { \ + register uint32_t tmp asm ("r3") = BASEPRI_KERNEL; \ + asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \ +} + +/** + * This port function is implemented as inlined code for performance reasons. + */ +#define sys_enable() { \ + register uint32_t tmp asm ("r3") = BASEPRI_USER; \ + asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \ +} + +/** + * This port function is implemented as inlined code for performance reasons. + */ +#define sys_disable_from_isr() sys_disable() + +/** + * This port function is implemented as inlined code for performance reasons. + */ +#define sys_enable_from_isr() sys_enable() + +#define sys_wait_for_interrupt() { \ + asm volatile ("wfi"); \ +} + +/** + * This port function is implemented as inlined code for performance reasons. + */ +#define sys_switch(otp, ntp) { \ + register Thread *_otp asm ("r0") = (otp); \ + register Thread *_ntp asm ("r1") = (ntp); \ + asm volatile ("svc #0" : : "r" (_otp), "r" (_ntp)); \ +} + +/** + * IRQ handler function modifier. + */ +#define SYS_IRQ_HANDLER + +#ifdef __cplusplus +extern "C" { +#endif + void sys_puts(char *msg); + void sys_halt(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_H_ */ + +/** @} */ diff --git a/src/templates/chcore.h b/src/templates/chcore.h index 46d30a3aa..4e0aaf16a 100644 --- a/src/templates/chcore.h +++ b/src/templates/chcore.h @@ -62,12 +62,11 @@ typedef struct { } Context; /** - * Platform dependent part of the \p chThdCreate() API. + * Platform dependent part of the @p chThdCreate() API. * This code usually setup the context switching frame represented by a * @p intctx structure. */ -#define SETUP_CONTEXT(workspace, wsize, pf, arg) \ -{ \ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ } /** @@ -76,7 +75,9 @@ typedef struct { * thread should take no more space than those reserved * by @p INT_REQUIRED_STACK. */ +#ifndef IDLE_THREAD_STACK_SIZE #define IDLE_THREAD_STACK_SIZE 0 +#endif /** * Per-thread stack overhead for interrupts servicing, it is used in the @@ -85,7 +86,9 @@ typedef struct { * interrupt stack and the stack space between @p intctx and @p extctx is * known to be zero. */ +#ifndef INT_REQUIRED_STACK #define INT_REQUIRED_STACK 0 +#endif /** * Enforces a correct alignment for a stack area size value. @@ -113,7 +116,7 @@ typedef struct { #define SYS_IRQ_PROLOGUE() /** - * IRQ epilogue code, inserted at the start of all IRQ handlers enabled to + * IRQ epilogue code, inserted at the end of all IRQ handlers enabled to * invoke system APIs. */ #define SYS_IRQ_EPILOGUE() -- cgit v1.2.3