From ec8fcc30ca9be56cbc73255202cc91807f6aad85 Mon Sep 17 00:00:00 2001 From: roccomarco Date: Wed, 4 Jan 2017 16:04:34 +0000 Subject: Fixed Bug #809 git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10016 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F0xx/stm32_registry.h | 1 - readme.txt | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h index 5e8b6532a..028ac219b 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h @@ -250,7 +250,6 @@ #define STM32_HAS_TIM2 FALSE #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE diff --git a/readme.txt b/readme.txt index 58ad64157..6914ab199 100644 --- a/readme.txt +++ b/readme.txt @@ -153,6 +153,8 @@ - RT: Merged RT4. - NIL: Merged NIL2. - NIL: Added STM32F7 demo. +- HAL: Fixed redefined TIM in STM32F030 registry (bug #809) + (backported to 16.1.7). - HAL: Fixed clock init in STM32F0x port which doesn't take in account PLL_XTPRE and PREDIV_0 are hard-wired (bug #808) (backported to 16.1.7). -- cgit v1.2.3