From e1613c5169d7c792015d6a0bd2224626873af4e2 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Fri, 11 Apr 2008 14:39:49 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@259
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 demos/ARMCM3-STM32F103-GCC/board.c | 19 +++----------------
 demos/ARMCM3-STM32F103-GCC/board.h | 18 ++++++++++--------
 demos/ARMCM3-STM32F103-GCC/main.c  |  6 ++++++
 ports/ARMCM3/chcore.c              |  6 +++---
 ports/ARMCM3/crt0.s                |  2 ++
 5 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/demos/ARMCM3-STM32F103-GCC/board.c b/demos/ARMCM3-STM32F103-GCC/board.c
index 631a13e0c..1323030f0 100644
--- a/demos/ARMCM3-STM32F103-GCC/board.c
+++ b/demos/ARMCM3-STM32F103-GCC/board.c
@@ -22,20 +22,6 @@
 
 #include "board.h"
 
-/*
- * Wait states setting is a function of the system clock. Those are the
- * recommended values, there should not be need to change them.
- */
-#if SYSCLK <= 24000000
-#define FLASHBITS 0x00000010
-#else
-#if SYSCLK <= 48000000
-#define FLASHBITS 0x00000011
-#else
-#define FLASHBITS 0x00000012
-#endif
-#endif
-
 /*
  * Hardware initialization goes here.
  * NOTE: Interrupts are still disabled.
@@ -89,7 +75,7 @@ void hwinit(void) {
   GPIOD->CRL = VAL_GPIODCRL;
   GPIOD->CRH = VAL_GPIODCRH;
   GPIOD->ODR = VAL_GPIODODR;
-
+#if 0
   /*
    * NVIC/SCB initialization.
    */
@@ -98,8 +84,9 @@ void hwinit(void) {
   /*
    * SysTick initialization.
    */
-  SCB_SHPR(2) = 0x10 << 24;     // SysTick at priority 1:0 (highest - 1).
+  SCB_SHPR(2) = 0x80 << 24;     // SysTick at priority 8:0.
   ST_RVR = SYSCLK / (8000000 / CH_FREQUENCY) - 1;
   ST_CVR = 0;
   ST_CSR = ENABLE_ON_BITS | TICKINT_ENABLED_BITS | CLKSOURCE_EXT_BITS;
+#endif
 }
diff --git a/demos/ARMCM3-STM32F103-GCC/board.h b/demos/ARMCM3-STM32F103-GCC/board.h
index fa47168ed..a1a0080ef 100644
--- a/demos/ARMCM3-STM32F103-GCC/board.h
+++ b/demos/ARMCM3-STM32F103-GCC/board.h
@@ -41,9 +41,9 @@
 #define HSICLK          8000000
 #define PLLPRE          1
 #ifdef SYSCLK_48
-#define PLLMUL          6
+  #define PLLMUL        6
 #else
-#define PLLMUL          9
+  #define PLLMUL        9
 #endif
 #define PLLCLK          ((HSECLK / PLLPRE) * PLLMUL)
 #define SYSCLK          PLLCLK
@@ -52,14 +52,16 @@
 #define AHB1CLK         (SYSCLK / 1)
 
 /*
- * Values derived from clock settings.
+ * Values derived from the clock settings.
  */
 #define PLLPREBITS      ((PLLPRE - 1) << 17)
 #define PLLMULBITS      ((PLLMUL - 2) << 18)
 #ifdef SYSCLK_48
-#define USBPREBITS      USBPRE_DIV1_BITS
+  #define USBPREBITS    USBPRE_DIV1_BITS
+  #define FLASHBITS     0x00000011
 #else
-#define USBPREBITS      USBPRE_DIV1P5_BITS
+  #define USBPREBITS    USBPRE_DIV1P5_BITS
+  #define FLASHBITS     0x00000012
 #endif
 
 /*
@@ -81,9 +83,9 @@
  * Definitions for RCC_CFGR register.
  */
 #define CFGR_SW_MASK            (0x3 << 0)
-#define   SW_HSI_BITS           (0 << 2)
-#define   SW_HSE_BITS           (1 << 2)
-#define   SW_PLL_BITS           (2 << 2)
+#define   SW_HSI_BITS           (0 << 0)
+#define   SW_HSE_BITS           (1 << 0)
+#define   SW_PLL_BITS           (2 << 0)
 #define CFGR_SWS_MASK           (0x3 << 2)
 #define   SWS_HSI_BITS          (0 << 2)
 #define   SWS_HSE_BITS          (1 << 2)
diff --git a/demos/ARMCM3-STM32F103-GCC/main.c b/demos/ARMCM3-STM32F103-GCC/main.c
index 60e53abd3..99a1c085e 100644
--- a/demos/ARMCM3-STM32F103-GCC/main.c
+++ b/demos/ARMCM3-STM32F103-GCC/main.c
@@ -19,6 +19,8 @@
 
 #include <ch.h>
 
+#include "board.h"
+
 /*
  * Red LEDs blinker thread, times are in milliseconds.
  */
@@ -36,6 +38,10 @@ static msg_t Thread1(void *arg) {
  */
 int main(int argc, char **argv) {
 
+  GPIOC->BRR = GPIOC_LED;
+  while(1)
+    ;
+
   /*
    * The main() function becomes a thread here then the interrupts are
    * enabled and ChibiOS/RT goes live.
diff --git a/ports/ARMCM3/chcore.c b/ports/ARMCM3/chcore.c
index ea33f62eb..d691cee20 100644
--- a/ports/ARMCM3/chcore.c
+++ b/ports/ARMCM3/chcore.c
@@ -95,10 +95,10 @@ void chSysIRQExitI(void) {
 
   asm volatile ("mrs     r0, PSP                                \n\t" \
                 "ldr     r1, =retaddr                           \n\t" \
-                "ldr     r2, [r0, #18]                          \n\t" \
+                "ldr     r2, [r0, #24]                          \n\t" \
                 "str     r2, [r1]                               \n\t" \
                 "ldr     r1, =threadswitch                      \n\t" \
-                "str     r1, [r0, #18]                          ");
+                "str     r1, [r0, #24]                          ");
       return; /* Note, returns *without* re-enabling interrupts.*/
     }
   }
@@ -106,7 +106,7 @@ void chSysIRQExitI(void) {
 }
 
 /*
- * This code is execute in thread mode when exiting from an ISR routine that
+ * This code is executed in thread mode when exiting from an ISR routine that
  * requires rescheduling.
  */
 __attribute__((naked, weak))
diff --git a/ports/ARMCM3/crt0.s b/ports/ARMCM3/crt0.s
index 8be43d6a3..75be93753 100644
--- a/ports/ARMCM3/crt0.s
+++ b/ports/ARMCM3/crt0.s
@@ -33,6 +33,8 @@
 /*
  * Reset handler.
  */
+.thumb
+.thumb_func
 .global ResetHandler
 ResetHandler:
         /*
-- 
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