From e01b1f1f1eeff80a2670e0c7d52619e7dd5a85e2 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 8 Jan 2011 13:40:44 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2617 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvopt | 1904 ++++++++++++++++++++++++ demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj | 1010 +++++++++++++ os/ports/IAR/ARMCMx/chcore_v6m.h | 4 +- os/ports/IAR/ARMCMx/chcoreasm_v6m.s | 4 - os/ports/RVCT/ARMCMx/chcore_v6m.c | 56 + os/ports/RVCT/ARMCMx/chcore_v6m.h | 250 ++++ os/ports/RVCT/ARMCMx/chcoreasm_v6m.s | 130 ++ os/ports/RVCT/ARMCMx/cstartup.s | 3 +- 8 files changed, 3354 insertions(+), 7 deletions(-) create mode 100644 demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvopt create mode 100644 demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvproj create mode 100644 os/ports/RVCT/ARMCMx/chcore_v6m.c create mode 100644 os/ports/RVCT/ARMCMx/chcore_v6m.h create mode 100644 os/ports/RVCT/ARMCMx/chcoreasm_v6m.s diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvopt b/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvopt new file mode 100644 index 000000000..ad6bc133e --- /dev/null +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/keil/ch.uvopt @@ -0,0 +1,1904 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
+ + + + Demo + 0x4 + ARM-ADS + + + LPC1114x302 + NXP (founded by Philips) + IRAM(0x10000000-0x10001FFF) IROM(0-0x7FFF) CLOCK(12000000) CPUTYPE("Cortex-M0") + + "STARTUP\NXP\LPC11xx\startup_LPC11xx.s" ("NXP LPC11xx Startup Code") + UL2CM3(-UV1742AOE -O463 -S0 -C0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC1xxx_32 -FS00 -FL08000) + 5376 + LPC11xx.h + + + + + + + + + + + 0 + + + + NXP\LPC11xx\ + NXP\LPC11xx\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + ch + 1 + 0 + 0 + 1 + 1 + .\lst\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DARMP1.DLL + -pLPC1114 + SARMCM3.DLL + + TARMP1.DLL + -pLPC1114 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + + 0 + 8 + + + + + + + + + + + + + + STLink\ST-LINKIII-KEIL.dll + + + + + 1 + 0 + 0 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..\;..\..\..\os\kernel\include;..\..\..\os\ports\RVCT\ARMCMx;..\..\..\os\ports\RVCT\ARMCMx\LPC11xx;..\..\..\os\hal\include;..\..\..\os\hal\platforms\LPC11xx;..\..\..\boards\EA_LPCXPRESSO_BB_1114;..\..\..\test + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\..\..\boards\EA_LPCXPRESSO_BB_1114;..\..\..\os\ports\RVCT\ARMCMx\LPC11xx + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + board + + + board.c + 1 + ..\..\..\boards\EA_LPCXPRESSO_BB_1114\board.c + + + board.h + 5 + ..\..\..\boards\EA_LPCXPRESSO_BB_1114\board.h + + + + + port + + + cstartup.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\cstartup.s + + + chcore.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.c + + + nvic.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\nvic.c + + + chcore.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore.h + + + chtypes.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chtypes.h + + + nvic.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\nvic.h + + + chcore_v6m.c + 1 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v6m.c + + + chcore_v6m.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\chcore_v6m.h + + + chcoreasm_v6m.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\chcoreasm_v6m.s + + + cmparams.h + 5 + ..\..\..\os\ports\RVCT\ARMCMx\LPC11xx\cmparams.h + + + vectors.s + 2 + ..\..\..\os\ports\RVCT\ARMCMx\LPC11xx\vectors.s + + + + + kernel + + + chcond.c + 1 + ..\..\..\os\kernel\src\chcond.c + + + chdebug.c + 1 + ..\..\..\os\kernel\src\chdebug.c + + + chdynamic.c + 1 + ..\..\..\os\kernel\src\chdynamic.c + + + chevents.c + 1 + ..\..\..\os\kernel\src\chevents.c + + + chheap.c + 1 + ..\..\..\os\kernel\src\chheap.c + + + chlists.c + 1 + ..\..\..\os\kernel\src\chlists.c + + + chmboxes.c + 1 + ..\..\..\os\kernel\src\chmboxes.c + + + chmemcore.c + 1 + ..\..\..\os\kernel\src\chmemcore.c + + + chmempools.c + 1 + ..\..\..\os\kernel\src\chmempools.c + + + chmsg.c + 1 + ..\..\..\os\kernel\src\chmsg.c + + + chmtx.c + 1 + ..\..\..\os\kernel\src\chmtx.c + + + chqueues.c + 1 + ..\..\..\os\kernel\src\chqueues.c + + + chregistry.c + 1 + ..\..\..\os\kernel\src\chregistry.c + + + chschd.c + 1 + ..\..\..\os\kernel\src\chschd.c + + + chsem.c + 1 + ..\..\..\os\kernel\src\chsem.c + + + chsys.c + 1 + ..\..\..\os\kernel\src\chsys.c + + + chthreads.c + 1 + ..\..\..\os\kernel\src\chthreads.c + + + chvt.c + 1 + ..\..\..\os\kernel\src\chvt.c + + + ch.h + 5 + ..\..\..\os\kernel\include\ch.h + + + chbsem.h + 5 + ..\..\..\os\kernel\include\chbsem.h + + + chcond.h + 5 + ..\..\..\os\kernel\include\chcond.h + + + chdebug.h + 5 + ..\..\..\os\kernel\include\chdebug.h + + + chdynamic.h + 5 + ..\..\..\os\kernel\include\chdynamic.h + + + chevents.h + 5 + ..\..\..\os\kernel\include\chevents.h + + + chfiles.h + 5 + ..\..\..\os\kernel\include\chfiles.h + + + chheap.h + 5 + ..\..\..\os\kernel\include\chheap.h + + + chinline.h + 5 + ..\..\..\os\kernel\include\chinline.h + + + chioch.h + 5 + ..\..\..\os\kernel\include\chioch.h + + + chlists.h + 5 + ..\..\..\os\kernel\include\chlists.h + + + chmboxes.h + 5 + ..\..\..\os\kernel\include\chmboxes.h + + + chmemcore.h + 5 + ..\..\..\os\kernel\include\chmemcore.h + + + chmempools.h + 5 + ..\..\..\os\kernel\include\chmempools.h + + + chmsg.h + 5 + ..\..\..\os\kernel\include\chmsg.h + + + chmtx.h + 5 + ..\..\..\os\kernel\include\chmtx.h + + + chqueues.h + 5 + ..\..\..\os\kernel\include\chqueues.h + + + chregistry.h + 5 + ..\..\..\os\kernel\include\chregistry.h + + + chschd.h + 5 + ..\..\..\os\kernel\include\chschd.h + + + chsem.h + 5 + ..\..\..\os\kernel\include\chsem.h + + + chstreams.h + 5 + ..\..\..\os\kernel\include\chstreams.h + + + chsys.h + 5 + ..\..\..\os\kernel\include\chsys.h + + + chthreads.h + 5 + ..\..\..\os\kernel\include\chthreads.h + + + chvt.h + 5 + ..\..\..\os\kernel\include\chvt.h + + + + + hal + + + adc.c + 1 + ..\..\..\os\hal\src\adc.c + + + can.c + 1 + ..\..\..\os\hal\src\can.c + + + hal.c + 1 + ..\..\..\os\hal\src\hal.c + + + i2c.c + 1 + ..\..\..\os\hal\src\i2c.c + + + mac.c + 1 + ..\..\..\os\hal\src\mac.c + + + mmc_spi.c + 1 + ..\..\..\os\hal\src\mmc_spi.c + + + pal.c + 1 + ..\..\..\os\hal\src\pal.c + + + pwm.c + 1 + ..\..\..\os\hal\src\pwm.c + + + serial.c + 1 + ..\..\..\os\hal\src\serial.c + + + spi.c + 1 + ..\..\..\os\hal\src\spi.c + + + uart.c + 1 + ..\..\..\os\hal\src\uart.c + + + adc.h + 5 + ..\..\..\os\hal\include\adc.h + + + can.h + 5 + ..\..\..\os\hal\include\can.h + + + hal.h + 5 + ..\..\..\os\hal\include\hal.h + + + i2c.h + 5 + ..\..\..\os\hal\include\i2c.h + + + mac.h + 5 + ..\..\..\os\hal\include\mac.h + + + mii.h + 5 + ..\..\..\os\hal\include\mii.h + + + mmc_spi.h + 5 + ..\..\..\os\hal\include\mmc_spi.h + + + pal.h + 5 + ..\..\..\os\hal\include\pal.h + + + pwm.h + 5 + ..\..\..\os\hal\include\pwm.h + + + serial.h + 5 + ..\..\..\os\hal\include\serial.h + + + spi.h + 5 + ..\..\..\os\hal\include\spi.h + + + uart.h + 5 + ..\..\..\os\hal\include\uart.h + + + + + platform + + + core_cm0.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\core_cm0.h + + + hal_lld.c + 1 + ..\..\..\os\hal\platforms\LPC11xx\hal_lld.c + + + hal_lld.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\hal_lld.h + + + LPC11xx.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\LPC11xx.h + + + pal_lld.c + 1 + ..\..\..\os\hal\platforms\LPC11xx\pal_lld.c + + + pal_lld.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\pal_lld.h + + + serial_lld.c + 1 + ..\..\..\os\hal\platforms\LPC11xx\serial_lld.c + + + serial_lld.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\serial_lld.h + + + spi_lld.c + 1 + ..\..\..\os\hal\platforms\LPC11xx\spi_lld.c + + + spi_lld.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\spi_lld.h + + + system_LPC11xx.h + 5 + ..\..\..\os\hal\platforms\LPC11xx\system_LPC11xx.h + + + + + test + + + test.c + 1 + ..\..\..\test\test.c + + + testbmk.c + 1 + ..\..\..\test\testbmk.c + + + testdyn.c + 1 + ..\..\..\test\testdyn.c + + + testevt.c + 1 + ..\..\..\test\testevt.c + + + testheap.c + 1 + ..\..\..\test\testheap.c + + + testmbox.c + 1 + ..\..\..\test\testmbox.c + + + testmsg.c + 1 + ..\..\..\test\testmsg.c + + + testmtx.c + 1 + ..\..\..\test\testmtx.c + + + testpools.c + 1 + ..\..\..\test\testpools.c + + + testqueues.c + 1 + ..\..\..\test\testqueues.c + + + testsem.c + 1 + ..\..\..\test\testsem.c + + + testthd.c + 1 + ..\..\..\test\testthd.c + + + test.h + 5 + ..\..\..\test\test.h + + + testbmk.h + 5 + ..\..\..\test\testbmk.h + + + testdyn.h + 5 + ..\..\..\test\testdyn.h + + + testevt.h + 5 + ..\..\..\test\testevt.h + + + testheap.h + 5 + ..\..\..\test\testheap.h + + + testmbox.h + 5 + ..\..\..\test\testmbox.h + + + testmsg.h + 5 + ..\..\..\test\testmsg.h + + + testmtx.h + 5 + ..\..\..\test\testmtx.h + + + testpools.h + 5 + ..\..\..\test\testpools.h + + + testqueues.h + 5 + ..\..\..\test\testqueues.h + + + testsem.h + 5 + ..\..\..\test\testsem.h + + + testthd.h + 5 + ..\..\..\test\testthd.h + + + + + demo + + + main.c + 1 + ..\main.c + + + chconf.h + 5 + ..\chconf.h + + + halconf.h + 5 + ..\halconf.h + + + mcuconf.h + 5 + ..\mcuconf.h + + + + + + + + diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.h b/os/ports/IAR/ARMCMx/chcore_v6m.h index fe6c68a92..9209fbaf4 100644 --- a/os/ports/IAR/ARMCMx/chcore_v6m.h +++ b/os/ports/IAR/ARMCMx/chcore_v6m.h @@ -190,12 +190,12 @@ struct intctx { /** * @brief Disables all the interrupt sources. */ -#define port_disable() __enable_interrupt() +#define port_disable() __disable_interrupt() /** * @brief Disables the interrupt sources below kernel-level priority. */ -#define port_suspend() __enable_interrupt() +#define port_suspend() __disable_interrupt() /** * @brief Enables all the interrupt sources. diff --git a/os/ports/IAR/ARMCMx/chcoreasm_v6m.s b/os/ports/IAR/ARMCMx/chcoreasm_v6m.s index c9ee6a0c8..5f0887960 100644 --- a/os/ports/IAR/ARMCMx/chcoreasm_v6m.s +++ b/os/ports/IAR/ARMCMx/chcoreasm_v6m.s @@ -30,10 +30,6 @@ #define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS)) -#ifndef CORTEX_PRIORITY_SVCALL -#define CORTEX_PRIORITY_SVCALL 1 -#endif - EXTCTX_SIZE SET 32 CONTEXT_OFFSET SET 12 diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.c b/os/ports/RVCT/ARMCMx/chcore_v6m.c new file mode 100644 index 000000000..6340df81c --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcore_v6m.c @@ -0,0 +1,56 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/chcore_v6m.c + * @brief ARMv6-M architecture port code. + * + * @addtogroup RVCT_ARMCMx_V6M_CORE + * @{ + */ + +#include "ch.h" + +/** + * @brief PC register temporary storage. + */ +regarm_t _port_saved_pc; + +/** + * @brief IRQ nesting counter. + */ +unsigned _port_irq_nesting; + +/** + * @brief System Timer vector. + * @details This interrupt is used as system tick. + * @note The timer must be initialized in the startup code. + */ +CH_IRQ_HANDLER(SysTickVector) { + + CH_IRQ_PROLOGUE(); + + chSysLockFromIsr(); + chSysTimerHandlerI(); + chSysUnlockFromIsr(); + + CH_IRQ_EPILOGUE(); +} + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.h b/os/ports/RVCT/ARMCMx/chcore_v6m.h new file mode 100644 index 000000000..796b7f22e --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcore_v6m.h @@ -0,0 +1,250 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file RVCT/ARMCMx/chcore_v6m.h + * @brief ARMv6-M architecture port macros and structures. + * + * @addtogroup RVCT_ARMCMx_V6M_CORE + * @{ + */ + +#ifndef _CHCORE_V6M_H_ +#define _CHCORE_V6M_H_ + +/*===========================================================================*/ +/* Port implementation part. */ +/*===========================================================================*/ + +/** + * @brief Cortex-Mx exception context. + */ +struct cmxctx { + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t r12; + regarm_t lr_thd; + regarm_t pc; + regarm_t xpsr; +}; + +#if !defined(__DOXYGEN__) +struct extctx { + regarm_t xpsr; + regarm_t r12; + regarm_t lr; + regarm_t r0; + regarm_t r1; + regarm_t r2; + regarm_t r3; + regarm_t pc; +}; + +struct intctx { + regarm_t r8; + regarm_t r9; + regarm_t r10; + regarm_t r11; + regarm_t r4; + regarm_t r5; + regarm_t r6; + regarm_t r7; + regarm_t lr; +}; +#endif + +/** + * @brief Platform dependent part of the @p chThdInit() API. + * @details This code usually setup the context switching frame represented + * by an @p intctx structure. + */ +#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \ + tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \ + wsize - \ + sizeof(struct intctx)); \ + tp->p_ctx.r13->r4 = (void *)pf; \ + tp->p_ctx.r13->r5 = arg; \ + tp->p_ctx.r13->lr = (void *)_port_thread_start; \ +} + +/** + * @brief Stack size for the system idle thread. + * @details This size depends on the idle thread implementation, usually + * the idle thread should take no more space than those reserved + * by @p INT_REQUIRED_STACK. + * @note In this port it is set to 8 because the idle thread does have + * a stack frame when compiling without optimizations. You may + * reduce this value to zero when compiling with optimizations. + */ +#ifndef IDLE_THREAD_STACK_SIZE +#define IDLE_THREAD_STACK_SIZE 8 +#endif + +/** + * @brief Per-thread stack overhead for interrupts servicing. + * @details This constant is used in the calculation of the correct working + * area size. + * This value can be zero on those architecture where there is a + * separate interrupt stack and the stack space between @p intctx and + * @p extctx is known to be zero. + * @note In this port it is conservatively set to 16 because the function + * @p chSchDoRescheduleI() can have a stack frame, expecially with + * compiler optimizations disabled. + */ +#ifndef INT_REQUIRED_STACK +#define INT_REQUIRED_STACK 16 +#endif + +/** + * @brief IRQ prologue code. + * @details This macro must be inserted at the start of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_PROLOGUE() { \ + port_lock_from_isr(); \ + _port_irq_nesting++; \ + port_unlock_from_isr(); \ +} + +/** + * @brief IRQ epilogue code. + * @details This macro must be inserted at the end of all IRQ handlers + * enabled to invoke system APIs. + */ +#define PORT_IRQ_EPILOGUE() _port_irq_epilogue() + +/** + * @brief IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_IRQ_HANDLER(id) void id(void) + +/** + * @brief Fast IRQ handler function declaration. + * @note @p id can be a function name or a vector number depending on the + * port implementation. + */ +#define PORT_FAST_IRQ_HANDLER(id) void id(void) + +/** + * @brief Port-related initialization code. + */ +#define port_init() { \ + _port_irq_nesting = 0; \ + SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0); \ + NVICSetSystemHandlerPriority(HANDLER_SYSTICK, \ + CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SYSTICK)); \ +} + +/** + * @brief Kernel-lock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + */ +#define port_lock() __disable_irq() + +/** + * @brief Kernel-unlock action. + * @details Usually this function just disables interrupts but may perform + * more actions. + */ +#define port_unlock() __enable_irq() + +/** + * @brief Kernel-lock action from an interrupt handler. + * @details This function is invoked before invoking I-class APIs from + * interrupt handlers. The implementation is architecture dependent, + * in its simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_lock_from_isr() port_lock() + +/** + * @brief Kernel-unlock action from an interrupt handler. + * @details This function is invoked after invoking I-class APIs from interrupt + * handlers. The implementation is architecture dependent, in its + * simplest form it is void. + * @note Same as @p port_lock() in this port. + */ +#define port_unlock_from_isr() port_unlock() + +/** + * @brief Disables all the interrupt sources. + */ +#define port_disable() __disable_irq() + +/** + * @brief Disables the interrupt sources below kernel-level priority. + */ +#define port_suspend() __disable_irq() + +/** + * @brief Enables all the interrupt sources. + */ +#define port_enable() __enable_irq() + +/** + * @brief Enters an architecture-dependent IRQ-waiting mode. + * @details The function is meant to return when an interrupt becomes pending. + * The simplest implementation is an empty function or macro but this + * would not take advantage of architecture-specific power saving + * modes. + * @note Implemented as an inlined @p WFI instruction. + */ +#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__) +#define port_wait_for_interrupt() __wfi() +#else +#define port_wait_for_interrupt() +#endif + +/** + * @brief Performs a context switch between two threads. + * @details This is the most critical code in any port, this function + * is responsible for the context switch between 2 threads. + * @note The implementation of this code affects directly the context + * switch performance so optimize here as much as you can. + * + * @param[in] ntp the thread to be switched in + * @param[in] otp the thread to be switched out + */ +#define port_switch(ntp, otp) _port_switch(ntp, otp) + +#if !defined(__DOXYGEN__) +extern regarm_t _port_saved_pc; +extern unsigned _port_irq_nesting; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void port_halt(void); + void _port_switch(Thread *ntp, Thread *otp); + void _port_irq_epilogue(void); + void _port_switch_from_isr(void); + void _port_thread_start(void); +#ifdef __cplusplus +} +#endif + +#endif /* _CHCORE_V6M_H_ */ + +/** @} */ diff --git a/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s new file mode 100644 index 000000000..e813d7eca --- /dev/null +++ b/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s @@ -0,0 +1,130 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * Imports the Cortex-Mx parameters header and performs the same calculations + * done in chcore.h. + */ +#include "cmparams.h" + +#define CORTEX_PRIORITY_MASK(n) ((n) << (8 - CORTEX_PRIORITY_BITS)) + +EXTCTX_SIZE EQU 32 +CONTEXT_OFFSET EQU 12 + + PRESERVE8 + THUMB + AREA |.text|, CODE, READONLY + + IMPORT chThdExit + IMPORT chSchIsRescRequiredExI + IMPORT chSchDoRescheduleI + IMPORT _port_saved_pc + IMPORT _port_irq_nesting + +/* + * Performs a context switch between two threads. + */ + EXPORT _port_switch +_port_switch PROC + push {r4, r5, r6, r7, lr} + mov r4, r8 + mov r5, r9 + mov r6, r10 + mov r7, r11 + push {r4, r5, r6, r7} + mov r3, sp + str r3, [r1, #CONTEXT_OFFSET] + ldr r3, [r0, #CONTEXT_OFFSET] + mov sp, r3 + pop {r4, r5, r6, r7} + mov r8, r4 + mov r9, r5 + mov r10, r6 + mov r11, r7 + pop {r4, r5, r6, r7, pc} + ENDP + +/* + * Start a thread by invoking its work function. + * If the work function returns @p chThdExit() is automatically invoked. + */ + EXPORT _port_thread_start +_port_thread_start PROC + cpsie i + mov r0, r5 + blx r4 + bl chThdExit + ENDP + +/* + * Post-IRQ switch code. + * Exception handlers return here for context switching. + */ + EXPORT _port_switch_from_isr +_port_switch_from_isr PROC + /* Note, saves r4 to make space for the PC.*/ + push {r0, r1, r2, r3, r4} + mrs r0, APSR + mov r1, r12 + push {r0, r1, lr} + ldr r0, =_port_saved_pc + ldr r0, [r0] + adds r0, r0, #1 + str r0, [sp, #28] + bl chSchDoRescheduleI + pop {r0, r1, r2} + mov r12, r1 + msr APSR, r0 + mov lr, r2 + cpsie i + pop {r0, r1, r2, r3, pc} + ENDP + +/* + * Reschedule verification and setup after an IRQ. + */ + EXPORT _port_irq_epilogue +_port_irq_epilogue PROC + push {r4, lr} + cpsid i + ldr r2, =_port_irq_nesting + ldr r3, [r2] + subs r3, r3, #1 + str r3, [r2] + cmp r3, #0 + beq skipexit + cpsie i + pop {r4, pc} +skipexit + bl chSchIsRescRequiredExI + cmp r0, #0 + beq notrequired + mrs r1, PSP + ldr r2, =_port_saved_pc + ldr r3, [r1, #24] + str r3, [r2] + ldr r3, =_port_switch_from_isr + str r3, [r1, #24] +notrequired + pop {r4, pc} + nop + ENDP + + END diff --git a/os/ports/RVCT/ARMCMx/cstartup.s b/os/ports/RVCT/ARMCMx/cstartup.s index 0d3a03f99..d0a8104a8 100644 --- a/os/ports/RVCT/ARMCMx/cstartup.s +++ b/os/ports/RVCT/ARMCMx/cstartup.s @@ -72,7 +72,8 @@ Reset_Handler PROC msr CONTROL, r0 isb bl __early_init - b __main + ldr r0, =__main + bx r0 ENDP __early_init PROC -- cgit v1.2.3